avr_device/devices/atmega328p/tc1/
timsk1.rs

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1#[doc = "Register `TIMSK1` reader"]
2pub struct R(crate::R<TIMSK1_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<TIMSK1_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<TIMSK1_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<TIMSK1_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `TIMSK1` writer"]
17pub struct W(crate::W<TIMSK1_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<TIMSK1_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<TIMSK1_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<TIMSK1_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `TOIE1` reader - Timer/Counter1 Overflow Interrupt Enable"]
38pub type TOIE1_R = crate::BitReader<bool>;
39#[doc = "Field `TOIE1` writer - Timer/Counter1 Overflow Interrupt Enable"]
40pub type TOIE1_W<'a, const O: u8> = crate::BitWriter<'a, u8, TIMSK1_SPEC, bool, O>;
41#[doc = "Field `OCIE1A` reader - Timer/Counter1 Output CompareA Match Interrupt Enable"]
42pub type OCIE1A_R = crate::BitReader<bool>;
43#[doc = "Field `OCIE1A` writer - Timer/Counter1 Output CompareA Match Interrupt Enable"]
44pub type OCIE1A_W<'a, const O: u8> = crate::BitWriter<'a, u8, TIMSK1_SPEC, bool, O>;
45#[doc = "Field `OCIE1B` reader - Timer/Counter1 Output CompareB Match Interrupt Enable"]
46pub type OCIE1B_R = crate::BitReader<bool>;
47#[doc = "Field `OCIE1B` writer - Timer/Counter1 Output CompareB Match Interrupt Enable"]
48pub type OCIE1B_W<'a, const O: u8> = crate::BitWriter<'a, u8, TIMSK1_SPEC, bool, O>;
49#[doc = "Field `ICIE1` reader - Timer/Counter1 Input Capture Interrupt Enable"]
50pub type ICIE1_R = crate::BitReader<bool>;
51#[doc = "Field `ICIE1` writer - Timer/Counter1 Input Capture Interrupt Enable"]
52pub type ICIE1_W<'a, const O: u8> = crate::BitWriter<'a, u8, TIMSK1_SPEC, bool, O>;
53impl R {
54    #[doc = "Bit 0 - Timer/Counter1 Overflow Interrupt Enable"]
55    #[inline(always)]
56    pub fn toie1(&self) -> TOIE1_R {
57        TOIE1_R::new((self.bits & 1) != 0)
58    }
59    #[doc = "Bit 1 - Timer/Counter1 Output CompareA Match Interrupt Enable"]
60    #[inline(always)]
61    pub fn ocie1a(&self) -> OCIE1A_R {
62        OCIE1A_R::new(((self.bits >> 1) & 1) != 0)
63    }
64    #[doc = "Bit 2 - Timer/Counter1 Output CompareB Match Interrupt Enable"]
65    #[inline(always)]
66    pub fn ocie1b(&self) -> OCIE1B_R {
67        OCIE1B_R::new(((self.bits >> 2) & 1) != 0)
68    }
69    #[doc = "Bit 5 - Timer/Counter1 Input Capture Interrupt Enable"]
70    #[inline(always)]
71    pub fn icie1(&self) -> ICIE1_R {
72        ICIE1_R::new(((self.bits >> 5) & 1) != 0)
73    }
74}
75impl W {
76    #[doc = "Bit 0 - Timer/Counter1 Overflow Interrupt Enable"]
77    #[inline(always)]
78    #[must_use]
79    pub fn toie1(&mut self) -> TOIE1_W<0> {
80        TOIE1_W::new(self)
81    }
82    #[doc = "Bit 1 - Timer/Counter1 Output CompareA Match Interrupt Enable"]
83    #[inline(always)]
84    #[must_use]
85    pub fn ocie1a(&mut self) -> OCIE1A_W<1> {
86        OCIE1A_W::new(self)
87    }
88    #[doc = "Bit 2 - Timer/Counter1 Output CompareB Match Interrupt Enable"]
89    #[inline(always)]
90    #[must_use]
91    pub fn ocie1b(&mut self) -> OCIE1B_W<2> {
92        OCIE1B_W::new(self)
93    }
94    #[doc = "Bit 5 - Timer/Counter1 Input Capture Interrupt Enable"]
95    #[inline(always)]
96    #[must_use]
97    pub fn icie1(&mut self) -> ICIE1_W<5> {
98        ICIE1_W::new(self)
99    }
100    #[doc = "Writes raw bits to the register."]
101    #[inline(always)]
102    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
103        self.0.bits(bits);
104        self
105    }
106}
107#[doc = "Timer/Counter Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [timsk1](index.html) module"]
108pub struct TIMSK1_SPEC;
109impl crate::RegisterSpec for TIMSK1_SPEC {
110    type Ux = u8;
111}
112#[doc = "`read()` method returns [timsk1::R](R) reader structure"]
113impl crate::Readable for TIMSK1_SPEC {
114    type Reader = R;
115}
116#[doc = "`write(|w| ..)` method takes [timsk1::W](W) writer structure"]
117impl crate::Writable for TIMSK1_SPEC {
118    type Writer = W;
119    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
120    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
121}
122#[doc = "`reset()` method sets TIMSK1 to value 0"]
123impl crate::Resettable for TIMSK1_SPEC {
124    const RESET_VALUE: Self::Ux = 0;
125}
avr_device/devices/atmega328p/tc1/timsk1.rs

avr_device/devices/atmega328p/tc1/
timsk1.rs
