avr_device/devices/attiny85/adc/
admux.rs

Help
1#[doc = "Register `ADMUX` reader"]
2pub struct R(crate::R<ADMUX_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<ADMUX_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<ADMUX_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<ADMUX_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `ADMUX` writer"]
17pub struct W(crate::W<ADMUX_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<ADMUX_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<ADMUX_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<ADMUX_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `MUX` reader - Analog Channel and Gain Selection Bits"]
38pub type MUX_R = crate::FieldReader<u8, MUX_A>;
39#[doc = "Analog Channel and Gain Selection Bits\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41#[repr(u8)]
42pub enum MUX_A {
43    #[doc = "0: Single-ended Input ADC0"]
44    ADC0 = 0,
45    #[doc = "1: Single-ended Input ADC1"]
46    ADC1 = 1,
47    #[doc = "2: Single-ended Input ADC2"]
48    ADC2 = 2,
49    #[doc = "3: Single-ended Input ADC3"]
50    ADC3 = 3,
51    #[doc = "4: Differential Inputs Positive ADC2 Negative ADC2 1x Gain"]
52    ADC2_ADC2_1X = 4,
53    #[doc = "5: Differential Inputs Positive ADC2 Negative ADC2 20x Gain"]
54    ADC2_ADC2_20X = 5,
55    #[doc = "6: Differential Inputs Positive ADC2 Negative ADC3 1x Gain"]
56    ADC2_ADC3_1X = 6,
57    #[doc = "7: Differential Inputs Positive ADC2 Negative ADC3 20x Gain"]
58    ADC2_ADC3_20X = 7,
59    #[doc = "8: Differential Inputs Positive ADC0 Negative ADC0 1x Gain"]
60    ADC0_ADC0_1X = 8,
61    #[doc = "9: Differential Inputs Positive ADC0 Negative ADC0 20x Gain"]
62    ADC0_ADC0_20X = 9,
63    #[doc = "10: Differential Inputs Positive ADC0 Negative ADC1 1x Gain"]
64    ADC0_ADC1_1X = 10,
65    #[doc = "11: Differential Inputs Positive ADC0 Negative ADC1 20x Gain"]
66    ADC0_ADC1_20X = 11,
67    #[doc = "12: Internal Reference (VBG)"]
68    ADC_VBG = 12,
69    #[doc = "13: 0V (GND)"]
70    ADC_GND = 13,
71    #[doc = "15: Temperature sensor"]
72    TEMPSENS = 15,
73}
74impl From<MUX_A> for u8 {
75    #[inline(always)]
76    fn from(variant: MUX_A) -> Self {
77        variant as _
78    }
79}
80impl MUX_R {
81    #[doc = "Get enumerated values variant"]
82    #[inline(always)]
83    pub fn variant(&self) -> Option<MUX_A> {
84        match self.bits {
85            0 => Some(MUX_A::ADC0),
86            1 => Some(MUX_A::ADC1),
87            2 => Some(MUX_A::ADC2),
88            3 => Some(MUX_A::ADC3),
89            4 => Some(MUX_A::ADC2_ADC2_1X),
90            5 => Some(MUX_A::ADC2_ADC2_20X),
91            6 => Some(MUX_A::ADC2_ADC3_1X),
92            7 => Some(MUX_A::ADC2_ADC3_20X),
93            8 => Some(MUX_A::ADC0_ADC0_1X),
94            9 => Some(MUX_A::ADC0_ADC0_20X),
95            10 => Some(MUX_A::ADC0_ADC1_1X),
96            11 => Some(MUX_A::ADC0_ADC1_20X),
97            12 => Some(MUX_A::ADC_VBG),
98            13 => Some(MUX_A::ADC_GND),
99            15 => Some(MUX_A::TEMPSENS),
100            _ => None,
101        }
102    }
103    #[doc = "Checks if the value of the field is `ADC0`"]
104    #[inline(always)]
105    pub fn is_adc0(&self) -> bool {
106        *self == MUX_A::ADC0
107    }
108    #[doc = "Checks if the value of the field is `ADC1`"]
109    #[inline(always)]
110    pub fn is_adc1(&self) -> bool {
111        *self == MUX_A::ADC1
112    }
113    #[doc = "Checks if the value of the field is `ADC2`"]
114    #[inline(always)]
115    pub fn is_adc2(&self) -> bool {
116        *self == MUX_A::ADC2
117    }
118    #[doc = "Checks if the value of the field is `ADC3`"]
119    #[inline(always)]
120    pub fn is_adc3(&self) -> bool {
121        *self == MUX_A::ADC3
122    }
123    #[doc = "Checks if the value of the field is `ADC2_ADC2_1X`"]
124    #[inline(always)]
125    pub fn is_adc2_adc2_1x(&self) -> bool {
126        *self == MUX_A::ADC2_ADC2_1X
127    }
128    #[doc = "Checks if the value of the field is `ADC2_ADC2_20X`"]
129    #[inline(always)]
130    pub fn is_adc2_adc2_20x(&self) -> bool {
131        *self == MUX_A::ADC2_ADC2_20X
132    }
133    #[doc = "Checks if the value of the field is `ADC2_ADC3_1X`"]
134    #[inline(always)]
135    pub fn is_adc2_adc3_1x(&self) -> bool {
136        *self == MUX_A::ADC2_ADC3_1X
137    }
138    #[doc = "Checks if the value of the field is `ADC2_ADC3_20X`"]
139    #[inline(always)]
140    pub fn is_adc2_adc3_20x(&self) -> bool {
141        *self == MUX_A::ADC2_ADC3_20X
142    }
143    #[doc = "Checks if the value of the field is `ADC0_ADC0_1X`"]
144    #[inline(always)]
145    pub fn is_adc0_adc0_1x(&self) -> bool {
146        *self == MUX_A::ADC0_ADC0_1X
147    }
148    #[doc = "Checks if the value of the field is `ADC0_ADC0_20X`"]
149    #[inline(always)]
150    pub fn is_adc0_adc0_20x(&self) -> bool {
151        *self == MUX_A::ADC0_ADC0_20X
152    }
153    #[doc = "Checks if the value of the field is `ADC0_ADC1_1X`"]
154    #[inline(always)]
155    pub fn is_adc0_adc1_1x(&self) -> bool {
156        *self == MUX_A::ADC0_ADC1_1X
157    }
158    #[doc = "Checks if the value of the field is `ADC0_ADC1_20X`"]
159    #[inline(always)]
160    pub fn is_adc0_adc1_20x(&self) -> bool {
161        *self == MUX_A::ADC0_ADC1_20X
162    }
163    #[doc = "Checks if the value of the field is `ADC_VBG`"]
164    #[inline(always)]
165    pub fn is_adc_vbg(&self) -> bool {
166        *self == MUX_A::ADC_VBG
167    }
168    #[doc = "Checks if the value of the field is `ADC_GND`"]
169    #[inline(always)]
170    pub fn is_adc_gnd(&self) -> bool {
171        *self == MUX_A::ADC_GND
172    }
173    #[doc = "Checks if the value of the field is `TEMPSENS`"]
174    #[inline(always)]
175    pub fn is_tempsens(&self) -> bool {
176        *self == MUX_A::TEMPSENS
177    }
178}
179#[doc = "Field `MUX` writer - Analog Channel and Gain Selection Bits"]
180pub type MUX_W<'a, const O: u8> = crate::FieldWriter<'a, u8, ADMUX_SPEC, u8, MUX_A, 4, O>;
181impl<'a, const O: u8> MUX_W<'a, O> {
182    #[doc = "Single-ended Input ADC0"]
183    #[inline(always)]
184    pub fn adc0(self) -> &'a mut W {
185        self.variant(MUX_A::ADC0)
186    }
187    #[doc = "Single-ended Input ADC1"]
188    #[inline(always)]
189    pub fn adc1(self) -> &'a mut W {
190        self.variant(MUX_A::ADC1)
191    }
192    #[doc = "Single-ended Input ADC2"]
193    #[inline(always)]
194    pub fn adc2(self) -> &'a mut W {
195        self.variant(MUX_A::ADC2)
196    }
197    #[doc = "Single-ended Input ADC3"]
198    #[inline(always)]
199    pub fn adc3(self) -> &'a mut W {
200        self.variant(MUX_A::ADC3)
201    }
202    #[doc = "Differential Inputs Positive ADC2 Negative ADC2 1x Gain"]
203    #[inline(always)]
204    pub fn adc2_adc2_1x(self) -> &'a mut W {
205        self.variant(MUX_A::ADC2_ADC2_1X)
206    }
207    #[doc = "Differential Inputs Positive ADC2 Negative ADC2 20x Gain"]
208    #[inline(always)]
209    pub fn adc2_adc2_20x(self) -> &'a mut W {
210        self.variant(MUX_A::ADC2_ADC2_20X)
211    }
212    #[doc = "Differential Inputs Positive ADC2 Negative ADC3 1x Gain"]
213    #[inline(always)]
214    pub fn adc2_adc3_1x(self) -> &'a mut W {
215        self.variant(MUX_A::ADC2_ADC3_1X)
216    }
217    #[doc = "Differential Inputs Positive ADC2 Negative ADC3 20x Gain"]
218    #[inline(always)]
219    pub fn adc2_adc3_20x(self) -> &'a mut W {
220        self.variant(MUX_A::ADC2_ADC3_20X)
221    }
222    #[doc = "Differential Inputs Positive ADC0 Negative ADC0 1x Gain"]
223    #[inline(always)]
224    pub fn adc0_adc0_1x(self) -> &'a mut W {
225        self.variant(MUX_A::ADC0_ADC0_1X)
226    }
227    #[doc = "Differential Inputs Positive ADC0 Negative ADC0 20x Gain"]
228    #[inline(always)]
229    pub fn adc0_adc0_20x(self) -> &'a mut W {
230        self.variant(MUX_A::ADC0_ADC0_20X)
231    }
232    #[doc = "Differential Inputs Positive ADC0 Negative ADC1 1x Gain"]
233    #[inline(always)]
234    pub fn adc0_adc1_1x(self) -> &'a mut W {
235        self.variant(MUX_A::ADC0_ADC1_1X)
236    }
237    #[doc = "Differential Inputs Positive ADC0 Negative ADC1 20x Gain"]
238    #[inline(always)]
239    pub fn adc0_adc1_20x(self) -> &'a mut W {
240        self.variant(MUX_A::ADC0_ADC1_20X)
241    }
242    #[doc = "Internal Reference (VBG)"]
243    #[inline(always)]
244    pub fn adc_vbg(self) -> &'a mut W {
245        self.variant(MUX_A::ADC_VBG)
246    }
247    #[doc = "0V (GND)"]
248    #[inline(always)]
249    pub fn adc_gnd(self) -> &'a mut W {
250        self.variant(MUX_A::ADC_GND)
251    }
252    #[doc = "Temperature sensor"]
253    #[inline(always)]
254    pub fn tempsens(self) -> &'a mut W {
255        self.variant(MUX_A::TEMPSENS)
256    }
257}
258#[doc = "Field `REFS2` reader - Reference Selection Bit 2"]
259pub type REFS2_R = crate::BitReader<bool>;
260#[doc = "Field `REFS2` writer - Reference Selection Bit 2"]
261pub type REFS2_W<'a, const O: u8> = crate::BitWriter<'a, u8, ADMUX_SPEC, bool, O>;
262#[doc = "Field `ADLAR` reader - Left Adjust Result"]
263pub type ADLAR_R = crate::BitReader<bool>;
264#[doc = "Field `ADLAR` writer - Left Adjust Result"]
265pub type ADLAR_W<'a, const O: u8> = crate::BitWriter<'a, u8, ADMUX_SPEC, bool, O>;
266#[doc = "Field `REFS` reader - Reference Selection Bits"]
267pub type REFS_R = crate::FieldReader<u8, REFS_A>;
268#[doc = "Reference Selection Bits\n\nValue on reset: 0"]
269#[derive(Clone, Copy, Debug, PartialEq, Eq)]
270#[repr(u8)]
271pub enum REFS_A {
272    #[doc = "0: Vcc used as Voltage Reference, disconnected from Aref"]
273    VCC = 0,
274    #[doc = "1: External Voltage Reference at AREF pin, Internal Voltage Reference turned off"]
275    AREF = 1,
276    #[doc = "2: Internal Voltage Reference (1.1V when REFS2 is cleared, 2.56V when REFS2 is set) without external bypass"]
277    INTERNAL = 2,
278    #[doc = "3: Internal 2.56V Voltage Reference with external bypass capacitor at AREF pin (REFS2 must be set)"]
279    INTERNAL_BYPASS = 3,
280}
281impl From<REFS_A> for u8 {
282    #[inline(always)]
283    fn from(variant: REFS_A) -> Self {
284        variant as _
285    }
286}
287impl REFS_R {
288    #[doc = "Get enumerated values variant"]
289    #[inline(always)]
290    pub fn variant(&self) -> REFS_A {
291        match self.bits {
292            0 => REFS_A::VCC,
293            1 => REFS_A::AREF,
294            2 => REFS_A::INTERNAL,
295            3 => REFS_A::INTERNAL_BYPASS,
296            _ => unreachable!(),
297        }
298    }
299    #[doc = "Checks if the value of the field is `VCC`"]
300    #[inline(always)]
301    pub fn is_vcc(&self) -> bool {
302        *self == REFS_A::VCC
303    }
304    #[doc = "Checks if the value of the field is `AREF`"]
305    #[inline(always)]
306    pub fn is_aref(&self) -> bool {
307        *self == REFS_A::AREF
308    }
309    #[doc = "Checks if the value of the field is `INTERNAL`"]
310    #[inline(always)]
311    pub fn is_internal(&self) -> bool {
312        *self == REFS_A::INTERNAL
313    }
314    #[doc = "Checks if the value of the field is `INTERNAL_BYPASS`"]
315    #[inline(always)]
316    pub fn is_internal_bypass(&self) -> bool {
317        *self == REFS_A::INTERNAL_BYPASS
318    }
319}
320#[doc = "Field `REFS` writer - Reference Selection Bits"]
321pub type REFS_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u8, ADMUX_SPEC, u8, REFS_A, 2, O>;
322impl<'a, const O: u8> REFS_W<'a, O> {
323    #[doc = "Vcc used as Voltage Reference, disconnected from Aref"]
324    #[inline(always)]
325    pub fn vcc(self) -> &'a mut W {
326        self.variant(REFS_A::VCC)
327    }
328    #[doc = "External Voltage Reference at AREF pin, Internal Voltage Reference turned off"]
329    #[inline(always)]
330    pub fn aref(self) -> &'a mut W {
331        self.variant(REFS_A::AREF)
332    }
333    #[doc = "Internal Voltage Reference (1.1V when REFS2 is cleared, 2.56V when REFS2 is set) without external bypass"]
334    #[inline(always)]
335    pub fn internal(self) -> &'a mut W {
336        self.variant(REFS_A::INTERNAL)
337    }
338    #[doc = "Internal 2.56V Voltage Reference with external bypass capacitor at AREF pin (REFS2 must be set)"]
339    #[inline(always)]
340    pub fn internal_bypass(self) -> &'a mut W {
341        self.variant(REFS_A::INTERNAL_BYPASS)
342    }
343}
344impl R {
345    #[doc = "Bits 0:3 - Analog Channel and Gain Selection Bits"]
346    #[inline(always)]
347    pub fn mux(&self) -> MUX_R {
348        MUX_R::new(self.bits & 0x0f)
349    }
350    #[doc = "Bit 4 - Reference Selection Bit 2"]
351    #[inline(always)]
352    pub fn refs2(&self) -> REFS2_R {
353        REFS2_R::new(((self.bits >> 4) & 1) != 0)
354    }
355    #[doc = "Bit 5 - Left Adjust Result"]
356    #[inline(always)]
357    pub fn adlar(&self) -> ADLAR_R {
358        ADLAR_R::new(((self.bits >> 5) & 1) != 0)
359    }
360    #[doc = "Bits 6:7 - Reference Selection Bits"]
361    #[inline(always)]
362    pub fn refs(&self) -> REFS_R {
363        REFS_R::new((self.bits >> 6) & 3)
364    }
365}
366impl W {
367    #[doc = "Bits 0:3 - Analog Channel and Gain Selection Bits"]
368    #[inline(always)]
369    #[must_use]
370    pub fn mux(&mut self) -> MUX_W<0> {
371        MUX_W::new(self)
372    }
373    #[doc = "Bit 4 - Reference Selection Bit 2"]
374    #[inline(always)]
375    #[must_use]
376    pub fn refs2(&mut self) -> REFS2_W<4> {
377        REFS2_W::new(self)
378    }
379    #[doc = "Bit 5 - Left Adjust Result"]
380    #[inline(always)]
381    #[must_use]
382    pub fn adlar(&mut self) -> ADLAR_W<5> {
383        ADLAR_W::new(self)
384    }
385    #[doc = "Bits 6:7 - Reference Selection Bits"]
386    #[inline(always)]
387    #[must_use]
388    pub fn refs(&mut self) -> REFS_W<6> {
389        REFS_W::new(self)
390    }
391    #[doc = "Writes raw bits to the register."]
392    #[inline(always)]
393    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
394        self.0.bits(bits);
395        self
396    }
397}
398#[doc = "The ADC multiplexer Selection Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [admux](index.html) module"]
399pub struct ADMUX_SPEC;
400impl crate::RegisterSpec for ADMUX_SPEC {
401    type Ux = u8;
402}
403#[doc = "`read()` method returns [admux::R](R) reader structure"]
404impl crate::Readable for ADMUX_SPEC {
405    type Reader = R;
406}
407#[doc = "`write(|w| ..)` method takes [admux::W](W) writer structure"]
408impl crate::Writable for ADMUX_SPEC {
409    type Writer = W;
410    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
411    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
412}
413#[doc = "`reset()` method sets ADMUX to value 0"]
414impl crate::Resettable for ADMUX_SPEC {
415    const RESET_VALUE: Self::Ux = 0;
416}
avr_device/devices/attiny85/adc/admux.rs

avr_device/devices/attiny85/adc/
admux.rs
