avr_device/home/runner/work/avr-hal/avr-hal/target/debug/build/avr-device-4ecd0f6dd31d9ace/out/pac/atmega328p.rs
1///Number available in the NVIC for configuring priority
2pub const NVIC_PRIO_BITS: u8 = 4;
3#[doc(hidden)]
4pub mod interrupt {
5 ///Enumeration of all the interrupts.
6 #[derive(Copy, Clone, Debug, PartialEq, Eq)]
7 #[repr(u16)]
8 pub enum Interrupt {
9 ///0 - External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset
10 RESET = 0,
11 ///1 - External Interrupt Request 0
12 INT0 = 1,
13 ///2 - External Interrupt Request 1
14 INT1 = 2,
15 ///3 - Pin Change Interrupt Request 0
16 PCINT0 = 3,
17 ///4 - Pin Change Interrupt Request 1
18 PCINT1 = 4,
19 ///5 - Pin Change Interrupt Request 2
20 PCINT2 = 5,
21 ///6 - Watchdog Time-out Interrupt
22 WDT = 6,
23 ///7 - Timer/Counter2 Compare Match A
24 TIMER2_COMPA = 7,
25 ///8 - Timer/Counter2 Compare Match B
26 TIMER2_COMPB = 8,
27 ///9 - Timer/Counter2 Overflow
28 TIMER2_OVF = 9,
29 ///10 - Timer/Counter1 Capture Event
30 TIMER1_CAPT = 10,
31 ///11 - Timer/Counter1 Compare Match A
32 TIMER1_COMPA = 11,
33 ///12 - Timer/Counter1 Compare Match B
34 TIMER1_COMPB = 12,
35 ///13 - Timer/Counter1 Overflow
36 TIMER1_OVF = 13,
37 ///14 - TimerCounter0 Compare Match A
38 TIMER0_COMPA = 14,
39 ///15 - TimerCounter0 Compare Match B
40 TIMER0_COMPB = 15,
41 ///16 - Timer/Couner0 Overflow
42 TIMER0_OVF = 16,
43 ///17 - SPI Serial Transfer Complete
44 SPI_STC = 17,
45 ///18 - USART Rx Complete
46 USART_RX = 18,
47 ///19 - USART, Data Register Empty
48 USART_UDRE = 19,
49 ///20 - USART Tx Complete
50 USART_TX = 20,
51 ///21 - ADC Conversion Complete
52 ADC = 21,
53 ///22 - EEPROM Ready
54 EE_READY = 22,
55 ///23 - Analog Comparator
56 ANALOG_COMP = 23,
57 ///24 - Two-wire Serial Interface
58 TWI = 24,
59 ///25 - Store Program Memory Read
60 SPM_READY = 25,
61 }
62 /// TryFromInterruptError
63 #[derive(Debug, Copy, Clone)]
64 pub struct TryFromInterruptError(());
65 impl Interrupt {
66 /// Attempt to convert a given value into an `Interrupt`
67 #[inline]
68 pub fn try_from(value: u8) -> Result<Self, TryFromInterruptError> {
69 match value {
70 0 => Ok(Interrupt::RESET),
71 1 => Ok(Interrupt::INT0),
72 2 => Ok(Interrupt::INT1),
73 3 => Ok(Interrupt::PCINT0),
74 4 => Ok(Interrupt::PCINT1),
75 5 => Ok(Interrupt::PCINT2),
76 6 => Ok(Interrupt::WDT),
77 7 => Ok(Interrupt::TIMER2_COMPA),
78 8 => Ok(Interrupt::TIMER2_COMPB),
79 9 => Ok(Interrupt::TIMER2_OVF),
80 10 => Ok(Interrupt::TIMER1_CAPT),
81 11 => Ok(Interrupt::TIMER1_COMPA),
82 12 => Ok(Interrupt::TIMER1_COMPB),
83 13 => Ok(Interrupt::TIMER1_OVF),
84 14 => Ok(Interrupt::TIMER0_COMPA),
85 15 => Ok(Interrupt::TIMER0_COMPB),
86 16 => Ok(Interrupt::TIMER0_OVF),
87 17 => Ok(Interrupt::SPI_STC),
88 18 => Ok(Interrupt::USART_RX),
89 19 => Ok(Interrupt::USART_UDRE),
90 20 => Ok(Interrupt::USART_TX),
91 21 => Ok(Interrupt::ADC),
92 22 => Ok(Interrupt::EE_READY),
93 23 => Ok(Interrupt::ANALOG_COMP),
94 24 => Ok(Interrupt::TWI),
95 25 => Ok(Interrupt::SPM_READY),
96 _ => Err(TryFromInterruptError(())),
97 }
98 }
99 }
100}
101pub use self::interrupt::Interrupt;
102///Analog Comparator
103pub type AC = crate::Periph<ac::RegisterBlock, 0x50>;
104impl core::fmt::Debug for AC {
105 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
106 f.debug_struct("AC").finish()
107 }
108}
109///Analog Comparator
110pub mod ac {
111 #[repr(C)]
112 ///Register block
113 pub struct RegisterBlock {
114 acsr: ACSR,
115 _reserved1: [u8; 0x2e],
116 didr1: DIDR1,
117 }
118 impl RegisterBlock {
119 ///0x00 - Analog Comparator Control And Status Register
120 #[inline(always)]
121 pub const fn acsr(&self) -> &ACSR {
122 &self.acsr
123 }
124 ///0x2f - Digital Input Disable Register 1
125 #[inline(always)]
126 pub const fn didr1(&self) -> &DIDR1 {
127 &self.didr1
128 }
129 }
130 /**ACSR (rw) register accessor: Analog Comparator Control And Status Register
131
132You can [`read`](crate::Reg::read) this register and get [`acsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`acsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
133
134For information about available fields see [`mod@acsr`] module*/
135 pub type ACSR = crate::Reg<acsr::ACSR_SPEC>;
136 ///Analog Comparator Control And Status Register
137 pub mod acsr {
138 ///Register `ACSR` reader
139 pub type R = crate::R<ACSR_SPEC>;
140 ///Register `ACSR` writer
141 pub type W = crate::W<ACSR_SPEC>;
142 /**Analog Comparator Interrupt Mode Select
143
144Value on reset: 0*/
145 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
146 #[repr(u8)]
147 pub enum ACIS_A {
148 ///0: Interrupt on Toggle
149 ON_TOGGLE = 0,
150 ///2: Interrupt on Falling Edge
151 ON_FALLING_EDGE = 2,
152 ///3: Interrupt on Rising Edge
153 ON_RISING_EDGE = 3,
154 }
155 impl From<ACIS_A> for u8 {
156 #[inline(always)]
157 fn from(variant: ACIS_A) -> Self {
158 variant as _
159 }
160 }
161 impl crate::FieldSpec for ACIS_A {
162 type Ux = u8;
163 }
164 impl crate::IsEnum for ACIS_A {}
165 ///Field `ACIS` reader - Analog Comparator Interrupt Mode Select
166 pub type ACIS_R = crate::FieldReader<ACIS_A>;
167 impl ACIS_R {
168 ///Get enumerated values variant
169 #[inline(always)]
170 pub const fn variant(&self) -> Option<ACIS_A> {
171 match self.bits {
172 0 => Some(ACIS_A::ON_TOGGLE),
173 2 => Some(ACIS_A::ON_FALLING_EDGE),
174 3 => Some(ACIS_A::ON_RISING_EDGE),
175 _ => None,
176 }
177 }
178 ///Interrupt on Toggle
179 #[inline(always)]
180 pub fn is_on_toggle(&self) -> bool {
181 *self == ACIS_A::ON_TOGGLE
182 }
183 ///Interrupt on Falling Edge
184 #[inline(always)]
185 pub fn is_on_falling_edge(&self) -> bool {
186 *self == ACIS_A::ON_FALLING_EDGE
187 }
188 ///Interrupt on Rising Edge
189 #[inline(always)]
190 pub fn is_on_rising_edge(&self) -> bool {
191 *self == ACIS_A::ON_RISING_EDGE
192 }
193 }
194 ///Field `ACIS` writer - Analog Comparator Interrupt Mode Select
195 pub type ACIS_W<'a, REG> = crate::FieldWriter<'a, REG, 2, ACIS_A>;
196 impl<'a, REG> ACIS_W<'a, REG>
197 where
198 REG: crate::Writable + crate::RegisterSpec,
199 REG::Ux: From<u8>,
200 {
201 ///Interrupt on Toggle
202 #[inline(always)]
203 pub fn on_toggle(self) -> &'a mut crate::W<REG> {
204 self.variant(ACIS_A::ON_TOGGLE)
205 }
206 ///Interrupt on Falling Edge
207 #[inline(always)]
208 pub fn on_falling_edge(self) -> &'a mut crate::W<REG> {
209 self.variant(ACIS_A::ON_FALLING_EDGE)
210 }
211 ///Interrupt on Rising Edge
212 #[inline(always)]
213 pub fn on_rising_edge(self) -> &'a mut crate::W<REG> {
214 self.variant(ACIS_A::ON_RISING_EDGE)
215 }
216 }
217 ///Field `ACIC` reader - Analog Comparator Input Capture Enable
218 pub type ACIC_R = crate::BitReader;
219 ///Field `ACIC` writer - Analog Comparator Input Capture Enable
220 pub type ACIC_W<'a, REG> = crate::BitWriter<'a, REG>;
221 ///Field `ACIE` reader - Analog Comparator Interrupt Enable
222 pub type ACIE_R = crate::BitReader;
223 ///Field `ACIE` writer - Analog Comparator Interrupt Enable
224 pub type ACIE_W<'a, REG> = crate::BitWriter<'a, REG>;
225 ///Field `ACI` reader - Analog Comparator Interrupt Flag
226 pub type ACI_R = crate::BitReader;
227 ///Field `ACI` writer - Analog Comparator Interrupt Flag
228 pub type ACI_W<'a, REG> = crate::BitWriter<'a, REG>;
229 ///Field `ACO` reader - Analog Compare Output
230 pub type ACO_R = crate::BitReader;
231 ///Field `ACBG` reader - Analog Comparator Bandgap Select
232 pub type ACBG_R = crate::BitReader;
233 ///Field `ACBG` writer - Analog Comparator Bandgap Select
234 pub type ACBG_W<'a, REG> = crate::BitWriter<'a, REG>;
235 ///Field `ACD` reader - Analog Comparator Disable
236 pub type ACD_R = crate::BitReader;
237 ///Field `ACD` writer - Analog Comparator Disable
238 pub type ACD_W<'a, REG> = crate::BitWriter<'a, REG>;
239 impl R {
240 ///Bits 0:1 - Analog Comparator Interrupt Mode Select
241 #[inline(always)]
242 pub fn acis(&self) -> ACIS_R {
243 ACIS_R::new(self.bits & 3)
244 }
245 ///Bit 2 - Analog Comparator Input Capture Enable
246 #[inline(always)]
247 pub fn acic(&self) -> ACIC_R {
248 ACIC_R::new(((self.bits >> 2) & 1) != 0)
249 }
250 ///Bit 3 - Analog Comparator Interrupt Enable
251 #[inline(always)]
252 pub fn acie(&self) -> ACIE_R {
253 ACIE_R::new(((self.bits >> 3) & 1) != 0)
254 }
255 ///Bit 4 - Analog Comparator Interrupt Flag
256 #[inline(always)]
257 pub fn aci(&self) -> ACI_R {
258 ACI_R::new(((self.bits >> 4) & 1) != 0)
259 }
260 ///Bit 5 - Analog Compare Output
261 #[inline(always)]
262 pub fn aco(&self) -> ACO_R {
263 ACO_R::new(((self.bits >> 5) & 1) != 0)
264 }
265 ///Bit 6 - Analog Comparator Bandgap Select
266 #[inline(always)]
267 pub fn acbg(&self) -> ACBG_R {
268 ACBG_R::new(((self.bits >> 6) & 1) != 0)
269 }
270 ///Bit 7 - Analog Comparator Disable
271 #[inline(always)]
272 pub fn acd(&self) -> ACD_R {
273 ACD_R::new(((self.bits >> 7) & 1) != 0)
274 }
275 }
276 impl W {
277 ///Bits 0:1 - Analog Comparator Interrupt Mode Select
278 #[inline(always)]
279 pub fn acis(&mut self) -> ACIS_W<'_, ACSR_SPEC> {
280 ACIS_W::new(self, 0)
281 }
282 ///Bit 2 - Analog Comparator Input Capture Enable
283 #[inline(always)]
284 pub fn acic(&mut self) -> ACIC_W<'_, ACSR_SPEC> {
285 ACIC_W::new(self, 2)
286 }
287 ///Bit 3 - Analog Comparator Interrupt Enable
288 #[inline(always)]
289 pub fn acie(&mut self) -> ACIE_W<'_, ACSR_SPEC> {
290 ACIE_W::new(self, 3)
291 }
292 ///Bit 4 - Analog Comparator Interrupt Flag
293 #[inline(always)]
294 pub fn aci(&mut self) -> ACI_W<'_, ACSR_SPEC> {
295 ACI_W::new(self, 4)
296 }
297 ///Bit 6 - Analog Comparator Bandgap Select
298 #[inline(always)]
299 pub fn acbg(&mut self) -> ACBG_W<'_, ACSR_SPEC> {
300 ACBG_W::new(self, 6)
301 }
302 ///Bit 7 - Analog Comparator Disable
303 #[inline(always)]
304 pub fn acd(&mut self) -> ACD_W<'_, ACSR_SPEC> {
305 ACD_W::new(self, 7)
306 }
307 }
308 /**Analog Comparator Control And Status Register
309
310You can [`read`](crate::Reg::read) this register and get [`acsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`acsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
311 pub struct ACSR_SPEC;
312 impl crate::RegisterSpec for ACSR_SPEC {
313 type Ux = u8;
314 }
315 ///`read()` method returns [`acsr::R`](R) reader structure
316 impl crate::Readable for ACSR_SPEC {}
317 ///`write(|w| ..)` method takes [`acsr::W`](W) writer structure
318 impl crate::Writable for ACSR_SPEC {
319 type Safety = crate::Unsafe;
320 }
321 ///`reset()` method sets ACSR to value 0
322 impl crate::Resettable for ACSR_SPEC {}
323 }
324 /**DIDR1 (rw) register accessor: Digital Input Disable Register 1
325
326You can [`read`](crate::Reg::read) this register and get [`didr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`didr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
327
328For information about available fields see [`mod@didr1`] module*/
329 pub type DIDR1 = crate::Reg<didr1::DIDR1_SPEC>;
330 ///Digital Input Disable Register 1
331 pub mod didr1 {
332 ///Register `DIDR1` reader
333 pub type R = crate::R<DIDR1_SPEC>;
334 ///Register `DIDR1` writer
335 pub type W = crate::W<DIDR1_SPEC>;
336 ///Field `AIN0D` reader - AIN0 Digital Input Disable
337 pub type AIN0D_R = crate::BitReader;
338 ///Field `AIN0D` writer - AIN0 Digital Input Disable
339 pub type AIN0D_W<'a, REG> = crate::BitWriter<'a, REG>;
340 ///Field `AIN1D` reader - AIN1 Digital Input Disable
341 pub type AIN1D_R = crate::BitReader;
342 ///Field `AIN1D` writer - AIN1 Digital Input Disable
343 pub type AIN1D_W<'a, REG> = crate::BitWriter<'a, REG>;
344 impl R {
345 ///Bit 0 - AIN0 Digital Input Disable
346 #[inline(always)]
347 pub fn ain0d(&self) -> AIN0D_R {
348 AIN0D_R::new((self.bits & 1) != 0)
349 }
350 ///Bit 1 - AIN1 Digital Input Disable
351 #[inline(always)]
352 pub fn ain1d(&self) -> AIN1D_R {
353 AIN1D_R::new(((self.bits >> 1) & 1) != 0)
354 }
355 }
356 impl W {
357 ///Bit 0 - AIN0 Digital Input Disable
358 #[inline(always)]
359 pub fn ain0d(&mut self) -> AIN0D_W<'_, DIDR1_SPEC> {
360 AIN0D_W::new(self, 0)
361 }
362 ///Bit 1 - AIN1 Digital Input Disable
363 #[inline(always)]
364 pub fn ain1d(&mut self) -> AIN1D_W<'_, DIDR1_SPEC> {
365 AIN1D_W::new(self, 1)
366 }
367 }
368 /**Digital Input Disable Register 1
369
370You can [`read`](crate::Reg::read) this register and get [`didr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`didr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
371 pub struct DIDR1_SPEC;
372 impl crate::RegisterSpec for DIDR1_SPEC {
373 type Ux = u8;
374 }
375 ///`read()` method returns [`didr1::R`](R) reader structure
376 impl crate::Readable for DIDR1_SPEC {}
377 ///`write(|w| ..)` method takes [`didr1::W`](W) writer structure
378 impl crate::Writable for DIDR1_SPEC {
379 type Safety = crate::Unsafe;
380 }
381 ///`reset()` method sets DIDR1 to value 0
382 impl crate::Resettable for DIDR1_SPEC {}
383 }
384}
385///Analog-to-Digital Converter
386pub type ADC = crate::Periph<adc::RegisterBlock, 0x78>;
387impl core::fmt::Debug for ADC {
388 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
389 f.debug_struct("ADC").finish()
390 }
391}
392///Analog-to-Digital Converter
393pub mod adc {
394 #[repr(C)]
395 ///Register block
396 pub struct RegisterBlock {
397 adc: ADC,
398 adcsra: ADCSRA,
399 adcsrb: ADCSRB,
400 admux: ADMUX,
401 _reserved4: [u8; 0x01],
402 didr0: DIDR0,
403 }
404 impl RegisterBlock {
405 ///0x00 - ADC Data Register Bytes
406 #[inline(always)]
407 pub const fn adc(&self) -> &ADC {
408 &self.adc
409 }
410 ///0x02 - The ADC Control and Status register A
411 #[inline(always)]
412 pub const fn adcsra(&self) -> &ADCSRA {
413 &self.adcsra
414 }
415 ///0x03 - The ADC Control and Status register B
416 #[inline(always)]
417 pub const fn adcsrb(&self) -> &ADCSRB {
418 &self.adcsrb
419 }
420 ///0x04 - The ADC multiplexer Selection Register
421 #[inline(always)]
422 pub const fn admux(&self) -> &ADMUX {
423 &self.admux
424 }
425 ///0x06 - Digital Input Disable Register
426 #[inline(always)]
427 pub const fn didr0(&self) -> &DIDR0 {
428 &self.didr0
429 }
430 }
431 /**ADC (rw) register accessor: ADC Data Register Bytes
432
433You can [`read`](crate::Reg::read) this register and get [`adc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
434
435For information about available fields see [`mod@adc`] module*/
436 pub type ADC = crate::Reg<adc::ADC_SPEC>;
437 ///ADC Data Register Bytes
438 pub mod adc {
439 ///Register `ADC` reader
440 pub type R = crate::R<ADC_SPEC>;
441 ///Register `ADC` writer
442 pub type W = crate::W<ADC_SPEC>;
443 impl core::fmt::Debug for R {
444 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
445 write!(f, "{}", self.bits())
446 }
447 }
448 impl W {}
449 /**ADC Data Register Bytes
450
451You can [`read`](crate::Reg::read) this register and get [`adc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
452 pub struct ADC_SPEC;
453 impl crate::RegisterSpec for ADC_SPEC {
454 type Ux = u16;
455 }
456 ///`read()` method returns [`adc::R`](R) reader structure
457 impl crate::Readable for ADC_SPEC {}
458 ///`write(|w| ..)` method takes [`adc::W`](W) writer structure
459 impl crate::Writable for ADC_SPEC {
460 type Safety = crate::Safe;
461 }
462 ///`reset()` method sets ADC to value 0
463 impl crate::Resettable for ADC_SPEC {}
464 }
465 /**ADCSRA (rw) register accessor: The ADC Control and Status register A
466
467You can [`read`](crate::Reg::read) this register and get [`adcsra::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adcsra::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
468
469For information about available fields see [`mod@adcsra`] module*/
470 pub type ADCSRA = crate::Reg<adcsra::ADCSRA_SPEC>;
471 ///The ADC Control and Status register A
472 pub mod adcsra {
473 ///Register `ADCSRA` reader
474 pub type R = crate::R<ADCSRA_SPEC>;
475 ///Register `ADCSRA` writer
476 pub type W = crate::W<ADCSRA_SPEC>;
477 /**ADC Prescaler Select Bits
478
479Value on reset: 0*/
480 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
481 #[repr(u8)]
482 pub enum ADPS_A {
483 ///1: Prescaler Value 2
484 PRESCALER_2 = 1,
485 ///2: Prescaler Value 4
486 PRESCALER_4 = 2,
487 ///3: Prescaler Value 8
488 PRESCALER_8 = 3,
489 ///4: Prescaler Value 16
490 PRESCALER_16 = 4,
491 ///5: Prescaler Value 32
492 PRESCALER_32 = 5,
493 ///6: Prescaler Value 64
494 PRESCALER_64 = 6,
495 ///7: Prescaler Value 128
496 PRESCALER_128 = 7,
497 }
498 impl From<ADPS_A> for u8 {
499 #[inline(always)]
500 fn from(variant: ADPS_A) -> Self {
501 variant as _
502 }
503 }
504 impl crate::FieldSpec for ADPS_A {
505 type Ux = u8;
506 }
507 impl crate::IsEnum for ADPS_A {}
508 ///Field `ADPS` reader - ADC Prescaler Select Bits
509 pub type ADPS_R = crate::FieldReader<ADPS_A>;
510 impl ADPS_R {
511 ///Get enumerated values variant
512 #[inline(always)]
513 pub const fn variant(&self) -> Option<ADPS_A> {
514 match self.bits {
515 1 => Some(ADPS_A::PRESCALER_2),
516 2 => Some(ADPS_A::PRESCALER_4),
517 3 => Some(ADPS_A::PRESCALER_8),
518 4 => Some(ADPS_A::PRESCALER_16),
519 5 => Some(ADPS_A::PRESCALER_32),
520 6 => Some(ADPS_A::PRESCALER_64),
521 7 => Some(ADPS_A::PRESCALER_128),
522 _ => None,
523 }
524 }
525 ///Prescaler Value 2
526 #[inline(always)]
527 pub fn is_prescaler_2(&self) -> bool {
528 *self == ADPS_A::PRESCALER_2
529 }
530 ///Prescaler Value 4
531 #[inline(always)]
532 pub fn is_prescaler_4(&self) -> bool {
533 *self == ADPS_A::PRESCALER_4
534 }
535 ///Prescaler Value 8
536 #[inline(always)]
537 pub fn is_prescaler_8(&self) -> bool {
538 *self == ADPS_A::PRESCALER_8
539 }
540 ///Prescaler Value 16
541 #[inline(always)]
542 pub fn is_prescaler_16(&self) -> bool {
543 *self == ADPS_A::PRESCALER_16
544 }
545 ///Prescaler Value 32
546 #[inline(always)]
547 pub fn is_prescaler_32(&self) -> bool {
548 *self == ADPS_A::PRESCALER_32
549 }
550 ///Prescaler Value 64
551 #[inline(always)]
552 pub fn is_prescaler_64(&self) -> bool {
553 *self == ADPS_A::PRESCALER_64
554 }
555 ///Prescaler Value 128
556 #[inline(always)]
557 pub fn is_prescaler_128(&self) -> bool {
558 *self == ADPS_A::PRESCALER_128
559 }
560 }
561 ///Field `ADPS` writer - ADC Prescaler Select Bits
562 pub type ADPS_W<'a, REG> = crate::FieldWriter<'a, REG, 3, ADPS_A>;
563 impl<'a, REG> ADPS_W<'a, REG>
564 where
565 REG: crate::Writable + crate::RegisterSpec,
566 REG::Ux: From<u8>,
567 {
568 ///Prescaler Value 2
569 #[inline(always)]
570 pub fn prescaler_2(self) -> &'a mut crate::W<REG> {
571 self.variant(ADPS_A::PRESCALER_2)
572 }
573 ///Prescaler Value 4
574 #[inline(always)]
575 pub fn prescaler_4(self) -> &'a mut crate::W<REG> {
576 self.variant(ADPS_A::PRESCALER_4)
577 }
578 ///Prescaler Value 8
579 #[inline(always)]
580 pub fn prescaler_8(self) -> &'a mut crate::W<REG> {
581 self.variant(ADPS_A::PRESCALER_8)
582 }
583 ///Prescaler Value 16
584 #[inline(always)]
585 pub fn prescaler_16(self) -> &'a mut crate::W<REG> {
586 self.variant(ADPS_A::PRESCALER_16)
587 }
588 ///Prescaler Value 32
589 #[inline(always)]
590 pub fn prescaler_32(self) -> &'a mut crate::W<REG> {
591 self.variant(ADPS_A::PRESCALER_32)
592 }
593 ///Prescaler Value 64
594 #[inline(always)]
595 pub fn prescaler_64(self) -> &'a mut crate::W<REG> {
596 self.variant(ADPS_A::PRESCALER_64)
597 }
598 ///Prescaler Value 128
599 #[inline(always)]
600 pub fn prescaler_128(self) -> &'a mut crate::W<REG> {
601 self.variant(ADPS_A::PRESCALER_128)
602 }
603 }
604 ///Field `ADIE` reader - ADC Interrupt Enable
605 pub type ADIE_R = crate::BitReader;
606 ///Field `ADIE` writer - ADC Interrupt Enable
607 pub type ADIE_W<'a, REG> = crate::BitWriter<'a, REG>;
608 ///Field `ADIF` reader - ADC Interrupt Flag
609 pub type ADIF_R = crate::BitReader;
610 ///Field `ADIF` writer - ADC Interrupt Flag
611 pub type ADIF_W<'a, REG> = crate::BitWriter<'a, REG>;
612 ///Field `ADATE` reader - ADC Auto Trigger Enable
613 pub type ADATE_R = crate::BitReader;
614 ///Field `ADATE` writer - ADC Auto Trigger Enable
615 pub type ADATE_W<'a, REG> = crate::BitWriter<'a, REG>;
616 ///Field `ADSC` reader - ADC Start Conversion
617 pub type ADSC_R = crate::BitReader;
618 ///Field `ADSC` writer - ADC Start Conversion
619 pub type ADSC_W<'a, REG> = crate::BitWriter<'a, REG>;
620 ///Field `ADEN` reader - ADC Enable
621 pub type ADEN_R = crate::BitReader;
622 ///Field `ADEN` writer - ADC Enable
623 pub type ADEN_W<'a, REG> = crate::BitWriter<'a, REG>;
624 impl R {
625 ///Bits 0:2 - ADC Prescaler Select Bits
626 #[inline(always)]
627 pub fn adps(&self) -> ADPS_R {
628 ADPS_R::new(self.bits & 7)
629 }
630 ///Bit 3 - ADC Interrupt Enable
631 #[inline(always)]
632 pub fn adie(&self) -> ADIE_R {
633 ADIE_R::new(((self.bits >> 3) & 1) != 0)
634 }
635 ///Bit 4 - ADC Interrupt Flag
636 #[inline(always)]
637 pub fn adif(&self) -> ADIF_R {
638 ADIF_R::new(((self.bits >> 4) & 1) != 0)
639 }
640 ///Bit 5 - ADC Auto Trigger Enable
641 #[inline(always)]
642 pub fn adate(&self) -> ADATE_R {
643 ADATE_R::new(((self.bits >> 5) & 1) != 0)
644 }
645 ///Bit 6 - ADC Start Conversion
646 #[inline(always)]
647 pub fn adsc(&self) -> ADSC_R {
648 ADSC_R::new(((self.bits >> 6) & 1) != 0)
649 }
650 ///Bit 7 - ADC Enable
651 #[inline(always)]
652 pub fn aden(&self) -> ADEN_R {
653 ADEN_R::new(((self.bits >> 7) & 1) != 0)
654 }
655 }
656 impl W {
657 ///Bits 0:2 - ADC Prescaler Select Bits
658 #[inline(always)]
659 pub fn adps(&mut self) -> ADPS_W<'_, ADCSRA_SPEC> {
660 ADPS_W::new(self, 0)
661 }
662 ///Bit 3 - ADC Interrupt Enable
663 #[inline(always)]
664 pub fn adie(&mut self) -> ADIE_W<'_, ADCSRA_SPEC> {
665 ADIE_W::new(self, 3)
666 }
667 ///Bit 4 - ADC Interrupt Flag
668 #[inline(always)]
669 pub fn adif(&mut self) -> ADIF_W<'_, ADCSRA_SPEC> {
670 ADIF_W::new(self, 4)
671 }
672 ///Bit 5 - ADC Auto Trigger Enable
673 #[inline(always)]
674 pub fn adate(&mut self) -> ADATE_W<'_, ADCSRA_SPEC> {
675 ADATE_W::new(self, 5)
676 }
677 ///Bit 6 - ADC Start Conversion
678 #[inline(always)]
679 pub fn adsc(&mut self) -> ADSC_W<'_, ADCSRA_SPEC> {
680 ADSC_W::new(self, 6)
681 }
682 ///Bit 7 - ADC Enable
683 #[inline(always)]
684 pub fn aden(&mut self) -> ADEN_W<'_, ADCSRA_SPEC> {
685 ADEN_W::new(self, 7)
686 }
687 }
688 /**The ADC Control and Status register A
689
690You can [`read`](crate::Reg::read) this register and get [`adcsra::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adcsra::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
691 pub struct ADCSRA_SPEC;
692 impl crate::RegisterSpec for ADCSRA_SPEC {
693 type Ux = u8;
694 }
695 ///`read()` method returns [`adcsra::R`](R) reader structure
696 impl crate::Readable for ADCSRA_SPEC {}
697 ///`write(|w| ..)` method takes [`adcsra::W`](W) writer structure
698 impl crate::Writable for ADCSRA_SPEC {
699 type Safety = crate::Unsafe;
700 }
701 ///`reset()` method sets ADCSRA to value 0
702 impl crate::Resettable for ADCSRA_SPEC {}
703 }
704 /**ADCSRB (rw) register accessor: The ADC Control and Status register B
705
706You can [`read`](crate::Reg::read) this register and get [`adcsrb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adcsrb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
707
708For information about available fields see [`mod@adcsrb`] module*/
709 pub type ADCSRB = crate::Reg<adcsrb::ADCSRB_SPEC>;
710 ///The ADC Control and Status register B
711 pub mod adcsrb {
712 ///Register `ADCSRB` reader
713 pub type R = crate::R<ADCSRB_SPEC>;
714 ///Register `ADCSRB` writer
715 pub type W = crate::W<ADCSRB_SPEC>;
716 /**ADC Auto Trigger Source bits
717
718Value on reset: 0*/
719 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
720 #[repr(u8)]
721 pub enum ADTS_A {
722 ///0: Free Running mode
723 VAL_0X00 = 0,
724 ///1: Analog Comparator
725 VAL_0X01 = 1,
726 ///2: External Interrupt Request 0
727 VAL_0X02 = 2,
728 ///3: Timer/Counter0 Compare Match A
729 VAL_0X03 = 3,
730 ///4: Timer/Counter0 Overflow
731 VAL_0X04 = 4,
732 ///5: Timer/Counter1 Compare Match B
733 VAL_0X05 = 5,
734 ///6: Timer/Counter1 Overflow
735 VAL_0X06 = 6,
736 ///7: Timer/Counter1 Capture Event
737 VAL_0X07 = 7,
738 }
739 impl From<ADTS_A> for u8 {
740 #[inline(always)]
741 fn from(variant: ADTS_A) -> Self {
742 variant as _
743 }
744 }
745 impl crate::FieldSpec for ADTS_A {
746 type Ux = u8;
747 }
748 impl crate::IsEnum for ADTS_A {}
749 ///Field `ADTS` reader - ADC Auto Trigger Source bits
750 pub type ADTS_R = crate::FieldReader<ADTS_A>;
751 impl ADTS_R {
752 ///Get enumerated values variant
753 #[inline(always)]
754 pub const fn variant(&self) -> ADTS_A {
755 match self.bits {
756 0 => ADTS_A::VAL_0X00,
757 1 => ADTS_A::VAL_0X01,
758 2 => ADTS_A::VAL_0X02,
759 3 => ADTS_A::VAL_0X03,
760 4 => ADTS_A::VAL_0X04,
761 5 => ADTS_A::VAL_0X05,
762 6 => ADTS_A::VAL_0X06,
763 7 => ADTS_A::VAL_0X07,
764 _ => unreachable!(),
765 }
766 }
767 ///Free Running mode
768 #[inline(always)]
769 pub fn is_val_0x00(&self) -> bool {
770 *self == ADTS_A::VAL_0X00
771 }
772 ///Analog Comparator
773 #[inline(always)]
774 pub fn is_val_0x01(&self) -> bool {
775 *self == ADTS_A::VAL_0X01
776 }
777 ///External Interrupt Request 0
778 #[inline(always)]
779 pub fn is_val_0x02(&self) -> bool {
780 *self == ADTS_A::VAL_0X02
781 }
782 ///Timer/Counter0 Compare Match A
783 #[inline(always)]
784 pub fn is_val_0x03(&self) -> bool {
785 *self == ADTS_A::VAL_0X03
786 }
787 ///Timer/Counter0 Overflow
788 #[inline(always)]
789 pub fn is_val_0x04(&self) -> bool {
790 *self == ADTS_A::VAL_0X04
791 }
792 ///Timer/Counter1 Compare Match B
793 #[inline(always)]
794 pub fn is_val_0x05(&self) -> bool {
795 *self == ADTS_A::VAL_0X05
796 }
797 ///Timer/Counter1 Overflow
798 #[inline(always)]
799 pub fn is_val_0x06(&self) -> bool {
800 *self == ADTS_A::VAL_0X06
801 }
802 ///Timer/Counter1 Capture Event
803 #[inline(always)]
804 pub fn is_val_0x07(&self) -> bool {
805 *self == ADTS_A::VAL_0X07
806 }
807 }
808 ///Field `ADTS` writer - ADC Auto Trigger Source bits
809 pub type ADTS_W<'a, REG> = crate::FieldWriter<'a, REG, 3, ADTS_A, crate::Safe>;
810 impl<'a, REG> ADTS_W<'a, REG>
811 where
812 REG: crate::Writable + crate::RegisterSpec,
813 REG::Ux: From<u8>,
814 {
815 ///Free Running mode
816 #[inline(always)]
817 pub fn val_0x00(self) -> &'a mut crate::W<REG> {
818 self.variant(ADTS_A::VAL_0X00)
819 }
820 ///Analog Comparator
821 #[inline(always)]
822 pub fn val_0x01(self) -> &'a mut crate::W<REG> {
823 self.variant(ADTS_A::VAL_0X01)
824 }
825 ///External Interrupt Request 0
826 #[inline(always)]
827 pub fn val_0x02(self) -> &'a mut crate::W<REG> {
828 self.variant(ADTS_A::VAL_0X02)
829 }
830 ///Timer/Counter0 Compare Match A
831 #[inline(always)]
832 pub fn val_0x03(self) -> &'a mut crate::W<REG> {
833 self.variant(ADTS_A::VAL_0X03)
834 }
835 ///Timer/Counter0 Overflow
836 #[inline(always)]
837 pub fn val_0x04(self) -> &'a mut crate::W<REG> {
838 self.variant(ADTS_A::VAL_0X04)
839 }
840 ///Timer/Counter1 Compare Match B
841 #[inline(always)]
842 pub fn val_0x05(self) -> &'a mut crate::W<REG> {
843 self.variant(ADTS_A::VAL_0X05)
844 }
845 ///Timer/Counter1 Overflow
846 #[inline(always)]
847 pub fn val_0x06(self) -> &'a mut crate::W<REG> {
848 self.variant(ADTS_A::VAL_0X06)
849 }
850 ///Timer/Counter1 Capture Event
851 #[inline(always)]
852 pub fn val_0x07(self) -> &'a mut crate::W<REG> {
853 self.variant(ADTS_A::VAL_0X07)
854 }
855 }
856 ///Field `ACME` reader - No Description.
857 pub type ACME_R = crate::BitReader;
858 ///Field `ACME` writer - No Description.
859 pub type ACME_W<'a, REG> = crate::BitWriter<'a, REG>;
860 impl R {
861 ///Bits 0:2 - ADC Auto Trigger Source bits
862 #[inline(always)]
863 pub fn adts(&self) -> ADTS_R {
864 ADTS_R::new(self.bits & 7)
865 }
866 ///Bit 6 - No Description.
867 #[inline(always)]
868 pub fn acme(&self) -> ACME_R {
869 ACME_R::new(((self.bits >> 6) & 1) != 0)
870 }
871 }
872 impl W {
873 ///Bits 0:2 - ADC Auto Trigger Source bits
874 #[inline(always)]
875 pub fn adts(&mut self) -> ADTS_W<'_, ADCSRB_SPEC> {
876 ADTS_W::new(self, 0)
877 }
878 ///Bit 6 - No Description.
879 #[inline(always)]
880 pub fn acme(&mut self) -> ACME_W<'_, ADCSRB_SPEC> {
881 ACME_W::new(self, 6)
882 }
883 }
884 /**The ADC Control and Status register B
885
886You can [`read`](crate::Reg::read) this register and get [`adcsrb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adcsrb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
887 pub struct ADCSRB_SPEC;
888 impl crate::RegisterSpec for ADCSRB_SPEC {
889 type Ux = u8;
890 }
891 ///`read()` method returns [`adcsrb::R`](R) reader structure
892 impl crate::Readable for ADCSRB_SPEC {}
893 ///`write(|w| ..)` method takes [`adcsrb::W`](W) writer structure
894 impl crate::Writable for ADCSRB_SPEC {
895 type Safety = crate::Unsafe;
896 }
897 ///`reset()` method sets ADCSRB to value 0
898 impl crate::Resettable for ADCSRB_SPEC {}
899 }
900 /**ADMUX (rw) register accessor: The ADC multiplexer Selection Register
901
902You can [`read`](crate::Reg::read) this register and get [`admux::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`admux::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
903
904For information about available fields see [`mod@admux`] module*/
905 pub type ADMUX = crate::Reg<admux::ADMUX_SPEC>;
906 ///The ADC multiplexer Selection Register
907 pub mod admux {
908 ///Register `ADMUX` reader
909 pub type R = crate::R<ADMUX_SPEC>;
910 ///Register `ADMUX` writer
911 pub type W = crate::W<ADMUX_SPEC>;
912 /**Analog Channel Selection Bits
913
914Value on reset: 0*/
915 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
916 #[repr(u8)]
917 pub enum MUX_A {
918 ///0: ADC Single Ended Input pin 0
919 ADC0 = 0,
920 ///1: ADC Single Ended Input pin 1
921 ADC1 = 1,
922 ///2: ADC Single Ended Input pin 2
923 ADC2 = 2,
924 ///3: ADC Single Ended Input pin 3
925 ADC3 = 3,
926 ///4: ADC Single Ended Input pin 4
927 ADC4 = 4,
928 ///5: ADC Single Ended Input pin 5
929 ADC5 = 5,
930 ///6: ADC Single Ended Input pin 6
931 ADC6 = 6,
932 ///7: ADC Single Ended Input pin 7
933 ADC7 = 7,
934 ///8: Temperature sensor
935 TEMPSENS = 8,
936 ///14: Internal Reference (VBG)
937 ADC_VBG = 14,
938 ///15: 0V (GND)
939 ADC_GND = 15,
940 }
941 impl From<MUX_A> for u8 {
942 #[inline(always)]
943 fn from(variant: MUX_A) -> Self {
944 variant as _
945 }
946 }
947 impl crate::FieldSpec for MUX_A {
948 type Ux = u8;
949 }
950 impl crate::IsEnum for MUX_A {}
951 ///Field `MUX` reader - Analog Channel Selection Bits
952 pub type MUX_R = crate::FieldReader<MUX_A>;
953 impl MUX_R {
954 ///Get enumerated values variant
955 #[inline(always)]
956 pub const fn variant(&self) -> Option<MUX_A> {
957 match self.bits {
958 0 => Some(MUX_A::ADC0),
959 1 => Some(MUX_A::ADC1),
960 2 => Some(MUX_A::ADC2),
961 3 => Some(MUX_A::ADC3),
962 4 => Some(MUX_A::ADC4),
963 5 => Some(MUX_A::ADC5),
964 6 => Some(MUX_A::ADC6),
965 7 => Some(MUX_A::ADC7),
966 8 => Some(MUX_A::TEMPSENS),
967 14 => Some(MUX_A::ADC_VBG),
968 15 => Some(MUX_A::ADC_GND),
969 _ => None,
970 }
971 }
972 ///ADC Single Ended Input pin 0
973 #[inline(always)]
974 pub fn is_adc0(&self) -> bool {
975 *self == MUX_A::ADC0
976 }
977 ///ADC Single Ended Input pin 1
978 #[inline(always)]
979 pub fn is_adc1(&self) -> bool {
980 *self == MUX_A::ADC1
981 }
982 ///ADC Single Ended Input pin 2
983 #[inline(always)]
984 pub fn is_adc2(&self) -> bool {
985 *self == MUX_A::ADC2
986 }
987 ///ADC Single Ended Input pin 3
988 #[inline(always)]
989 pub fn is_adc3(&self) -> bool {
990 *self == MUX_A::ADC3
991 }
992 ///ADC Single Ended Input pin 4
993 #[inline(always)]
994 pub fn is_adc4(&self) -> bool {
995 *self == MUX_A::ADC4
996 }
997 ///ADC Single Ended Input pin 5
998 #[inline(always)]
999 pub fn is_adc5(&self) -> bool {
1000 *self == MUX_A::ADC5
1001 }
1002 ///ADC Single Ended Input pin 6
1003 #[inline(always)]
1004 pub fn is_adc6(&self) -> bool {
1005 *self == MUX_A::ADC6
1006 }
1007 ///ADC Single Ended Input pin 7
1008 #[inline(always)]
1009 pub fn is_adc7(&self) -> bool {
1010 *self == MUX_A::ADC7
1011 }
1012 ///Temperature sensor
1013 #[inline(always)]
1014 pub fn is_tempsens(&self) -> bool {
1015 *self == MUX_A::TEMPSENS
1016 }
1017 ///Internal Reference (VBG)
1018 #[inline(always)]
1019 pub fn is_adc_vbg(&self) -> bool {
1020 *self == MUX_A::ADC_VBG
1021 }
1022 ///0V (GND)
1023 #[inline(always)]
1024 pub fn is_adc_gnd(&self) -> bool {
1025 *self == MUX_A::ADC_GND
1026 }
1027 }
1028 ///Field `MUX` writer - Analog Channel Selection Bits
1029 pub type MUX_W<'a, REG> = crate::FieldWriter<'a, REG, 4, MUX_A>;
1030 impl<'a, REG> MUX_W<'a, REG>
1031 where
1032 REG: crate::Writable + crate::RegisterSpec,
1033 REG::Ux: From<u8>,
1034 {
1035 ///ADC Single Ended Input pin 0
1036 #[inline(always)]
1037 pub fn adc0(self) -> &'a mut crate::W<REG> {
1038 self.variant(MUX_A::ADC0)
1039 }
1040 ///ADC Single Ended Input pin 1
1041 #[inline(always)]
1042 pub fn adc1(self) -> &'a mut crate::W<REG> {
1043 self.variant(MUX_A::ADC1)
1044 }
1045 ///ADC Single Ended Input pin 2
1046 #[inline(always)]
1047 pub fn adc2(self) -> &'a mut crate::W<REG> {
1048 self.variant(MUX_A::ADC2)
1049 }
1050 ///ADC Single Ended Input pin 3
1051 #[inline(always)]
1052 pub fn adc3(self) -> &'a mut crate::W<REG> {
1053 self.variant(MUX_A::ADC3)
1054 }
1055 ///ADC Single Ended Input pin 4
1056 #[inline(always)]
1057 pub fn adc4(self) -> &'a mut crate::W<REG> {
1058 self.variant(MUX_A::ADC4)
1059 }
1060 ///ADC Single Ended Input pin 5
1061 #[inline(always)]
1062 pub fn adc5(self) -> &'a mut crate::W<REG> {
1063 self.variant(MUX_A::ADC5)
1064 }
1065 ///ADC Single Ended Input pin 6
1066 #[inline(always)]
1067 pub fn adc6(self) -> &'a mut crate::W<REG> {
1068 self.variant(MUX_A::ADC6)
1069 }
1070 ///ADC Single Ended Input pin 7
1071 #[inline(always)]
1072 pub fn adc7(self) -> &'a mut crate::W<REG> {
1073 self.variant(MUX_A::ADC7)
1074 }
1075 ///Temperature sensor
1076 #[inline(always)]
1077 pub fn tempsens(self) -> &'a mut crate::W<REG> {
1078 self.variant(MUX_A::TEMPSENS)
1079 }
1080 ///Internal Reference (VBG)
1081 #[inline(always)]
1082 pub fn adc_vbg(self) -> &'a mut crate::W<REG> {
1083 self.variant(MUX_A::ADC_VBG)
1084 }
1085 ///0V (GND)
1086 #[inline(always)]
1087 pub fn adc_gnd(self) -> &'a mut crate::W<REG> {
1088 self.variant(MUX_A::ADC_GND)
1089 }
1090 }
1091 ///Field `ADLAR` reader - Left Adjust Result
1092 pub type ADLAR_R = crate::BitReader;
1093 ///Field `ADLAR` writer - Left Adjust Result
1094 pub type ADLAR_W<'a, REG> = crate::BitWriter<'a, REG>;
1095 /**Reference Selection Bits
1096
1097Value on reset: 0*/
1098 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
1099 #[repr(u8)]
1100 pub enum REFS_A {
1101 ///0: Aref Internal Vref turned off
1102 AREF = 0,
1103 ///1: AVcc with external capacitor at AREF pin
1104 AVCC = 1,
1105 ///3: Internal 1.1V Voltage Reference with external capacitor at AREF pin
1106 INTERNAL = 3,
1107 }
1108 impl From<REFS_A> for u8 {
1109 #[inline(always)]
1110 fn from(variant: REFS_A) -> Self {
1111 variant as _
1112 }
1113 }
1114 impl crate::FieldSpec for REFS_A {
1115 type Ux = u8;
1116 }
1117 impl crate::IsEnum for REFS_A {}
1118 ///Field `REFS` reader - Reference Selection Bits
1119 pub type REFS_R = crate::FieldReader<REFS_A>;
1120 impl REFS_R {
1121 ///Get enumerated values variant
1122 #[inline(always)]
1123 pub const fn variant(&self) -> Option<REFS_A> {
1124 match self.bits {
1125 0 => Some(REFS_A::AREF),
1126 1 => Some(REFS_A::AVCC),
1127 3 => Some(REFS_A::INTERNAL),
1128 _ => None,
1129 }
1130 }
1131 ///Aref Internal Vref turned off
1132 #[inline(always)]
1133 pub fn is_aref(&self) -> bool {
1134 *self == REFS_A::AREF
1135 }
1136 ///AVcc with external capacitor at AREF pin
1137 #[inline(always)]
1138 pub fn is_avcc(&self) -> bool {
1139 *self == REFS_A::AVCC
1140 }
1141 ///Internal 1.1V Voltage Reference with external capacitor at AREF pin
1142 #[inline(always)]
1143 pub fn is_internal(&self) -> bool {
1144 *self == REFS_A::INTERNAL
1145 }
1146 }
1147 ///Field `REFS` writer - Reference Selection Bits
1148 pub type REFS_W<'a, REG> = crate::FieldWriter<'a, REG, 2, REFS_A>;
1149 impl<'a, REG> REFS_W<'a, REG>
1150 where
1151 REG: crate::Writable + crate::RegisterSpec,
1152 REG::Ux: From<u8>,
1153 {
1154 ///Aref Internal Vref turned off
1155 #[inline(always)]
1156 pub fn aref(self) -> &'a mut crate::W<REG> {
1157 self.variant(REFS_A::AREF)
1158 }
1159 ///AVcc with external capacitor at AREF pin
1160 #[inline(always)]
1161 pub fn avcc(self) -> &'a mut crate::W<REG> {
1162 self.variant(REFS_A::AVCC)
1163 }
1164 ///Internal 1.1V Voltage Reference with external capacitor at AREF pin
1165 #[inline(always)]
1166 pub fn internal(self) -> &'a mut crate::W<REG> {
1167 self.variant(REFS_A::INTERNAL)
1168 }
1169 }
1170 impl R {
1171 ///Bits 0:3 - Analog Channel Selection Bits
1172 #[inline(always)]
1173 pub fn mux(&self) -> MUX_R {
1174 MUX_R::new(self.bits & 0x0f)
1175 }
1176 ///Bit 5 - Left Adjust Result
1177 #[inline(always)]
1178 pub fn adlar(&self) -> ADLAR_R {
1179 ADLAR_R::new(((self.bits >> 5) & 1) != 0)
1180 }
1181 ///Bits 6:7 - Reference Selection Bits
1182 #[inline(always)]
1183 pub fn refs(&self) -> REFS_R {
1184 REFS_R::new((self.bits >> 6) & 3)
1185 }
1186 }
1187 impl W {
1188 ///Bits 0:3 - Analog Channel Selection Bits
1189 #[inline(always)]
1190 pub fn mux(&mut self) -> MUX_W<'_, ADMUX_SPEC> {
1191 MUX_W::new(self, 0)
1192 }
1193 ///Bit 5 - Left Adjust Result
1194 #[inline(always)]
1195 pub fn adlar(&mut self) -> ADLAR_W<'_, ADMUX_SPEC> {
1196 ADLAR_W::new(self, 5)
1197 }
1198 ///Bits 6:7 - Reference Selection Bits
1199 #[inline(always)]
1200 pub fn refs(&mut self) -> REFS_W<'_, ADMUX_SPEC> {
1201 REFS_W::new(self, 6)
1202 }
1203 }
1204 /**The ADC multiplexer Selection Register
1205
1206You can [`read`](crate::Reg::read) this register and get [`admux::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`admux::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
1207 pub struct ADMUX_SPEC;
1208 impl crate::RegisterSpec for ADMUX_SPEC {
1209 type Ux = u8;
1210 }
1211 ///`read()` method returns [`admux::R`](R) reader structure
1212 impl crate::Readable for ADMUX_SPEC {}
1213 ///`write(|w| ..)` method takes [`admux::W`](W) writer structure
1214 impl crate::Writable for ADMUX_SPEC {
1215 type Safety = crate::Unsafe;
1216 }
1217 ///`reset()` method sets ADMUX to value 0
1218 impl crate::Resettable for ADMUX_SPEC {}
1219 }
1220 /**DIDR0 (rw) register accessor: Digital Input Disable Register
1221
1222You can [`read`](crate::Reg::read) this register and get [`didr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`didr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
1223
1224For information about available fields see [`mod@didr0`] module*/
1225 pub type DIDR0 = crate::Reg<didr0::DIDR0_SPEC>;
1226 ///Digital Input Disable Register
1227 pub mod didr0 {
1228 ///Register `DIDR0` reader
1229 pub type R = crate::R<DIDR0_SPEC>;
1230 ///Register `DIDR0` writer
1231 pub type W = crate::W<DIDR0_SPEC>;
1232 ///Field `ADC0D` reader - No Description.
1233 pub type ADC0D_R = crate::BitReader;
1234 ///Field `ADC0D` writer - No Description.
1235 pub type ADC0D_W<'a, REG> = crate::BitWriter<'a, REG>;
1236 ///Field `ADC1D` reader - No Description.
1237 pub type ADC1D_R = crate::BitReader;
1238 ///Field `ADC1D` writer - No Description.
1239 pub type ADC1D_W<'a, REG> = crate::BitWriter<'a, REG>;
1240 ///Field `ADC2D` reader - No Description.
1241 pub type ADC2D_R = crate::BitReader;
1242 ///Field `ADC2D` writer - No Description.
1243 pub type ADC2D_W<'a, REG> = crate::BitWriter<'a, REG>;
1244 ///Field `ADC3D` reader - No Description.
1245 pub type ADC3D_R = crate::BitReader;
1246 ///Field `ADC3D` writer - No Description.
1247 pub type ADC3D_W<'a, REG> = crate::BitWriter<'a, REG>;
1248 ///Field `ADC4D` reader - No Description.
1249 pub type ADC4D_R = crate::BitReader;
1250 ///Field `ADC4D` writer - No Description.
1251 pub type ADC4D_W<'a, REG> = crate::BitWriter<'a, REG>;
1252 ///Field `ADC5D` reader - No Description.
1253 pub type ADC5D_R = crate::BitReader;
1254 ///Field `ADC5D` writer - No Description.
1255 pub type ADC5D_W<'a, REG> = crate::BitWriter<'a, REG>;
1256 impl R {
1257 ///Bit 0 - No Description.
1258 #[inline(always)]
1259 pub fn adc0d(&self) -> ADC0D_R {
1260 ADC0D_R::new((self.bits & 1) != 0)
1261 }
1262 ///Bit 1 - No Description.
1263 #[inline(always)]
1264 pub fn adc1d(&self) -> ADC1D_R {
1265 ADC1D_R::new(((self.bits >> 1) & 1) != 0)
1266 }
1267 ///Bit 2 - No Description.
1268 #[inline(always)]
1269 pub fn adc2d(&self) -> ADC2D_R {
1270 ADC2D_R::new(((self.bits >> 2) & 1) != 0)
1271 }
1272 ///Bit 3 - No Description.
1273 #[inline(always)]
1274 pub fn adc3d(&self) -> ADC3D_R {
1275 ADC3D_R::new(((self.bits >> 3) & 1) != 0)
1276 }
1277 ///Bit 4 - No Description.
1278 #[inline(always)]
1279 pub fn adc4d(&self) -> ADC4D_R {
1280 ADC4D_R::new(((self.bits >> 4) & 1) != 0)
1281 }
1282 ///Bit 5 - No Description.
1283 #[inline(always)]
1284 pub fn adc5d(&self) -> ADC5D_R {
1285 ADC5D_R::new(((self.bits >> 5) & 1) != 0)
1286 }
1287 }
1288 impl W {
1289 ///Bit 0 - No Description.
1290 #[inline(always)]
1291 pub fn adc0d(&mut self) -> ADC0D_W<'_, DIDR0_SPEC> {
1292 ADC0D_W::new(self, 0)
1293 }
1294 ///Bit 1 - No Description.
1295 #[inline(always)]
1296 pub fn adc1d(&mut self) -> ADC1D_W<'_, DIDR0_SPEC> {
1297 ADC1D_W::new(self, 1)
1298 }
1299 ///Bit 2 - No Description.
1300 #[inline(always)]
1301 pub fn adc2d(&mut self) -> ADC2D_W<'_, DIDR0_SPEC> {
1302 ADC2D_W::new(self, 2)
1303 }
1304 ///Bit 3 - No Description.
1305 #[inline(always)]
1306 pub fn adc3d(&mut self) -> ADC3D_W<'_, DIDR0_SPEC> {
1307 ADC3D_W::new(self, 3)
1308 }
1309 ///Bit 4 - No Description.
1310 #[inline(always)]
1311 pub fn adc4d(&mut self) -> ADC4D_W<'_, DIDR0_SPEC> {
1312 ADC4D_W::new(self, 4)
1313 }
1314 ///Bit 5 - No Description.
1315 #[inline(always)]
1316 pub fn adc5d(&mut self) -> ADC5D_W<'_, DIDR0_SPEC> {
1317 ADC5D_W::new(self, 5)
1318 }
1319 }
1320 /**Digital Input Disable Register
1321
1322You can [`read`](crate::Reg::read) this register and get [`didr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`didr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
1323 pub struct DIDR0_SPEC;
1324 impl crate::RegisterSpec for DIDR0_SPEC {
1325 type Ux = u8;
1326 }
1327 ///`read()` method returns [`didr0::R`](R) reader structure
1328 impl crate::Readable for DIDR0_SPEC {}
1329 ///`write(|w| ..)` method takes [`didr0::W`](W) writer structure
1330 impl crate::Writable for DIDR0_SPEC {
1331 type Safety = crate::Unsafe;
1332 }
1333 ///`reset()` method sets DIDR0 to value 0
1334 impl crate::Resettable for DIDR0_SPEC {}
1335 }
1336}
1337///CPU Registers
1338pub type CPU = crate::Periph<cpu::RegisterBlock, 0x3e>;
1339impl core::fmt::Debug for CPU {
1340 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1341 f.debug_struct("CPU").finish()
1342 }
1343}
1344///CPU Registers
1345pub mod cpu {
1346 #[repr(C)]
1347 ///Register block
1348 pub struct RegisterBlock {
1349 gpior0: GPIOR0,
1350 _reserved1: [u8; 0x0b],
1351 gpior1: GPIOR1,
1352 gpior2: GPIOR2,
1353 _reserved3: [u8; 0x07],
1354 smcr: SMCR,
1355 mcusr: MCUSR,
1356 mcucr: MCUCR,
1357 _reserved6: [u8; 0x01],
1358 spmcsr: SPMCSR,
1359 _reserved7: [u8; 0x09],
1360 clkpr: CLKPR,
1361 _reserved8: [u8; 0x02],
1362 prr: PRR,
1363 _reserved9: [u8; 0x01],
1364 osccal: OSCCAL,
1365 }
1366 impl RegisterBlock {
1367 ///0x00 - General Purpose I/O Register 0
1368 #[inline(always)]
1369 pub const fn gpior0(&self) -> &GPIOR0 {
1370 &self.gpior0
1371 }
1372 ///0x0c - General Purpose I/O Register 1
1373 #[inline(always)]
1374 pub const fn gpior1(&self) -> &GPIOR1 {
1375 &self.gpior1
1376 }
1377 ///0x0d - General Purpose I/O Register 2
1378 #[inline(always)]
1379 pub const fn gpior2(&self) -> &GPIOR2 {
1380 &self.gpior2
1381 }
1382 ///0x15 - Sleep Mode Control Register
1383 #[inline(always)]
1384 pub const fn smcr(&self) -> &SMCR {
1385 &self.smcr
1386 }
1387 ///0x16 - MCU Status Register
1388 #[inline(always)]
1389 pub const fn mcusr(&self) -> &MCUSR {
1390 &self.mcusr
1391 }
1392 ///0x17 - MCU Control Register
1393 #[inline(always)]
1394 pub const fn mcucr(&self) -> &MCUCR {
1395 &self.mcucr
1396 }
1397 ///0x19 - Store Program Memory Control and Status Register
1398 #[inline(always)]
1399 pub const fn spmcsr(&self) -> &SPMCSR {
1400 &self.spmcsr
1401 }
1402 ///0x23 - Clock Prescale Register
1403 #[inline(always)]
1404 pub const fn clkpr(&self) -> &CLKPR {
1405 &self.clkpr
1406 }
1407 ///0x26 - Power Reduction Register
1408 #[inline(always)]
1409 pub const fn prr(&self) -> &PRR {
1410 &self.prr
1411 }
1412 ///0x28 - Oscillator Calibration Value
1413 #[inline(always)]
1414 pub const fn osccal(&self) -> &OSCCAL {
1415 &self.osccal
1416 }
1417 }
1418 /**CLKPR (rw) register accessor: Clock Prescale Register
1419
1420You can [`read`](crate::Reg::read) this register and get [`clkpr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkpr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
1421
1422For information about available fields see [`mod@clkpr`] module*/
1423 pub type CLKPR = crate::Reg<clkpr::CLKPR_SPEC>;
1424 ///Clock Prescale Register
1425 pub mod clkpr {
1426 ///Register `CLKPR` reader
1427 pub type R = crate::R<CLKPR_SPEC>;
1428 ///Register `CLKPR` writer
1429 pub type W = crate::W<CLKPR_SPEC>;
1430 /**Clock Prescaler Select Bits
1431
1432Value on reset: 0*/
1433 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
1434 #[repr(u8)]
1435 pub enum CLKPS_A {
1436 ///0: 1
1437 VAL_0X00 = 0,
1438 ///1: 2
1439 VAL_0X01 = 1,
1440 ///2: 4
1441 VAL_0X02 = 2,
1442 ///3: 8
1443 VAL_0X03 = 3,
1444 ///4: 16
1445 VAL_0X04 = 4,
1446 ///5: 32
1447 VAL_0X05 = 5,
1448 ///6: 64
1449 VAL_0X06 = 6,
1450 ///7: 128
1451 VAL_0X07 = 7,
1452 ///8: 256
1453 VAL_0X08 = 8,
1454 }
1455 impl From<CLKPS_A> for u8 {
1456 #[inline(always)]
1457 fn from(variant: CLKPS_A) -> Self {
1458 variant as _
1459 }
1460 }
1461 impl crate::FieldSpec for CLKPS_A {
1462 type Ux = u8;
1463 }
1464 impl crate::IsEnum for CLKPS_A {}
1465 ///Field `CLKPS` reader - Clock Prescaler Select Bits
1466 pub type CLKPS_R = crate::FieldReader<CLKPS_A>;
1467 impl CLKPS_R {
1468 ///Get enumerated values variant
1469 #[inline(always)]
1470 pub const fn variant(&self) -> Option<CLKPS_A> {
1471 match self.bits {
1472 0 => Some(CLKPS_A::VAL_0X00),
1473 1 => Some(CLKPS_A::VAL_0X01),
1474 2 => Some(CLKPS_A::VAL_0X02),
1475 3 => Some(CLKPS_A::VAL_0X03),
1476 4 => Some(CLKPS_A::VAL_0X04),
1477 5 => Some(CLKPS_A::VAL_0X05),
1478 6 => Some(CLKPS_A::VAL_0X06),
1479 7 => Some(CLKPS_A::VAL_0X07),
1480 8 => Some(CLKPS_A::VAL_0X08),
1481 _ => None,
1482 }
1483 }
1484 ///1
1485 #[inline(always)]
1486 pub fn is_val_0x00(&self) -> bool {
1487 *self == CLKPS_A::VAL_0X00
1488 }
1489 ///2
1490 #[inline(always)]
1491 pub fn is_val_0x01(&self) -> bool {
1492 *self == CLKPS_A::VAL_0X01
1493 }
1494 ///4
1495 #[inline(always)]
1496 pub fn is_val_0x02(&self) -> bool {
1497 *self == CLKPS_A::VAL_0X02
1498 }
1499 ///8
1500 #[inline(always)]
1501 pub fn is_val_0x03(&self) -> bool {
1502 *self == CLKPS_A::VAL_0X03
1503 }
1504 ///16
1505 #[inline(always)]
1506 pub fn is_val_0x04(&self) -> bool {
1507 *self == CLKPS_A::VAL_0X04
1508 }
1509 ///32
1510 #[inline(always)]
1511 pub fn is_val_0x05(&self) -> bool {
1512 *self == CLKPS_A::VAL_0X05
1513 }
1514 ///64
1515 #[inline(always)]
1516 pub fn is_val_0x06(&self) -> bool {
1517 *self == CLKPS_A::VAL_0X06
1518 }
1519 ///128
1520 #[inline(always)]
1521 pub fn is_val_0x07(&self) -> bool {
1522 *self == CLKPS_A::VAL_0X07
1523 }
1524 ///256
1525 #[inline(always)]
1526 pub fn is_val_0x08(&self) -> bool {
1527 *self == CLKPS_A::VAL_0X08
1528 }
1529 }
1530 ///Field `CLKPS` writer - Clock Prescaler Select Bits
1531 pub type CLKPS_W<'a, REG> = crate::FieldWriter<'a, REG, 4, CLKPS_A>;
1532 impl<'a, REG> CLKPS_W<'a, REG>
1533 where
1534 REG: crate::Writable + crate::RegisterSpec,
1535 REG::Ux: From<u8>,
1536 {
1537 ///1
1538 #[inline(always)]
1539 pub fn val_0x00(self) -> &'a mut crate::W<REG> {
1540 self.variant(CLKPS_A::VAL_0X00)
1541 }
1542 ///2
1543 #[inline(always)]
1544 pub fn val_0x01(self) -> &'a mut crate::W<REG> {
1545 self.variant(CLKPS_A::VAL_0X01)
1546 }
1547 ///4
1548 #[inline(always)]
1549 pub fn val_0x02(self) -> &'a mut crate::W<REG> {
1550 self.variant(CLKPS_A::VAL_0X02)
1551 }
1552 ///8
1553 #[inline(always)]
1554 pub fn val_0x03(self) -> &'a mut crate::W<REG> {
1555 self.variant(CLKPS_A::VAL_0X03)
1556 }
1557 ///16
1558 #[inline(always)]
1559 pub fn val_0x04(self) -> &'a mut crate::W<REG> {
1560 self.variant(CLKPS_A::VAL_0X04)
1561 }
1562 ///32
1563 #[inline(always)]
1564 pub fn val_0x05(self) -> &'a mut crate::W<REG> {
1565 self.variant(CLKPS_A::VAL_0X05)
1566 }
1567 ///64
1568 #[inline(always)]
1569 pub fn val_0x06(self) -> &'a mut crate::W<REG> {
1570 self.variant(CLKPS_A::VAL_0X06)
1571 }
1572 ///128
1573 #[inline(always)]
1574 pub fn val_0x07(self) -> &'a mut crate::W<REG> {
1575 self.variant(CLKPS_A::VAL_0X07)
1576 }
1577 ///256
1578 #[inline(always)]
1579 pub fn val_0x08(self) -> &'a mut crate::W<REG> {
1580 self.variant(CLKPS_A::VAL_0X08)
1581 }
1582 }
1583 ///Field `CLKPCE` reader - Clock Prescaler Change Enable
1584 pub type CLKPCE_R = crate::BitReader;
1585 ///Field `CLKPCE` writer - Clock Prescaler Change Enable
1586 pub type CLKPCE_W<'a, REG> = crate::BitWriter<'a, REG>;
1587 impl R {
1588 ///Bits 0:3 - Clock Prescaler Select Bits
1589 #[inline(always)]
1590 pub fn clkps(&self) -> CLKPS_R {
1591 CLKPS_R::new(self.bits & 0x0f)
1592 }
1593 ///Bit 7 - Clock Prescaler Change Enable
1594 #[inline(always)]
1595 pub fn clkpce(&self) -> CLKPCE_R {
1596 CLKPCE_R::new(((self.bits >> 7) & 1) != 0)
1597 }
1598 }
1599 impl W {
1600 ///Bits 0:3 - Clock Prescaler Select Bits
1601 #[inline(always)]
1602 pub fn clkps(&mut self) -> CLKPS_W<'_, CLKPR_SPEC> {
1603 CLKPS_W::new(self, 0)
1604 }
1605 ///Bit 7 - Clock Prescaler Change Enable
1606 #[inline(always)]
1607 pub fn clkpce(&mut self) -> CLKPCE_W<'_, CLKPR_SPEC> {
1608 CLKPCE_W::new(self, 7)
1609 }
1610 }
1611 /**Clock Prescale Register
1612
1613You can [`read`](crate::Reg::read) this register and get [`clkpr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkpr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
1614 pub struct CLKPR_SPEC;
1615 impl crate::RegisterSpec for CLKPR_SPEC {
1616 type Ux = u8;
1617 }
1618 ///`read()` method returns [`clkpr::R`](R) reader structure
1619 impl crate::Readable for CLKPR_SPEC {}
1620 ///`write(|w| ..)` method takes [`clkpr::W`](W) writer structure
1621 impl crate::Writable for CLKPR_SPEC {
1622 type Safety = crate::Unsafe;
1623 }
1624 ///`reset()` method sets CLKPR to value 0
1625 impl crate::Resettable for CLKPR_SPEC {}
1626 }
1627 /**GPIOR0 (rw) register accessor: General Purpose I/O Register 0
1628
1629You can [`read`](crate::Reg::read) this register and get [`gpior0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpior0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
1630
1631For information about available fields see [`mod@gpior0`] module*/
1632 pub type GPIOR0 = crate::Reg<gpior0::GPIOR0_SPEC>;
1633 ///General Purpose I/O Register 0
1634 pub mod gpior0 {
1635 ///Register `GPIOR0` reader
1636 pub type R = crate::R<GPIOR0_SPEC>;
1637 ///Register `GPIOR0` writer
1638 pub type W = crate::W<GPIOR0_SPEC>;
1639 impl core::fmt::Debug for R {
1640 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1641 write!(f, "{}", self.bits())
1642 }
1643 }
1644 impl W {}
1645 /**General Purpose I/O Register 0
1646
1647You can [`read`](crate::Reg::read) this register and get [`gpior0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpior0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
1648 pub struct GPIOR0_SPEC;
1649 impl crate::RegisterSpec for GPIOR0_SPEC {
1650 type Ux = u8;
1651 }
1652 ///`read()` method returns [`gpior0::R`](R) reader structure
1653 impl crate::Readable for GPIOR0_SPEC {}
1654 ///`write(|w| ..)` method takes [`gpior0::W`](W) writer structure
1655 impl crate::Writable for GPIOR0_SPEC {
1656 type Safety = crate::Safe;
1657 }
1658 ///`reset()` method sets GPIOR0 to value 0
1659 impl crate::Resettable for GPIOR0_SPEC {}
1660 }
1661 /**GPIOR1 (rw) register accessor: General Purpose I/O Register 1
1662
1663You can [`read`](crate::Reg::read) this register and get [`gpior1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpior1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
1664
1665For information about available fields see [`mod@gpior1`] module*/
1666 pub type GPIOR1 = crate::Reg<gpior1::GPIOR1_SPEC>;
1667 ///General Purpose I/O Register 1
1668 pub mod gpior1 {
1669 ///Register `GPIOR1` reader
1670 pub type R = crate::R<GPIOR1_SPEC>;
1671 ///Register `GPIOR1` writer
1672 pub type W = crate::W<GPIOR1_SPEC>;
1673 impl core::fmt::Debug for R {
1674 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1675 write!(f, "{}", self.bits())
1676 }
1677 }
1678 impl W {}
1679 /**General Purpose I/O Register 1
1680
1681You can [`read`](crate::Reg::read) this register and get [`gpior1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpior1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
1682 pub struct GPIOR1_SPEC;
1683 impl crate::RegisterSpec for GPIOR1_SPEC {
1684 type Ux = u8;
1685 }
1686 ///`read()` method returns [`gpior1::R`](R) reader structure
1687 impl crate::Readable for GPIOR1_SPEC {}
1688 ///`write(|w| ..)` method takes [`gpior1::W`](W) writer structure
1689 impl crate::Writable for GPIOR1_SPEC {
1690 type Safety = crate::Safe;
1691 }
1692 ///`reset()` method sets GPIOR1 to value 0
1693 impl crate::Resettable for GPIOR1_SPEC {}
1694 }
1695 /**GPIOR2 (rw) register accessor: General Purpose I/O Register 2
1696
1697You can [`read`](crate::Reg::read) this register and get [`gpior2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpior2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
1698
1699For information about available fields see [`mod@gpior2`] module*/
1700 pub type GPIOR2 = crate::Reg<gpior2::GPIOR2_SPEC>;
1701 ///General Purpose I/O Register 2
1702 pub mod gpior2 {
1703 ///Register `GPIOR2` reader
1704 pub type R = crate::R<GPIOR2_SPEC>;
1705 ///Register `GPIOR2` writer
1706 pub type W = crate::W<GPIOR2_SPEC>;
1707 impl core::fmt::Debug for R {
1708 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1709 write!(f, "{}", self.bits())
1710 }
1711 }
1712 impl W {}
1713 /**General Purpose I/O Register 2
1714
1715You can [`read`](crate::Reg::read) this register and get [`gpior2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpior2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
1716 pub struct GPIOR2_SPEC;
1717 impl crate::RegisterSpec for GPIOR2_SPEC {
1718 type Ux = u8;
1719 }
1720 ///`read()` method returns [`gpior2::R`](R) reader structure
1721 impl crate::Readable for GPIOR2_SPEC {}
1722 ///`write(|w| ..)` method takes [`gpior2::W`](W) writer structure
1723 impl crate::Writable for GPIOR2_SPEC {
1724 type Safety = crate::Safe;
1725 }
1726 ///`reset()` method sets GPIOR2 to value 0
1727 impl crate::Resettable for GPIOR2_SPEC {}
1728 }
1729 /**MCUCR (rw) register accessor: MCU Control Register
1730
1731You can [`read`](crate::Reg::read) this register and get [`mcucr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mcucr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
1732
1733For information about available fields see [`mod@mcucr`] module*/
1734 pub type MCUCR = crate::Reg<mcucr::MCUCR_SPEC>;
1735 ///MCU Control Register
1736 pub mod mcucr {
1737 ///Register `MCUCR` reader
1738 pub type R = crate::R<MCUCR_SPEC>;
1739 ///Register `MCUCR` writer
1740 pub type W = crate::W<MCUCR_SPEC>;
1741 ///Field `IVCE` reader - No Description.
1742 pub type IVCE_R = crate::BitReader;
1743 ///Field `IVCE` writer - No Description.
1744 pub type IVCE_W<'a, REG> = crate::BitWriter<'a, REG>;
1745 ///Field `IVSEL` reader - No Description.
1746 pub type IVSEL_R = crate::BitReader;
1747 ///Field `IVSEL` writer - No Description.
1748 pub type IVSEL_W<'a, REG> = crate::BitWriter<'a, REG>;
1749 ///Field `PUD` reader - No Description.
1750 pub type PUD_R = crate::BitReader;
1751 ///Field `PUD` writer - No Description.
1752 pub type PUD_W<'a, REG> = crate::BitWriter<'a, REG>;
1753 ///Field `BODSE` reader - BOD Sleep Enable
1754 pub type BODSE_R = crate::BitReader;
1755 ///Field `BODSE` writer - BOD Sleep Enable
1756 pub type BODSE_W<'a, REG> = crate::BitWriter<'a, REG>;
1757 ///Field `BODS` reader - BOD Sleep
1758 pub type BODS_R = crate::BitReader;
1759 ///Field `BODS` writer - BOD Sleep
1760 pub type BODS_W<'a, REG> = crate::BitWriter<'a, REG>;
1761 impl R {
1762 ///Bit 0 - No Description.
1763 #[inline(always)]
1764 pub fn ivce(&self) -> IVCE_R {
1765 IVCE_R::new((self.bits & 1) != 0)
1766 }
1767 ///Bit 1 - No Description.
1768 #[inline(always)]
1769 pub fn ivsel(&self) -> IVSEL_R {
1770 IVSEL_R::new(((self.bits >> 1) & 1) != 0)
1771 }
1772 ///Bit 4 - No Description.
1773 #[inline(always)]
1774 pub fn pud(&self) -> PUD_R {
1775 PUD_R::new(((self.bits >> 4) & 1) != 0)
1776 }
1777 ///Bit 5 - BOD Sleep Enable
1778 #[inline(always)]
1779 pub fn bodse(&self) -> BODSE_R {
1780 BODSE_R::new(((self.bits >> 5) & 1) != 0)
1781 }
1782 ///Bit 6 - BOD Sleep
1783 #[inline(always)]
1784 pub fn bods(&self) -> BODS_R {
1785 BODS_R::new(((self.bits >> 6) & 1) != 0)
1786 }
1787 }
1788 impl W {
1789 ///Bit 0 - No Description.
1790 #[inline(always)]
1791 pub fn ivce(&mut self) -> IVCE_W<'_, MCUCR_SPEC> {
1792 IVCE_W::new(self, 0)
1793 }
1794 ///Bit 1 - No Description.
1795 #[inline(always)]
1796 pub fn ivsel(&mut self) -> IVSEL_W<'_, MCUCR_SPEC> {
1797 IVSEL_W::new(self, 1)
1798 }
1799 ///Bit 4 - No Description.
1800 #[inline(always)]
1801 pub fn pud(&mut self) -> PUD_W<'_, MCUCR_SPEC> {
1802 PUD_W::new(self, 4)
1803 }
1804 ///Bit 5 - BOD Sleep Enable
1805 #[inline(always)]
1806 pub fn bodse(&mut self) -> BODSE_W<'_, MCUCR_SPEC> {
1807 BODSE_W::new(self, 5)
1808 }
1809 ///Bit 6 - BOD Sleep
1810 #[inline(always)]
1811 pub fn bods(&mut self) -> BODS_W<'_, MCUCR_SPEC> {
1812 BODS_W::new(self, 6)
1813 }
1814 }
1815 /**MCU Control Register
1816
1817You can [`read`](crate::Reg::read) this register and get [`mcucr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mcucr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
1818 pub struct MCUCR_SPEC;
1819 impl crate::RegisterSpec for MCUCR_SPEC {
1820 type Ux = u8;
1821 }
1822 ///`read()` method returns [`mcucr::R`](R) reader structure
1823 impl crate::Readable for MCUCR_SPEC {}
1824 ///`write(|w| ..)` method takes [`mcucr::W`](W) writer structure
1825 impl crate::Writable for MCUCR_SPEC {
1826 type Safety = crate::Unsafe;
1827 }
1828 ///`reset()` method sets MCUCR to value 0
1829 impl crate::Resettable for MCUCR_SPEC {}
1830 }
1831 /**MCUSR (rw) register accessor: MCU Status Register
1832
1833You can [`read`](crate::Reg::read) this register and get [`mcusr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mcusr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
1834
1835For information about available fields see [`mod@mcusr`] module*/
1836 pub type MCUSR = crate::Reg<mcusr::MCUSR_SPEC>;
1837 ///MCU Status Register
1838 pub mod mcusr {
1839 ///Register `MCUSR` reader
1840 pub type R = crate::R<MCUSR_SPEC>;
1841 ///Register `MCUSR` writer
1842 pub type W = crate::W<MCUSR_SPEC>;
1843 ///Field `PORF` reader - Power-on reset flag
1844 pub type PORF_R = crate::BitReader;
1845 ///Field `PORF` writer - Power-on reset flag
1846 pub type PORF_W<'a, REG> = crate::BitWriter<'a, REG>;
1847 ///Field `EXTRF` reader - External Reset Flag
1848 pub type EXTRF_R = crate::BitReader;
1849 ///Field `EXTRF` writer - External Reset Flag
1850 pub type EXTRF_W<'a, REG> = crate::BitWriter<'a, REG>;
1851 ///Field `BORF` reader - Brown-out Reset Flag
1852 pub type BORF_R = crate::BitReader;
1853 ///Field `BORF` writer - Brown-out Reset Flag
1854 pub type BORF_W<'a, REG> = crate::BitWriter<'a, REG>;
1855 ///Field `WDRF` reader - Watchdog Reset Flag
1856 pub type WDRF_R = crate::BitReader;
1857 ///Field `WDRF` writer - Watchdog Reset Flag
1858 pub type WDRF_W<'a, REG> = crate::BitWriter<'a, REG>;
1859 impl R {
1860 ///Bit 0 - Power-on reset flag
1861 #[inline(always)]
1862 pub fn porf(&self) -> PORF_R {
1863 PORF_R::new((self.bits & 1) != 0)
1864 }
1865 ///Bit 1 - External Reset Flag
1866 #[inline(always)]
1867 pub fn extrf(&self) -> EXTRF_R {
1868 EXTRF_R::new(((self.bits >> 1) & 1) != 0)
1869 }
1870 ///Bit 2 - Brown-out Reset Flag
1871 #[inline(always)]
1872 pub fn borf(&self) -> BORF_R {
1873 BORF_R::new(((self.bits >> 2) & 1) != 0)
1874 }
1875 ///Bit 3 - Watchdog Reset Flag
1876 #[inline(always)]
1877 pub fn wdrf(&self) -> WDRF_R {
1878 WDRF_R::new(((self.bits >> 3) & 1) != 0)
1879 }
1880 }
1881 impl W {
1882 ///Bit 0 - Power-on reset flag
1883 #[inline(always)]
1884 pub fn porf(&mut self) -> PORF_W<'_, MCUSR_SPEC> {
1885 PORF_W::new(self, 0)
1886 }
1887 ///Bit 1 - External Reset Flag
1888 #[inline(always)]
1889 pub fn extrf(&mut self) -> EXTRF_W<'_, MCUSR_SPEC> {
1890 EXTRF_W::new(self, 1)
1891 }
1892 ///Bit 2 - Brown-out Reset Flag
1893 #[inline(always)]
1894 pub fn borf(&mut self) -> BORF_W<'_, MCUSR_SPEC> {
1895 BORF_W::new(self, 2)
1896 }
1897 ///Bit 3 - Watchdog Reset Flag
1898 #[inline(always)]
1899 pub fn wdrf(&mut self) -> WDRF_W<'_, MCUSR_SPEC> {
1900 WDRF_W::new(self, 3)
1901 }
1902 }
1903 /**MCU Status Register
1904
1905You can [`read`](crate::Reg::read) this register and get [`mcusr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mcusr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
1906 pub struct MCUSR_SPEC;
1907 impl crate::RegisterSpec for MCUSR_SPEC {
1908 type Ux = u8;
1909 }
1910 ///`read()` method returns [`mcusr::R`](R) reader structure
1911 impl crate::Readable for MCUSR_SPEC {}
1912 ///`write(|w| ..)` method takes [`mcusr::W`](W) writer structure
1913 impl crate::Writable for MCUSR_SPEC {
1914 type Safety = crate::Unsafe;
1915 }
1916 ///`reset()` method sets MCUSR to value 0
1917 impl crate::Resettable for MCUSR_SPEC {}
1918 }
1919 /**OSCCAL (rw) register accessor: Oscillator Calibration Value
1920
1921You can [`read`](crate::Reg::read) this register and get [`osccal::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`osccal::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
1922
1923For information about available fields see [`mod@osccal`] module*/
1924 pub type OSCCAL = crate::Reg<osccal::OSCCAL_SPEC>;
1925 ///Oscillator Calibration Value
1926 pub mod osccal {
1927 ///Register `OSCCAL` reader
1928 pub type R = crate::R<OSCCAL_SPEC>;
1929 ///Register `OSCCAL` writer
1930 pub type W = crate::W<OSCCAL_SPEC>;
1931 ///Field `OSCCAL` reader - Oscillator Calibration
1932 pub type OSCCAL_R = crate::FieldReader;
1933 ///Field `OSCCAL` writer - Oscillator Calibration
1934 pub type OSCCAL_W<'a, REG> = crate::FieldWriter<'a, REG, 8, u8, crate::Safe>;
1935 impl R {
1936 ///Bits 0:7 - Oscillator Calibration
1937 #[inline(always)]
1938 pub fn osccal(&self) -> OSCCAL_R {
1939 OSCCAL_R::new(self.bits)
1940 }
1941 }
1942 impl W {
1943 ///Bits 0:7 - Oscillator Calibration
1944 #[inline(always)]
1945 pub fn osccal(&mut self) -> OSCCAL_W<'_, OSCCAL_SPEC> {
1946 OSCCAL_W::new(self, 0)
1947 }
1948 }
1949 /**Oscillator Calibration Value
1950
1951You can [`read`](crate::Reg::read) this register and get [`osccal::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`osccal::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
1952 pub struct OSCCAL_SPEC;
1953 impl crate::RegisterSpec for OSCCAL_SPEC {
1954 type Ux = u8;
1955 }
1956 ///`read()` method returns [`osccal::R`](R) reader structure
1957 impl crate::Readable for OSCCAL_SPEC {}
1958 ///`write(|w| ..)` method takes [`osccal::W`](W) writer structure
1959 impl crate::Writable for OSCCAL_SPEC {
1960 type Safety = crate::Safe;
1961 }
1962 ///`reset()` method sets OSCCAL to value 0
1963 impl crate::Resettable for OSCCAL_SPEC {}
1964 }
1965 /**PRR (rw) register accessor: Power Reduction Register
1966
1967You can [`read`](crate::Reg::read) this register and get [`prr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`prr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
1968
1969For information about available fields see [`mod@prr`] module*/
1970 pub type PRR = crate::Reg<prr::PRR_SPEC>;
1971 ///Power Reduction Register
1972 pub mod prr {
1973 ///Register `PRR` reader
1974 pub type R = crate::R<PRR_SPEC>;
1975 ///Register `PRR` writer
1976 pub type W = crate::W<PRR_SPEC>;
1977 ///Field `PRADC` reader - Power Reduction ADC
1978 pub type PRADC_R = crate::BitReader;
1979 ///Field `PRADC` writer - Power Reduction ADC
1980 pub type PRADC_W<'a, REG> = crate::BitWriter<'a, REG>;
1981 ///Field `PRUSART0` reader - Power Reduction USART
1982 pub type PRUSART0_R = crate::BitReader;
1983 ///Field `PRUSART0` writer - Power Reduction USART
1984 pub type PRUSART0_W<'a, REG> = crate::BitWriter<'a, REG>;
1985 ///Field `PRSPI` reader - Power Reduction Serial Peripheral Interface
1986 pub type PRSPI_R = crate::BitReader;
1987 ///Field `PRSPI` writer - Power Reduction Serial Peripheral Interface
1988 pub type PRSPI_W<'a, REG> = crate::BitWriter<'a, REG>;
1989 ///Field `PRTIM1` reader - Power Reduction Timer/Counter1
1990 pub type PRTIM1_R = crate::BitReader;
1991 ///Field `PRTIM1` writer - Power Reduction Timer/Counter1
1992 pub type PRTIM1_W<'a, REG> = crate::BitWriter<'a, REG>;
1993 ///Field `PRTIM0` reader - Power Reduction Timer/Counter0
1994 pub type PRTIM0_R = crate::BitReader;
1995 ///Field `PRTIM0` writer - Power Reduction Timer/Counter0
1996 pub type PRTIM0_W<'a, REG> = crate::BitWriter<'a, REG>;
1997 ///Field `PRTIM2` reader - Power Reduction Timer/Counter2
1998 pub type PRTIM2_R = crate::BitReader;
1999 ///Field `PRTIM2` writer - Power Reduction Timer/Counter2
2000 pub type PRTIM2_W<'a, REG> = crate::BitWriter<'a, REG>;
2001 ///Field `PRTWI` reader - Power Reduction TWI
2002 pub type PRTWI_R = crate::BitReader;
2003 ///Field `PRTWI` writer - Power Reduction TWI
2004 pub type PRTWI_W<'a, REG> = crate::BitWriter<'a, REG>;
2005 impl R {
2006 ///Bit 0 - Power Reduction ADC
2007 #[inline(always)]
2008 pub fn pradc(&self) -> PRADC_R {
2009 PRADC_R::new((self.bits & 1) != 0)
2010 }
2011 ///Bit 1 - Power Reduction USART
2012 #[inline(always)]
2013 pub fn prusart0(&self) -> PRUSART0_R {
2014 PRUSART0_R::new(((self.bits >> 1) & 1) != 0)
2015 }
2016 ///Bit 2 - Power Reduction Serial Peripheral Interface
2017 #[inline(always)]
2018 pub fn prspi(&self) -> PRSPI_R {
2019 PRSPI_R::new(((self.bits >> 2) & 1) != 0)
2020 }
2021 ///Bit 3 - Power Reduction Timer/Counter1
2022 #[inline(always)]
2023 pub fn prtim1(&self) -> PRTIM1_R {
2024 PRTIM1_R::new(((self.bits >> 3) & 1) != 0)
2025 }
2026 ///Bit 5 - Power Reduction Timer/Counter0
2027 #[inline(always)]
2028 pub fn prtim0(&self) -> PRTIM0_R {
2029 PRTIM0_R::new(((self.bits >> 5) & 1) != 0)
2030 }
2031 ///Bit 6 - Power Reduction Timer/Counter2
2032 #[inline(always)]
2033 pub fn prtim2(&self) -> PRTIM2_R {
2034 PRTIM2_R::new(((self.bits >> 6) & 1) != 0)
2035 }
2036 ///Bit 7 - Power Reduction TWI
2037 #[inline(always)]
2038 pub fn prtwi(&self) -> PRTWI_R {
2039 PRTWI_R::new(((self.bits >> 7) & 1) != 0)
2040 }
2041 }
2042 impl W {
2043 ///Bit 0 - Power Reduction ADC
2044 #[inline(always)]
2045 pub fn pradc(&mut self) -> PRADC_W<'_, PRR_SPEC> {
2046 PRADC_W::new(self, 0)
2047 }
2048 ///Bit 1 - Power Reduction USART
2049 #[inline(always)]
2050 pub fn prusart0(&mut self) -> PRUSART0_W<'_, PRR_SPEC> {
2051 PRUSART0_W::new(self, 1)
2052 }
2053 ///Bit 2 - Power Reduction Serial Peripheral Interface
2054 #[inline(always)]
2055 pub fn prspi(&mut self) -> PRSPI_W<'_, PRR_SPEC> {
2056 PRSPI_W::new(self, 2)
2057 }
2058 ///Bit 3 - Power Reduction Timer/Counter1
2059 #[inline(always)]
2060 pub fn prtim1(&mut self) -> PRTIM1_W<'_, PRR_SPEC> {
2061 PRTIM1_W::new(self, 3)
2062 }
2063 ///Bit 5 - Power Reduction Timer/Counter0
2064 #[inline(always)]
2065 pub fn prtim0(&mut self) -> PRTIM0_W<'_, PRR_SPEC> {
2066 PRTIM0_W::new(self, 5)
2067 }
2068 ///Bit 6 - Power Reduction Timer/Counter2
2069 #[inline(always)]
2070 pub fn prtim2(&mut self) -> PRTIM2_W<'_, PRR_SPEC> {
2071 PRTIM2_W::new(self, 6)
2072 }
2073 ///Bit 7 - Power Reduction TWI
2074 #[inline(always)]
2075 pub fn prtwi(&mut self) -> PRTWI_W<'_, PRR_SPEC> {
2076 PRTWI_W::new(self, 7)
2077 }
2078 }
2079 /**Power Reduction Register
2080
2081You can [`read`](crate::Reg::read) this register and get [`prr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`prr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
2082 pub struct PRR_SPEC;
2083 impl crate::RegisterSpec for PRR_SPEC {
2084 type Ux = u8;
2085 }
2086 ///`read()` method returns [`prr::R`](R) reader structure
2087 impl crate::Readable for PRR_SPEC {}
2088 ///`write(|w| ..)` method takes [`prr::W`](W) writer structure
2089 impl crate::Writable for PRR_SPEC {
2090 type Safety = crate::Unsafe;
2091 }
2092 ///`reset()` method sets PRR to value 0
2093 impl crate::Resettable for PRR_SPEC {}
2094 }
2095 /**SMCR (rw) register accessor: Sleep Mode Control Register
2096
2097You can [`read`](crate::Reg::read) this register and get [`smcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`smcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
2098
2099For information about available fields see [`mod@smcr`] module*/
2100 pub type SMCR = crate::Reg<smcr::SMCR_SPEC>;
2101 ///Sleep Mode Control Register
2102 pub mod smcr {
2103 ///Register `SMCR` reader
2104 pub type R = crate::R<SMCR_SPEC>;
2105 ///Register `SMCR` writer
2106 pub type W = crate::W<SMCR_SPEC>;
2107 ///Field `SE` reader - Sleep Enable
2108 pub type SE_R = crate::BitReader;
2109 ///Field `SE` writer - Sleep Enable
2110 pub type SE_W<'a, REG> = crate::BitWriter<'a, REG>;
2111 /**Sleep Mode Select Bits
2112
2113Value on reset: 0*/
2114 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
2115 #[repr(u8)]
2116 pub enum SM_A {
2117 ///0: Idle
2118 IDLE = 0,
2119 ///1: ADC Noise Reduction (If Available)
2120 ADC = 1,
2121 ///2: Power Down
2122 PDOWN = 2,
2123 ///3: Power Save
2124 PSAVE = 3,
2125 ///4: Reserved
2126 VAL_0X04 = 4,
2127 ///5: Reserved
2128 VAL_0X05 = 5,
2129 ///6: Standby
2130 STDBY = 6,
2131 ///7: Extended Standby
2132 ESTDBY = 7,
2133 }
2134 impl From<SM_A> for u8 {
2135 #[inline(always)]
2136 fn from(variant: SM_A) -> Self {
2137 variant as _
2138 }
2139 }
2140 impl crate::FieldSpec for SM_A {
2141 type Ux = u8;
2142 }
2143 impl crate::IsEnum for SM_A {}
2144 ///Field `SM` reader - Sleep Mode Select Bits
2145 pub type SM_R = crate::FieldReader<SM_A>;
2146 impl SM_R {
2147 ///Get enumerated values variant
2148 #[inline(always)]
2149 pub const fn variant(&self) -> SM_A {
2150 match self.bits {
2151 0 => SM_A::IDLE,
2152 1 => SM_A::ADC,
2153 2 => SM_A::PDOWN,
2154 3 => SM_A::PSAVE,
2155 4 => SM_A::VAL_0X04,
2156 5 => SM_A::VAL_0X05,
2157 6 => SM_A::STDBY,
2158 7 => SM_A::ESTDBY,
2159 _ => unreachable!(),
2160 }
2161 }
2162 ///Idle
2163 #[inline(always)]
2164 pub fn is_idle(&self) -> bool {
2165 *self == SM_A::IDLE
2166 }
2167 ///ADC Noise Reduction (If Available)
2168 #[inline(always)]
2169 pub fn is_adc(&self) -> bool {
2170 *self == SM_A::ADC
2171 }
2172 ///Power Down
2173 #[inline(always)]
2174 pub fn is_pdown(&self) -> bool {
2175 *self == SM_A::PDOWN
2176 }
2177 ///Power Save
2178 #[inline(always)]
2179 pub fn is_psave(&self) -> bool {
2180 *self == SM_A::PSAVE
2181 }
2182 ///Reserved
2183 #[inline(always)]
2184 pub fn is_val_0x04(&self) -> bool {
2185 *self == SM_A::VAL_0X04
2186 }
2187 ///Reserved
2188 #[inline(always)]
2189 pub fn is_val_0x05(&self) -> bool {
2190 *self == SM_A::VAL_0X05
2191 }
2192 ///Standby
2193 #[inline(always)]
2194 pub fn is_stdby(&self) -> bool {
2195 *self == SM_A::STDBY
2196 }
2197 ///Extended Standby
2198 #[inline(always)]
2199 pub fn is_estdby(&self) -> bool {
2200 *self == SM_A::ESTDBY
2201 }
2202 }
2203 ///Field `SM` writer - Sleep Mode Select Bits
2204 pub type SM_W<'a, REG> = crate::FieldWriter<'a, REG, 3, SM_A, crate::Safe>;
2205 impl<'a, REG> SM_W<'a, REG>
2206 where
2207 REG: crate::Writable + crate::RegisterSpec,
2208 REG::Ux: From<u8>,
2209 {
2210 ///Idle
2211 #[inline(always)]
2212 pub fn idle(self) -> &'a mut crate::W<REG> {
2213 self.variant(SM_A::IDLE)
2214 }
2215 ///ADC Noise Reduction (If Available)
2216 #[inline(always)]
2217 pub fn adc(self) -> &'a mut crate::W<REG> {
2218 self.variant(SM_A::ADC)
2219 }
2220 ///Power Down
2221 #[inline(always)]
2222 pub fn pdown(self) -> &'a mut crate::W<REG> {
2223 self.variant(SM_A::PDOWN)
2224 }
2225 ///Power Save
2226 #[inline(always)]
2227 pub fn psave(self) -> &'a mut crate::W<REG> {
2228 self.variant(SM_A::PSAVE)
2229 }
2230 ///Reserved
2231 #[inline(always)]
2232 pub fn val_0x04(self) -> &'a mut crate::W<REG> {
2233 self.variant(SM_A::VAL_0X04)
2234 }
2235 ///Reserved
2236 #[inline(always)]
2237 pub fn val_0x05(self) -> &'a mut crate::W<REG> {
2238 self.variant(SM_A::VAL_0X05)
2239 }
2240 ///Standby
2241 #[inline(always)]
2242 pub fn stdby(self) -> &'a mut crate::W<REG> {
2243 self.variant(SM_A::STDBY)
2244 }
2245 ///Extended Standby
2246 #[inline(always)]
2247 pub fn estdby(self) -> &'a mut crate::W<REG> {
2248 self.variant(SM_A::ESTDBY)
2249 }
2250 }
2251 impl R {
2252 ///Bit 0 - Sleep Enable
2253 #[inline(always)]
2254 pub fn se(&self) -> SE_R {
2255 SE_R::new((self.bits & 1) != 0)
2256 }
2257 ///Bits 1:3 - Sleep Mode Select Bits
2258 #[inline(always)]
2259 pub fn sm(&self) -> SM_R {
2260 SM_R::new((self.bits >> 1) & 7)
2261 }
2262 }
2263 impl W {
2264 ///Bit 0 - Sleep Enable
2265 #[inline(always)]
2266 pub fn se(&mut self) -> SE_W<'_, SMCR_SPEC> {
2267 SE_W::new(self, 0)
2268 }
2269 ///Bits 1:3 - Sleep Mode Select Bits
2270 #[inline(always)]
2271 pub fn sm(&mut self) -> SM_W<'_, SMCR_SPEC> {
2272 SM_W::new(self, 1)
2273 }
2274 }
2275 /**Sleep Mode Control Register
2276
2277You can [`read`](crate::Reg::read) this register and get [`smcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`smcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
2278 pub struct SMCR_SPEC;
2279 impl crate::RegisterSpec for SMCR_SPEC {
2280 type Ux = u8;
2281 }
2282 ///`read()` method returns [`smcr::R`](R) reader structure
2283 impl crate::Readable for SMCR_SPEC {}
2284 ///`write(|w| ..)` method takes [`smcr::W`](W) writer structure
2285 impl crate::Writable for SMCR_SPEC {
2286 type Safety = crate::Unsafe;
2287 }
2288 ///`reset()` method sets SMCR to value 0
2289 impl crate::Resettable for SMCR_SPEC {}
2290 }
2291 /**SPMCSR (rw) register accessor: Store Program Memory Control and Status Register
2292
2293You can [`read`](crate::Reg::read) this register and get [`spmcsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spmcsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
2294
2295For information about available fields see [`mod@spmcsr`] module*/
2296 pub type SPMCSR = crate::Reg<spmcsr::SPMCSR_SPEC>;
2297 ///Store Program Memory Control and Status Register
2298 pub mod spmcsr {
2299 ///Register `SPMCSR` reader
2300 pub type R = crate::R<SPMCSR_SPEC>;
2301 ///Register `SPMCSR` writer
2302 pub type W = crate::W<SPMCSR_SPEC>;
2303 ///Field `SPMEN` reader - Store Program Memory
2304 pub type SPMEN_R = crate::BitReader;
2305 ///Field `SPMEN` writer - Store Program Memory
2306 pub type SPMEN_W<'a, REG> = crate::BitWriter<'a, REG>;
2307 ///Field `PGERS` reader - Page Erase
2308 pub type PGERS_R = crate::BitReader;
2309 ///Field `PGERS` writer - Page Erase
2310 pub type PGERS_W<'a, REG> = crate::BitWriter<'a, REG>;
2311 ///Field `PGWRT` reader - Page Write
2312 pub type PGWRT_R = crate::BitReader;
2313 ///Field `PGWRT` writer - Page Write
2314 pub type PGWRT_W<'a, REG> = crate::BitWriter<'a, REG>;
2315 ///Field `BLBSET` reader - Boot Lock Bit Set
2316 pub type BLBSET_R = crate::BitReader;
2317 ///Field `BLBSET` writer - Boot Lock Bit Set
2318 pub type BLBSET_W<'a, REG> = crate::BitWriter<'a, REG>;
2319 ///Field `RWWSRE` reader - Read-While-Write section read enable
2320 pub type RWWSRE_R = crate::BitReader;
2321 ///Field `RWWSRE` writer - Read-While-Write section read enable
2322 pub type RWWSRE_W<'a, REG> = crate::BitWriter<'a, REG>;
2323 ///Field `SIGRD` reader - Signature Row Read
2324 pub type SIGRD_R = crate::BitReader;
2325 ///Field `SIGRD` writer - Signature Row Read
2326 pub type SIGRD_W<'a, REG> = crate::BitWriter<'a, REG>;
2327 ///Field `RWWSB` reader - Read-While-Write Section Busy
2328 pub type RWWSB_R = crate::BitReader;
2329 ///Field `RWWSB` writer - Read-While-Write Section Busy
2330 pub type RWWSB_W<'a, REG> = crate::BitWriter<'a, REG>;
2331 ///Field `SPMIE` reader - SPM Interrupt Enable
2332 pub type SPMIE_R = crate::BitReader;
2333 ///Field `SPMIE` writer - SPM Interrupt Enable
2334 pub type SPMIE_W<'a, REG> = crate::BitWriter<'a, REG>;
2335 impl R {
2336 ///Bit 0 - Store Program Memory
2337 #[inline(always)]
2338 pub fn spmen(&self) -> SPMEN_R {
2339 SPMEN_R::new((self.bits & 1) != 0)
2340 }
2341 ///Bit 1 - Page Erase
2342 #[inline(always)]
2343 pub fn pgers(&self) -> PGERS_R {
2344 PGERS_R::new(((self.bits >> 1) & 1) != 0)
2345 }
2346 ///Bit 2 - Page Write
2347 #[inline(always)]
2348 pub fn pgwrt(&self) -> PGWRT_R {
2349 PGWRT_R::new(((self.bits >> 2) & 1) != 0)
2350 }
2351 ///Bit 3 - Boot Lock Bit Set
2352 #[inline(always)]
2353 pub fn blbset(&self) -> BLBSET_R {
2354 BLBSET_R::new(((self.bits >> 3) & 1) != 0)
2355 }
2356 ///Bit 4 - Read-While-Write section read enable
2357 #[inline(always)]
2358 pub fn rwwsre(&self) -> RWWSRE_R {
2359 RWWSRE_R::new(((self.bits >> 4) & 1) != 0)
2360 }
2361 ///Bit 5 - Signature Row Read
2362 #[inline(always)]
2363 pub fn sigrd(&self) -> SIGRD_R {
2364 SIGRD_R::new(((self.bits >> 5) & 1) != 0)
2365 }
2366 ///Bit 6 - Read-While-Write Section Busy
2367 #[inline(always)]
2368 pub fn rwwsb(&self) -> RWWSB_R {
2369 RWWSB_R::new(((self.bits >> 6) & 1) != 0)
2370 }
2371 ///Bit 7 - SPM Interrupt Enable
2372 #[inline(always)]
2373 pub fn spmie(&self) -> SPMIE_R {
2374 SPMIE_R::new(((self.bits >> 7) & 1) != 0)
2375 }
2376 }
2377 impl W {
2378 ///Bit 0 - Store Program Memory
2379 #[inline(always)]
2380 pub fn spmen(&mut self) -> SPMEN_W<'_, SPMCSR_SPEC> {
2381 SPMEN_W::new(self, 0)
2382 }
2383 ///Bit 1 - Page Erase
2384 #[inline(always)]
2385 pub fn pgers(&mut self) -> PGERS_W<'_, SPMCSR_SPEC> {
2386 PGERS_W::new(self, 1)
2387 }
2388 ///Bit 2 - Page Write
2389 #[inline(always)]
2390 pub fn pgwrt(&mut self) -> PGWRT_W<'_, SPMCSR_SPEC> {
2391 PGWRT_W::new(self, 2)
2392 }
2393 ///Bit 3 - Boot Lock Bit Set
2394 #[inline(always)]
2395 pub fn blbset(&mut self) -> BLBSET_W<'_, SPMCSR_SPEC> {
2396 BLBSET_W::new(self, 3)
2397 }
2398 ///Bit 4 - Read-While-Write section read enable
2399 #[inline(always)]
2400 pub fn rwwsre(&mut self) -> RWWSRE_W<'_, SPMCSR_SPEC> {
2401 RWWSRE_W::new(self, 4)
2402 }
2403 ///Bit 5 - Signature Row Read
2404 #[inline(always)]
2405 pub fn sigrd(&mut self) -> SIGRD_W<'_, SPMCSR_SPEC> {
2406 SIGRD_W::new(self, 5)
2407 }
2408 ///Bit 6 - Read-While-Write Section Busy
2409 #[inline(always)]
2410 pub fn rwwsb(&mut self) -> RWWSB_W<'_, SPMCSR_SPEC> {
2411 RWWSB_W::new(self, 6)
2412 }
2413 ///Bit 7 - SPM Interrupt Enable
2414 #[inline(always)]
2415 pub fn spmie(&mut self) -> SPMIE_W<'_, SPMCSR_SPEC> {
2416 SPMIE_W::new(self, 7)
2417 }
2418 }
2419 /**Store Program Memory Control and Status Register
2420
2421You can [`read`](crate::Reg::read) this register and get [`spmcsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spmcsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
2422 pub struct SPMCSR_SPEC;
2423 impl crate::RegisterSpec for SPMCSR_SPEC {
2424 type Ux = u8;
2425 }
2426 ///`read()` method returns [`spmcsr::R`](R) reader structure
2427 impl crate::Readable for SPMCSR_SPEC {}
2428 ///`write(|w| ..)` method takes [`spmcsr::W`](W) writer structure
2429 impl crate::Writable for SPMCSR_SPEC {
2430 type Safety = crate::Unsafe;
2431 }
2432 ///`reset()` method sets SPMCSR to value 0
2433 impl crate::Resettable for SPMCSR_SPEC {}
2434 }
2435}
2436///EEPROM
2437pub type EEPROM = crate::Periph<eeprom::RegisterBlock, 0x3f>;
2438impl core::fmt::Debug for EEPROM {
2439 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2440 f.debug_struct("EEPROM").finish()
2441 }
2442}
2443///EEPROM
2444pub mod eeprom {
2445 #[repr(C)]
2446 ///Register block
2447 pub struct RegisterBlock {
2448 eecr: EECR,
2449 eedr: EEDR,
2450 eear: EEAR,
2451 }
2452 impl RegisterBlock {
2453 ///0x00 - EEPROM Control Register
2454 #[inline(always)]
2455 pub const fn eecr(&self) -> &EECR {
2456 &self.eecr
2457 }
2458 ///0x01 - EEPROM Data Register
2459 #[inline(always)]
2460 pub const fn eedr(&self) -> &EEDR {
2461 &self.eedr
2462 }
2463 ///0x02 - EEPROM Address Register Bytes
2464 #[inline(always)]
2465 pub const fn eear(&self) -> &EEAR {
2466 &self.eear
2467 }
2468 }
2469 /**EEAR (rw) register accessor: EEPROM Address Register Bytes
2470
2471You can [`read`](crate::Reg::read) this register and get [`eear::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eear::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
2472
2473For information about available fields see [`mod@eear`] module*/
2474 pub type EEAR = crate::Reg<eear::EEAR_SPEC>;
2475 ///EEPROM Address Register Bytes
2476 pub mod eear {
2477 ///Register `EEAR` reader
2478 pub type R = crate::R<EEAR_SPEC>;
2479 ///Register `EEAR` writer
2480 pub type W = crate::W<EEAR_SPEC>;
2481 impl core::fmt::Debug for R {
2482 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2483 write!(f, "{}", self.bits())
2484 }
2485 }
2486 impl W {}
2487 /**EEPROM Address Register Bytes
2488
2489You can [`read`](crate::Reg::read) this register and get [`eear::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eear::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
2490 pub struct EEAR_SPEC;
2491 impl crate::RegisterSpec for EEAR_SPEC {
2492 type Ux = u16;
2493 }
2494 ///`read()` method returns [`eear::R`](R) reader structure
2495 impl crate::Readable for EEAR_SPEC {}
2496 ///`write(|w| ..)` method takes [`eear::W`](W) writer structure
2497 impl crate::Writable for EEAR_SPEC {
2498 type Safety = crate::Safe;
2499 }
2500 ///`reset()` method sets EEAR to value 0
2501 impl crate::Resettable for EEAR_SPEC {}
2502 }
2503 /**EECR (rw) register accessor: EEPROM Control Register
2504
2505You can [`read`](crate::Reg::read) this register and get [`eecr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eecr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
2506
2507For information about available fields see [`mod@eecr`] module*/
2508 pub type EECR = crate::Reg<eecr::EECR_SPEC>;
2509 ///EEPROM Control Register
2510 pub mod eecr {
2511 ///Register `EECR` reader
2512 pub type R = crate::R<EECR_SPEC>;
2513 ///Register `EECR` writer
2514 pub type W = crate::W<EECR_SPEC>;
2515 ///Field `EERE` reader - EEPROM Read Enable
2516 pub type EERE_R = crate::BitReader;
2517 ///Field `EERE` writer - EEPROM Read Enable
2518 pub type EERE_W<'a, REG> = crate::BitWriter<'a, REG>;
2519 ///Field `EEPE` reader - EEPROM Write Enable
2520 pub type EEPE_R = crate::BitReader;
2521 ///Field `EEPE` writer - EEPROM Write Enable
2522 pub type EEPE_W<'a, REG> = crate::BitWriter<'a, REG>;
2523 ///Field `EEMPE` reader - EEPROM Master Write Enable
2524 pub type EEMPE_R = crate::BitReader;
2525 ///Field `EEMPE` writer - EEPROM Master Write Enable
2526 pub type EEMPE_W<'a, REG> = crate::BitWriter<'a, REG>;
2527 ///Field `EERIE` reader - EEPROM Ready Interrupt Enable
2528 pub type EERIE_R = crate::BitReader;
2529 ///Field `EERIE` writer - EEPROM Ready Interrupt Enable
2530 pub type EERIE_W<'a, REG> = crate::BitWriter<'a, REG>;
2531 /**EEPROM Programming Mode Bits
2532
2533Value on reset: 0*/
2534 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
2535 #[repr(u8)]
2536 pub enum EEPM_A {
2537 ///0: Erase and Write in one operation
2538 VAL_0X00 = 0,
2539 ///1: Erase Only
2540 VAL_0X01 = 1,
2541 ///2: Write Only
2542 VAL_0X02 = 2,
2543 }
2544 impl From<EEPM_A> for u8 {
2545 #[inline(always)]
2546 fn from(variant: EEPM_A) -> Self {
2547 variant as _
2548 }
2549 }
2550 impl crate::FieldSpec for EEPM_A {
2551 type Ux = u8;
2552 }
2553 impl crate::IsEnum for EEPM_A {}
2554 ///Field `EEPM` reader - EEPROM Programming Mode Bits
2555 pub type EEPM_R = crate::FieldReader<EEPM_A>;
2556 impl EEPM_R {
2557 ///Get enumerated values variant
2558 #[inline(always)]
2559 pub const fn variant(&self) -> Option<EEPM_A> {
2560 match self.bits {
2561 0 => Some(EEPM_A::VAL_0X00),
2562 1 => Some(EEPM_A::VAL_0X01),
2563 2 => Some(EEPM_A::VAL_0X02),
2564 _ => None,
2565 }
2566 }
2567 ///Erase and Write in one operation
2568 #[inline(always)]
2569 pub fn is_val_0x00(&self) -> bool {
2570 *self == EEPM_A::VAL_0X00
2571 }
2572 ///Erase Only
2573 #[inline(always)]
2574 pub fn is_val_0x01(&self) -> bool {
2575 *self == EEPM_A::VAL_0X01
2576 }
2577 ///Write Only
2578 #[inline(always)]
2579 pub fn is_val_0x02(&self) -> bool {
2580 *self == EEPM_A::VAL_0X02
2581 }
2582 }
2583 ///Field `EEPM` writer - EEPROM Programming Mode Bits
2584 pub type EEPM_W<'a, REG> = crate::FieldWriter<'a, REG, 2, EEPM_A>;
2585 impl<'a, REG> EEPM_W<'a, REG>
2586 where
2587 REG: crate::Writable + crate::RegisterSpec,
2588 REG::Ux: From<u8>,
2589 {
2590 ///Erase and Write in one operation
2591 #[inline(always)]
2592 pub fn val_0x00(self) -> &'a mut crate::W<REG> {
2593 self.variant(EEPM_A::VAL_0X00)
2594 }
2595 ///Erase Only
2596 #[inline(always)]
2597 pub fn val_0x01(self) -> &'a mut crate::W<REG> {
2598 self.variant(EEPM_A::VAL_0X01)
2599 }
2600 ///Write Only
2601 #[inline(always)]
2602 pub fn val_0x02(self) -> &'a mut crate::W<REG> {
2603 self.variant(EEPM_A::VAL_0X02)
2604 }
2605 }
2606 impl R {
2607 ///Bit 0 - EEPROM Read Enable
2608 #[inline(always)]
2609 pub fn eere(&self) -> EERE_R {
2610 EERE_R::new((self.bits & 1) != 0)
2611 }
2612 ///Bit 1 - EEPROM Write Enable
2613 #[inline(always)]
2614 pub fn eepe(&self) -> EEPE_R {
2615 EEPE_R::new(((self.bits >> 1) & 1) != 0)
2616 }
2617 ///Bit 2 - EEPROM Master Write Enable
2618 #[inline(always)]
2619 pub fn eempe(&self) -> EEMPE_R {
2620 EEMPE_R::new(((self.bits >> 2) & 1) != 0)
2621 }
2622 ///Bit 3 - EEPROM Ready Interrupt Enable
2623 #[inline(always)]
2624 pub fn eerie(&self) -> EERIE_R {
2625 EERIE_R::new(((self.bits >> 3) & 1) != 0)
2626 }
2627 ///Bits 4:5 - EEPROM Programming Mode Bits
2628 #[inline(always)]
2629 pub fn eepm(&self) -> EEPM_R {
2630 EEPM_R::new((self.bits >> 4) & 3)
2631 }
2632 }
2633 impl W {
2634 ///Bit 0 - EEPROM Read Enable
2635 #[inline(always)]
2636 pub fn eere(&mut self) -> EERE_W<'_, EECR_SPEC> {
2637 EERE_W::new(self, 0)
2638 }
2639 ///Bit 1 - EEPROM Write Enable
2640 #[inline(always)]
2641 pub fn eepe(&mut self) -> EEPE_W<'_, EECR_SPEC> {
2642 EEPE_W::new(self, 1)
2643 }
2644 ///Bit 2 - EEPROM Master Write Enable
2645 #[inline(always)]
2646 pub fn eempe(&mut self) -> EEMPE_W<'_, EECR_SPEC> {
2647 EEMPE_W::new(self, 2)
2648 }
2649 ///Bit 3 - EEPROM Ready Interrupt Enable
2650 #[inline(always)]
2651 pub fn eerie(&mut self) -> EERIE_W<'_, EECR_SPEC> {
2652 EERIE_W::new(self, 3)
2653 }
2654 ///Bits 4:5 - EEPROM Programming Mode Bits
2655 #[inline(always)]
2656 pub fn eepm(&mut self) -> EEPM_W<'_, EECR_SPEC> {
2657 EEPM_W::new(self, 4)
2658 }
2659 }
2660 /**EEPROM Control Register
2661
2662You can [`read`](crate::Reg::read) this register and get [`eecr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eecr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
2663 pub struct EECR_SPEC;
2664 impl crate::RegisterSpec for EECR_SPEC {
2665 type Ux = u8;
2666 }
2667 ///`read()` method returns [`eecr::R`](R) reader structure
2668 impl crate::Readable for EECR_SPEC {}
2669 ///`write(|w| ..)` method takes [`eecr::W`](W) writer structure
2670 impl crate::Writable for EECR_SPEC {
2671 type Safety = crate::Unsafe;
2672 }
2673 ///`reset()` method sets EECR to value 0
2674 impl crate::Resettable for EECR_SPEC {}
2675 }
2676 /**EEDR (rw) register accessor: EEPROM Data Register
2677
2678You can [`read`](crate::Reg::read) this register and get [`eedr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eedr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
2679
2680For information about available fields see [`mod@eedr`] module*/
2681 pub type EEDR = crate::Reg<eedr::EEDR_SPEC>;
2682 ///EEPROM Data Register
2683 pub mod eedr {
2684 ///Register `EEDR` reader
2685 pub type R = crate::R<EEDR_SPEC>;
2686 ///Register `EEDR` writer
2687 pub type W = crate::W<EEDR_SPEC>;
2688 impl core::fmt::Debug for R {
2689 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2690 write!(f, "{}", self.bits())
2691 }
2692 }
2693 impl W {}
2694 /**EEPROM Data Register
2695
2696You can [`read`](crate::Reg::read) this register and get [`eedr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eedr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
2697 pub struct EEDR_SPEC;
2698 impl crate::RegisterSpec for EEDR_SPEC {
2699 type Ux = u8;
2700 }
2701 ///`read()` method returns [`eedr::R`](R) reader structure
2702 impl crate::Readable for EEDR_SPEC {}
2703 ///`write(|w| ..)` method takes [`eedr::W`](W) writer structure
2704 impl crate::Writable for EEDR_SPEC {
2705 type Safety = crate::Safe;
2706 }
2707 ///`reset()` method sets EEDR to value 0
2708 impl crate::Resettable for EEDR_SPEC {}
2709 }
2710}
2711///External Interrupts
2712pub type EXINT = crate::Periph<exint::RegisterBlock, 0x3b>;
2713impl core::fmt::Debug for EXINT {
2714 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2715 f.debug_struct("EXINT").finish()
2716 }
2717}
2718///External Interrupts
2719pub mod exint {
2720 #[repr(C)]
2721 ///Register block
2722 pub struct RegisterBlock {
2723 pcifr: PCIFR,
2724 eifr: EIFR,
2725 eimsk: EIMSK,
2726 _reserved3: [u8; 0x2a],
2727 pcicr: PCICR,
2728 eicra: EICRA,
2729 _reserved5: [u8; 0x01],
2730 pcmsk0: PCMSK0,
2731 pcmsk1: PCMSK1,
2732 pcmsk2: PCMSK2,
2733 }
2734 impl RegisterBlock {
2735 ///0x00 - Pin Change Interrupt Flag Register
2736 #[inline(always)]
2737 pub const fn pcifr(&self) -> &PCIFR {
2738 &self.pcifr
2739 }
2740 ///0x01 - External Interrupt Flag Register
2741 #[inline(always)]
2742 pub const fn eifr(&self) -> &EIFR {
2743 &self.eifr
2744 }
2745 ///0x02 - External Interrupt Mask Register
2746 #[inline(always)]
2747 pub const fn eimsk(&self) -> &EIMSK {
2748 &self.eimsk
2749 }
2750 ///0x2d - Pin Change Interrupt Control Register
2751 #[inline(always)]
2752 pub const fn pcicr(&self) -> &PCICR {
2753 &self.pcicr
2754 }
2755 ///0x2e - External Interrupt Control Register
2756 #[inline(always)]
2757 pub const fn eicra(&self) -> &EICRA {
2758 &self.eicra
2759 }
2760 ///0x30 - Pin Change Mask Register 0
2761 #[inline(always)]
2762 pub const fn pcmsk0(&self) -> &PCMSK0 {
2763 &self.pcmsk0
2764 }
2765 ///0x31 - Pin Change Mask Register 1
2766 #[inline(always)]
2767 pub const fn pcmsk1(&self) -> &PCMSK1 {
2768 &self.pcmsk1
2769 }
2770 ///0x32 - Pin Change Mask Register 2
2771 #[inline(always)]
2772 pub const fn pcmsk2(&self) -> &PCMSK2 {
2773 &self.pcmsk2
2774 }
2775 }
2776 /**EICRA (rw) register accessor: External Interrupt Control Register
2777
2778You can [`read`](crate::Reg::read) this register and get [`eicra::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eicra::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
2779
2780For information about available fields see [`mod@eicra`] module*/
2781 pub type EICRA = crate::Reg<eicra::EICRA_SPEC>;
2782 ///External Interrupt Control Register
2783 pub mod eicra {
2784 ///Register `EICRA` reader
2785 pub type R = crate::R<EICRA_SPEC>;
2786 ///Register `EICRA` writer
2787 pub type W = crate::W<EICRA_SPEC>;
2788 /**External Interrupt Sense Control 0 Bits
2789
2790Value on reset: 0*/
2791 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
2792 #[repr(u8)]
2793 pub enum ISC0_A {
2794 ///0: Low Level of INTX
2795 VAL_0X00 = 0,
2796 ///1: Any Logical Change of INTX
2797 VAL_0X01 = 1,
2798 ///2: Falling Edge of INTX
2799 VAL_0X02 = 2,
2800 ///3: Rising Edge of INTX
2801 VAL_0X03 = 3,
2802 }
2803 impl From<ISC0_A> for u8 {
2804 #[inline(always)]
2805 fn from(variant: ISC0_A) -> Self {
2806 variant as _
2807 }
2808 }
2809 impl crate::FieldSpec for ISC0_A {
2810 type Ux = u8;
2811 }
2812 impl crate::IsEnum for ISC0_A {}
2813 ///Field `ISC0` reader - External Interrupt Sense Control 0 Bits
2814 pub type ISC0_R = crate::FieldReader<ISC0_A>;
2815 impl ISC0_R {
2816 ///Get enumerated values variant
2817 #[inline(always)]
2818 pub const fn variant(&self) -> ISC0_A {
2819 match self.bits {
2820 0 => ISC0_A::VAL_0X00,
2821 1 => ISC0_A::VAL_0X01,
2822 2 => ISC0_A::VAL_0X02,
2823 3 => ISC0_A::VAL_0X03,
2824 _ => unreachable!(),
2825 }
2826 }
2827 ///Low Level of INTX
2828 #[inline(always)]
2829 pub fn is_val_0x00(&self) -> bool {
2830 *self == ISC0_A::VAL_0X00
2831 }
2832 ///Any Logical Change of INTX
2833 #[inline(always)]
2834 pub fn is_val_0x01(&self) -> bool {
2835 *self == ISC0_A::VAL_0X01
2836 }
2837 ///Falling Edge of INTX
2838 #[inline(always)]
2839 pub fn is_val_0x02(&self) -> bool {
2840 *self == ISC0_A::VAL_0X02
2841 }
2842 ///Rising Edge of INTX
2843 #[inline(always)]
2844 pub fn is_val_0x03(&self) -> bool {
2845 *self == ISC0_A::VAL_0X03
2846 }
2847 }
2848 ///Field `ISC0` writer - External Interrupt Sense Control 0 Bits
2849 pub type ISC0_W<'a, REG> = crate::FieldWriter<'a, REG, 2, ISC0_A, crate::Safe>;
2850 impl<'a, REG> ISC0_W<'a, REG>
2851 where
2852 REG: crate::Writable + crate::RegisterSpec,
2853 REG::Ux: From<u8>,
2854 {
2855 ///Low Level of INTX
2856 #[inline(always)]
2857 pub fn val_0x00(self) -> &'a mut crate::W<REG> {
2858 self.variant(ISC0_A::VAL_0X00)
2859 }
2860 ///Any Logical Change of INTX
2861 #[inline(always)]
2862 pub fn val_0x01(self) -> &'a mut crate::W<REG> {
2863 self.variant(ISC0_A::VAL_0X01)
2864 }
2865 ///Falling Edge of INTX
2866 #[inline(always)]
2867 pub fn val_0x02(self) -> &'a mut crate::W<REG> {
2868 self.variant(ISC0_A::VAL_0X02)
2869 }
2870 ///Rising Edge of INTX
2871 #[inline(always)]
2872 pub fn val_0x03(self) -> &'a mut crate::W<REG> {
2873 self.variant(ISC0_A::VAL_0X03)
2874 }
2875 }
2876 /**External Interrupt Sense Control 1 Bits
2877
2878Value on reset: 0*/
2879 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
2880 #[repr(u8)]
2881 pub enum ISC1_A {
2882 ///0: Low Level of INTX
2883 VAL_0X00 = 0,
2884 ///1: Any Logical Change of INTX
2885 VAL_0X01 = 1,
2886 ///2: Falling Edge of INTX
2887 VAL_0X02 = 2,
2888 ///3: Rising Edge of INTX
2889 VAL_0X03 = 3,
2890 }
2891 impl From<ISC1_A> for u8 {
2892 #[inline(always)]
2893 fn from(variant: ISC1_A) -> Self {
2894 variant as _
2895 }
2896 }
2897 impl crate::FieldSpec for ISC1_A {
2898 type Ux = u8;
2899 }
2900 impl crate::IsEnum for ISC1_A {}
2901 ///Field `ISC1` reader - External Interrupt Sense Control 1 Bits
2902 pub type ISC1_R = crate::FieldReader<ISC1_A>;
2903 impl ISC1_R {
2904 ///Get enumerated values variant
2905 #[inline(always)]
2906 pub const fn variant(&self) -> ISC1_A {
2907 match self.bits {
2908 0 => ISC1_A::VAL_0X00,
2909 1 => ISC1_A::VAL_0X01,
2910 2 => ISC1_A::VAL_0X02,
2911 3 => ISC1_A::VAL_0X03,
2912 _ => unreachable!(),
2913 }
2914 }
2915 ///Low Level of INTX
2916 #[inline(always)]
2917 pub fn is_val_0x00(&self) -> bool {
2918 *self == ISC1_A::VAL_0X00
2919 }
2920 ///Any Logical Change of INTX
2921 #[inline(always)]
2922 pub fn is_val_0x01(&self) -> bool {
2923 *self == ISC1_A::VAL_0X01
2924 }
2925 ///Falling Edge of INTX
2926 #[inline(always)]
2927 pub fn is_val_0x02(&self) -> bool {
2928 *self == ISC1_A::VAL_0X02
2929 }
2930 ///Rising Edge of INTX
2931 #[inline(always)]
2932 pub fn is_val_0x03(&self) -> bool {
2933 *self == ISC1_A::VAL_0X03
2934 }
2935 }
2936 ///Field `ISC1` writer - External Interrupt Sense Control 1 Bits
2937 pub type ISC1_W<'a, REG> = crate::FieldWriter<'a, REG, 2, ISC1_A, crate::Safe>;
2938 impl<'a, REG> ISC1_W<'a, REG>
2939 where
2940 REG: crate::Writable + crate::RegisterSpec,
2941 REG::Ux: From<u8>,
2942 {
2943 ///Low Level of INTX
2944 #[inline(always)]
2945 pub fn val_0x00(self) -> &'a mut crate::W<REG> {
2946 self.variant(ISC1_A::VAL_0X00)
2947 }
2948 ///Any Logical Change of INTX
2949 #[inline(always)]
2950 pub fn val_0x01(self) -> &'a mut crate::W<REG> {
2951 self.variant(ISC1_A::VAL_0X01)
2952 }
2953 ///Falling Edge of INTX
2954 #[inline(always)]
2955 pub fn val_0x02(self) -> &'a mut crate::W<REG> {
2956 self.variant(ISC1_A::VAL_0X02)
2957 }
2958 ///Rising Edge of INTX
2959 #[inline(always)]
2960 pub fn val_0x03(self) -> &'a mut crate::W<REG> {
2961 self.variant(ISC1_A::VAL_0X03)
2962 }
2963 }
2964 impl R {
2965 ///Bits 0:1 - External Interrupt Sense Control 0 Bits
2966 #[inline(always)]
2967 pub fn isc0(&self) -> ISC0_R {
2968 ISC0_R::new(self.bits & 3)
2969 }
2970 ///Bits 2:3 - External Interrupt Sense Control 1 Bits
2971 #[inline(always)]
2972 pub fn isc1(&self) -> ISC1_R {
2973 ISC1_R::new((self.bits >> 2) & 3)
2974 }
2975 }
2976 impl W {
2977 ///Bits 0:1 - External Interrupt Sense Control 0 Bits
2978 #[inline(always)]
2979 pub fn isc0(&mut self) -> ISC0_W<'_, EICRA_SPEC> {
2980 ISC0_W::new(self, 0)
2981 }
2982 ///Bits 2:3 - External Interrupt Sense Control 1 Bits
2983 #[inline(always)]
2984 pub fn isc1(&mut self) -> ISC1_W<'_, EICRA_SPEC> {
2985 ISC1_W::new(self, 2)
2986 }
2987 }
2988 /**External Interrupt Control Register
2989
2990You can [`read`](crate::Reg::read) this register and get [`eicra::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eicra::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
2991 pub struct EICRA_SPEC;
2992 impl crate::RegisterSpec for EICRA_SPEC {
2993 type Ux = u8;
2994 }
2995 ///`read()` method returns [`eicra::R`](R) reader structure
2996 impl crate::Readable for EICRA_SPEC {}
2997 ///`write(|w| ..)` method takes [`eicra::W`](W) writer structure
2998 impl crate::Writable for EICRA_SPEC {
2999 type Safety = crate::Unsafe;
3000 }
3001 ///`reset()` method sets EICRA to value 0
3002 impl crate::Resettable for EICRA_SPEC {}
3003 }
3004 /**EIFR (rw) register accessor: External Interrupt Flag Register
3005
3006You can [`read`](crate::Reg::read) this register and get [`eifr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eifr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
3007
3008For information about available fields see [`mod@eifr`] module*/
3009 pub type EIFR = crate::Reg<eifr::EIFR_SPEC>;
3010 ///External Interrupt Flag Register
3011 pub mod eifr {
3012 ///Register `EIFR` reader
3013 pub type R = crate::R<EIFR_SPEC>;
3014 ///Register `EIFR` writer
3015 pub type W = crate::W<EIFR_SPEC>;
3016 ///Field `INTF` reader - External Interrupt Flags
3017 pub type INTF_R = crate::FieldReader;
3018 ///Field `INTF` writer - External Interrupt Flags
3019 pub type INTF_W<'a, REG> = crate::FieldWriter<'a, REG, 2, u8, crate::Safe>;
3020 impl R {
3021 ///Bits 0:1 - External Interrupt Flags
3022 #[inline(always)]
3023 pub fn intf(&self) -> INTF_R {
3024 INTF_R::new(self.bits & 3)
3025 }
3026 }
3027 impl W {
3028 ///Bits 0:1 - External Interrupt Flags
3029 #[inline(always)]
3030 pub fn intf(&mut self) -> INTF_W<'_, EIFR_SPEC> {
3031 INTF_W::new(self, 0)
3032 }
3033 }
3034 /**External Interrupt Flag Register
3035
3036You can [`read`](crate::Reg::read) this register and get [`eifr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eifr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
3037 pub struct EIFR_SPEC;
3038 impl crate::RegisterSpec for EIFR_SPEC {
3039 type Ux = u8;
3040 }
3041 ///`read()` method returns [`eifr::R`](R) reader structure
3042 impl crate::Readable for EIFR_SPEC {}
3043 ///`write(|w| ..)` method takes [`eifr::W`](W) writer structure
3044 impl crate::Writable for EIFR_SPEC {
3045 type Safety = crate::Unsafe;
3046 }
3047 ///`reset()` method sets EIFR to value 0
3048 impl crate::Resettable for EIFR_SPEC {}
3049 }
3050 /**EIMSK (rw) register accessor: External Interrupt Mask Register
3051
3052You can [`read`](crate::Reg::read) this register and get [`eimsk::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eimsk::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
3053
3054For information about available fields see [`mod@eimsk`] module*/
3055 pub type EIMSK = crate::Reg<eimsk::EIMSK_SPEC>;
3056 ///External Interrupt Mask Register
3057 pub mod eimsk {
3058 ///Register `EIMSK` reader
3059 pub type R = crate::R<EIMSK_SPEC>;
3060 ///Register `EIMSK` writer
3061 pub type W = crate::W<EIMSK_SPEC>;
3062 ///Field `INT0` reader - External Interrupt Request Enable
3063 pub type INT0_R = crate::BitReader;
3064 ///Field `INT0` writer - External Interrupt Request Enable
3065 pub type INT0_W<'a, REG> = crate::BitWriter<'a, REG>;
3066 ///Field `INT1` reader - External Interrupt Request Enable
3067 pub type INT1_R = crate::BitReader;
3068 ///Field `INT1` writer - External Interrupt Request Enable
3069 pub type INT1_W<'a, REG> = crate::BitWriter<'a, REG>;
3070 impl R {
3071 ///Bit 0 - External Interrupt Request Enable
3072 #[inline(always)]
3073 pub fn int0(&self) -> INT0_R {
3074 INT0_R::new((self.bits & 1) != 0)
3075 }
3076 ///Bit 1 - External Interrupt Request Enable
3077 #[inline(always)]
3078 pub fn int1(&self) -> INT1_R {
3079 INT1_R::new(((self.bits >> 1) & 1) != 0)
3080 }
3081 }
3082 impl W {
3083 ///Bit 0 - External Interrupt Request Enable
3084 #[inline(always)]
3085 pub fn int0(&mut self) -> INT0_W<'_, EIMSK_SPEC> {
3086 INT0_W::new(self, 0)
3087 }
3088 ///Bit 1 - External Interrupt Request Enable
3089 #[inline(always)]
3090 pub fn int1(&mut self) -> INT1_W<'_, EIMSK_SPEC> {
3091 INT1_W::new(self, 1)
3092 }
3093 }
3094 /**External Interrupt Mask Register
3095
3096You can [`read`](crate::Reg::read) this register and get [`eimsk::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eimsk::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
3097 pub struct EIMSK_SPEC;
3098 impl crate::RegisterSpec for EIMSK_SPEC {
3099 type Ux = u8;
3100 }
3101 ///`read()` method returns [`eimsk::R`](R) reader structure
3102 impl crate::Readable for EIMSK_SPEC {}
3103 ///`write(|w| ..)` method takes [`eimsk::W`](W) writer structure
3104 impl crate::Writable for EIMSK_SPEC {
3105 type Safety = crate::Unsafe;
3106 }
3107 ///`reset()` method sets EIMSK to value 0
3108 impl crate::Resettable for EIMSK_SPEC {}
3109 }
3110 /**PCICR (rw) register accessor: Pin Change Interrupt Control Register
3111
3112You can [`read`](crate::Reg::read) this register and get [`pcicr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcicr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
3113
3114For information about available fields see [`mod@pcicr`] module*/
3115 pub type PCICR = crate::Reg<pcicr::PCICR_SPEC>;
3116 ///Pin Change Interrupt Control Register
3117 pub mod pcicr {
3118 ///Register `PCICR` reader
3119 pub type R = crate::R<PCICR_SPEC>;
3120 ///Register `PCICR` writer
3121 pub type W = crate::W<PCICR_SPEC>;
3122 ///Field `PCIE` reader - Pin Change Interrupt Enables
3123 pub type PCIE_R = crate::FieldReader;
3124 ///Field `PCIE` writer - Pin Change Interrupt Enables
3125 pub type PCIE_W<'a, REG> = crate::FieldWriter<'a, REG, 3, u8, crate::Safe>;
3126 impl R {
3127 ///Bits 0:2 - Pin Change Interrupt Enables
3128 #[inline(always)]
3129 pub fn pcie(&self) -> PCIE_R {
3130 PCIE_R::new(self.bits & 7)
3131 }
3132 }
3133 impl W {
3134 ///Bits 0:2 - Pin Change Interrupt Enables
3135 #[inline(always)]
3136 pub fn pcie(&mut self) -> PCIE_W<'_, PCICR_SPEC> {
3137 PCIE_W::new(self, 0)
3138 }
3139 }
3140 /**Pin Change Interrupt Control Register
3141
3142You can [`read`](crate::Reg::read) this register and get [`pcicr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcicr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
3143 pub struct PCICR_SPEC;
3144 impl crate::RegisterSpec for PCICR_SPEC {
3145 type Ux = u8;
3146 }
3147 ///`read()` method returns [`pcicr::R`](R) reader structure
3148 impl crate::Readable for PCICR_SPEC {}
3149 ///`write(|w| ..)` method takes [`pcicr::W`](W) writer structure
3150 impl crate::Writable for PCICR_SPEC {
3151 type Safety = crate::Unsafe;
3152 }
3153 ///`reset()` method sets PCICR to value 0
3154 impl crate::Resettable for PCICR_SPEC {}
3155 }
3156 /**PCIFR (rw) register accessor: Pin Change Interrupt Flag Register
3157
3158You can [`read`](crate::Reg::read) this register and get [`pcifr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcifr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
3159
3160For information about available fields see [`mod@pcifr`] module*/
3161 pub type PCIFR = crate::Reg<pcifr::PCIFR_SPEC>;
3162 ///Pin Change Interrupt Flag Register
3163 pub mod pcifr {
3164 ///Register `PCIFR` reader
3165 pub type R = crate::R<PCIFR_SPEC>;
3166 ///Register `PCIFR` writer
3167 pub type W = crate::W<PCIFR_SPEC>;
3168 ///Field `PCIF` reader - Pin Change Interrupt Flags
3169 pub type PCIF_R = crate::FieldReader;
3170 ///Field `PCIF` writer - Pin Change Interrupt Flags
3171 pub type PCIF_W<'a, REG> = crate::FieldWriter<'a, REG, 3, u8, crate::Safe>;
3172 impl R {
3173 ///Bits 0:2 - Pin Change Interrupt Flags
3174 #[inline(always)]
3175 pub fn pcif(&self) -> PCIF_R {
3176 PCIF_R::new(self.bits & 7)
3177 }
3178 }
3179 impl W {
3180 ///Bits 0:2 - Pin Change Interrupt Flags
3181 #[inline(always)]
3182 pub fn pcif(&mut self) -> PCIF_W<'_, PCIFR_SPEC> {
3183 PCIF_W::new(self, 0)
3184 }
3185 }
3186 /**Pin Change Interrupt Flag Register
3187
3188You can [`read`](crate::Reg::read) this register and get [`pcifr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcifr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
3189 pub struct PCIFR_SPEC;
3190 impl crate::RegisterSpec for PCIFR_SPEC {
3191 type Ux = u8;
3192 }
3193 ///`read()` method returns [`pcifr::R`](R) reader structure
3194 impl crate::Readable for PCIFR_SPEC {}
3195 ///`write(|w| ..)` method takes [`pcifr::W`](W) writer structure
3196 impl crate::Writable for PCIFR_SPEC {
3197 type Safety = crate::Unsafe;
3198 }
3199 ///`reset()` method sets PCIFR to value 0
3200 impl crate::Resettable for PCIFR_SPEC {}
3201 }
3202 /**PCMSK0 (rw) register accessor: Pin Change Mask Register 0
3203
3204You can [`read`](crate::Reg::read) this register and get [`pcmsk0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcmsk0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
3205
3206For information about available fields see [`mod@pcmsk0`] module*/
3207 pub type PCMSK0 = crate::Reg<pcmsk0::PCMSK0_SPEC>;
3208 ///Pin Change Mask Register 0
3209 pub mod pcmsk0 {
3210 ///Register `PCMSK0` reader
3211 pub type R = crate::R<PCMSK0_SPEC>;
3212 ///Register `PCMSK0` writer
3213 pub type W = crate::W<PCMSK0_SPEC>;
3214 ///Field `PCINT` reader - Pin Change Enable Masks
3215 pub type PCINT_R = crate::FieldReader;
3216 ///Field `PCINT` writer - Pin Change Enable Masks
3217 pub type PCINT_W<'a, REG> = crate::FieldWriter<'a, REG, 8, u8, crate::Safe>;
3218 impl R {
3219 ///Bits 0:7 - Pin Change Enable Masks
3220 #[inline(always)]
3221 pub fn pcint(&self) -> PCINT_R {
3222 PCINT_R::new(self.bits)
3223 }
3224 }
3225 impl W {
3226 ///Bits 0:7 - Pin Change Enable Masks
3227 #[inline(always)]
3228 pub fn pcint(&mut self) -> PCINT_W<'_, PCMSK0_SPEC> {
3229 PCINT_W::new(self, 0)
3230 }
3231 }
3232 /**Pin Change Mask Register 0
3233
3234You can [`read`](crate::Reg::read) this register and get [`pcmsk0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcmsk0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
3235 pub struct PCMSK0_SPEC;
3236 impl crate::RegisterSpec for PCMSK0_SPEC {
3237 type Ux = u8;
3238 }
3239 ///`read()` method returns [`pcmsk0::R`](R) reader structure
3240 impl crate::Readable for PCMSK0_SPEC {}
3241 ///`write(|w| ..)` method takes [`pcmsk0::W`](W) writer structure
3242 impl crate::Writable for PCMSK0_SPEC {
3243 type Safety = crate::Safe;
3244 }
3245 ///`reset()` method sets PCMSK0 to value 0
3246 impl crate::Resettable for PCMSK0_SPEC {}
3247 }
3248 /**PCMSK1 (rw) register accessor: Pin Change Mask Register 1
3249
3250You can [`read`](crate::Reg::read) this register and get [`pcmsk1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcmsk1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
3251
3252For information about available fields see [`mod@pcmsk1`] module*/
3253 pub type PCMSK1 = crate::Reg<pcmsk1::PCMSK1_SPEC>;
3254 ///Pin Change Mask Register 1
3255 pub mod pcmsk1 {
3256 ///Register `PCMSK1` reader
3257 pub type R = crate::R<PCMSK1_SPEC>;
3258 ///Register `PCMSK1` writer
3259 pub type W = crate::W<PCMSK1_SPEC>;
3260 ///Field `PCINT` reader - Pin Change Enable Masks
3261 pub type PCINT_R = crate::FieldReader;
3262 ///Field `PCINT` writer - Pin Change Enable Masks
3263 pub type PCINT_W<'a, REG> = crate::FieldWriter<'a, REG, 7, u8, crate::Safe>;
3264 impl R {
3265 ///Bits 0:6 - Pin Change Enable Masks
3266 #[inline(always)]
3267 pub fn pcint(&self) -> PCINT_R {
3268 PCINT_R::new(self.bits & 0x7f)
3269 }
3270 }
3271 impl W {
3272 ///Bits 0:6 - Pin Change Enable Masks
3273 #[inline(always)]
3274 pub fn pcint(&mut self) -> PCINT_W<'_, PCMSK1_SPEC> {
3275 PCINT_W::new(self, 0)
3276 }
3277 }
3278 /**Pin Change Mask Register 1
3279
3280You can [`read`](crate::Reg::read) this register and get [`pcmsk1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcmsk1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
3281 pub struct PCMSK1_SPEC;
3282 impl crate::RegisterSpec for PCMSK1_SPEC {
3283 type Ux = u8;
3284 }
3285 ///`read()` method returns [`pcmsk1::R`](R) reader structure
3286 impl crate::Readable for PCMSK1_SPEC {}
3287 ///`write(|w| ..)` method takes [`pcmsk1::W`](W) writer structure
3288 impl crate::Writable for PCMSK1_SPEC {
3289 type Safety = crate::Unsafe;
3290 }
3291 ///`reset()` method sets PCMSK1 to value 0
3292 impl crate::Resettable for PCMSK1_SPEC {}
3293 }
3294 /**PCMSK2 (rw) register accessor: Pin Change Mask Register 2
3295
3296You can [`read`](crate::Reg::read) this register and get [`pcmsk2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcmsk2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
3297
3298For information about available fields see [`mod@pcmsk2`] module*/
3299 pub type PCMSK2 = crate::Reg<pcmsk2::PCMSK2_SPEC>;
3300 ///Pin Change Mask Register 2
3301 pub mod pcmsk2 {
3302 ///Register `PCMSK2` reader
3303 pub type R = crate::R<PCMSK2_SPEC>;
3304 ///Register `PCMSK2` writer
3305 pub type W = crate::W<PCMSK2_SPEC>;
3306 ///Field `PCINT` reader - Pin Change Enable Masks
3307 pub type PCINT_R = crate::FieldReader;
3308 ///Field `PCINT` writer - Pin Change Enable Masks
3309 pub type PCINT_W<'a, REG> = crate::FieldWriter<'a, REG, 8, u8, crate::Safe>;
3310 impl R {
3311 ///Bits 0:7 - Pin Change Enable Masks
3312 #[inline(always)]
3313 pub fn pcint(&self) -> PCINT_R {
3314 PCINT_R::new(self.bits)
3315 }
3316 }
3317 impl W {
3318 ///Bits 0:7 - Pin Change Enable Masks
3319 #[inline(always)]
3320 pub fn pcint(&mut self) -> PCINT_W<'_, PCMSK2_SPEC> {
3321 PCINT_W::new(self, 0)
3322 }
3323 }
3324 /**Pin Change Mask Register 2
3325
3326You can [`read`](crate::Reg::read) this register and get [`pcmsk2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcmsk2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
3327 pub struct PCMSK2_SPEC;
3328 impl crate::RegisterSpec for PCMSK2_SPEC {
3329 type Ux = u8;
3330 }
3331 ///`read()` method returns [`pcmsk2::R`](R) reader structure
3332 impl crate::Readable for PCMSK2_SPEC {}
3333 ///`write(|w| ..)` method takes [`pcmsk2::W`](W) writer structure
3334 impl crate::Writable for PCMSK2_SPEC {
3335 type Safety = crate::Safe;
3336 }
3337 ///`reset()` method sets PCMSK2 to value 0
3338 impl crate::Resettable for PCMSK2_SPEC {}
3339 }
3340}
3341///Fuses
3342pub type FUSE = crate::Periph<fuse::RegisterBlock, 0>;
3343impl core::fmt::Debug for FUSE {
3344 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
3345 f.debug_struct("FUSE").finish()
3346 }
3347}
3348///Fuses
3349pub mod fuse {
3350 #[repr(C)]
3351 ///Register block
3352 pub struct RegisterBlock {
3353 low: LOW,
3354 high: HIGH,
3355 extended: EXTENDED,
3356 }
3357 impl RegisterBlock {
3358 ///0x00 - No Description.
3359 #[inline(always)]
3360 pub const fn low(&self) -> &LOW {
3361 &self.low
3362 }
3363 ///0x01 - No Description.
3364 #[inline(always)]
3365 pub const fn high(&self) -> &HIGH {
3366 &self.high
3367 }
3368 ///0x02 - No Description.
3369 #[inline(always)]
3370 pub const fn extended(&self) -> &EXTENDED {
3371 &self.extended
3372 }
3373 }
3374 /**EXTENDED (rw) register accessor: No Description.
3375
3376You can [`read`](crate::Reg::read) this register and get [`extended::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`extended::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
3377
3378For information about available fields see [`mod@extended`] module*/
3379 pub type EXTENDED = crate::Reg<extended::EXTENDED_SPEC>;
3380 ///No Description.
3381 pub mod extended {
3382 ///Register `EXTENDED` reader
3383 pub type R = crate::R<EXTENDED_SPEC>;
3384 ///Register `EXTENDED` writer
3385 pub type W = crate::W<EXTENDED_SPEC>;
3386 /**Brown-out Detector trigger level
3387
3388Value on reset: 0*/
3389 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
3390 #[repr(u8)]
3391 pub enum BODLEVEL_A {
3392 ///4: Brown-out detection at VCC=4.3 V
3393 _4V3 = 4,
3394 ///5: Brown-out detection at VCC=2.7 V
3395 _2V7 = 5,
3396 ///6: Brown-out detection at VCC=1.8 V
3397 _1V8 = 6,
3398 ///7: Brown-out detection disabled
3399 DISABLED = 7,
3400 }
3401 impl From<BODLEVEL_A> for u8 {
3402 #[inline(always)]
3403 fn from(variant: BODLEVEL_A) -> Self {
3404 variant as _
3405 }
3406 }
3407 impl crate::FieldSpec for BODLEVEL_A {
3408 type Ux = u8;
3409 }
3410 impl crate::IsEnum for BODLEVEL_A {}
3411 ///Field `BODLEVEL` reader - Brown-out Detector trigger level
3412 pub type BODLEVEL_R = crate::FieldReader<BODLEVEL_A>;
3413 impl BODLEVEL_R {
3414 ///Get enumerated values variant
3415 #[inline(always)]
3416 pub const fn variant(&self) -> Option<BODLEVEL_A> {
3417 match self.bits {
3418 4 => Some(BODLEVEL_A::_4V3),
3419 5 => Some(BODLEVEL_A::_2V7),
3420 6 => Some(BODLEVEL_A::_1V8),
3421 7 => Some(BODLEVEL_A::DISABLED),
3422 _ => None,
3423 }
3424 }
3425 ///Brown-out detection at VCC=4.3 V
3426 #[inline(always)]
3427 pub fn is_4v3(&self) -> bool {
3428 *self == BODLEVEL_A::_4V3
3429 }
3430 ///Brown-out detection at VCC=2.7 V
3431 #[inline(always)]
3432 pub fn is_2v7(&self) -> bool {
3433 *self == BODLEVEL_A::_2V7
3434 }
3435 ///Brown-out detection at VCC=1.8 V
3436 #[inline(always)]
3437 pub fn is_1v8(&self) -> bool {
3438 *self == BODLEVEL_A::_1V8
3439 }
3440 ///Brown-out detection disabled
3441 #[inline(always)]
3442 pub fn is_disabled(&self) -> bool {
3443 *self == BODLEVEL_A::DISABLED
3444 }
3445 }
3446 ///Field `BODLEVEL` writer - Brown-out Detector trigger level
3447 pub type BODLEVEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3, BODLEVEL_A>;
3448 impl<'a, REG> BODLEVEL_W<'a, REG>
3449 where
3450 REG: crate::Writable + crate::RegisterSpec,
3451 REG::Ux: From<u8>,
3452 {
3453 ///Brown-out detection at VCC=4.3 V
3454 #[inline(always)]
3455 pub fn _4v3(self) -> &'a mut crate::W<REG> {
3456 self.variant(BODLEVEL_A::_4V3)
3457 }
3458 ///Brown-out detection at VCC=2.7 V
3459 #[inline(always)]
3460 pub fn _2v7(self) -> &'a mut crate::W<REG> {
3461 self.variant(BODLEVEL_A::_2V7)
3462 }
3463 ///Brown-out detection at VCC=1.8 V
3464 #[inline(always)]
3465 pub fn _1v8(self) -> &'a mut crate::W<REG> {
3466 self.variant(BODLEVEL_A::_1V8)
3467 }
3468 ///Brown-out detection disabled
3469 #[inline(always)]
3470 pub fn disabled(self) -> &'a mut crate::W<REG> {
3471 self.variant(BODLEVEL_A::DISABLED)
3472 }
3473 }
3474 impl R {
3475 ///Bits 0:2 - Brown-out Detector trigger level
3476 #[inline(always)]
3477 pub fn bodlevel(&self) -> BODLEVEL_R {
3478 BODLEVEL_R::new(self.bits & 7)
3479 }
3480 }
3481 impl W {
3482 ///Bits 0:2 - Brown-out Detector trigger level
3483 #[inline(always)]
3484 pub fn bodlevel(&mut self) -> BODLEVEL_W<'_, EXTENDED_SPEC> {
3485 BODLEVEL_W::new(self, 0)
3486 }
3487 }
3488 /**No Description.
3489
3490You can [`read`](crate::Reg::read) this register and get [`extended::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`extended::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
3491 pub struct EXTENDED_SPEC;
3492 impl crate::RegisterSpec for EXTENDED_SPEC {
3493 type Ux = u8;
3494 }
3495 ///`read()` method returns [`extended::R`](R) reader structure
3496 impl crate::Readable for EXTENDED_SPEC {}
3497 ///`write(|w| ..)` method takes [`extended::W`](W) writer structure
3498 impl crate::Writable for EXTENDED_SPEC {
3499 type Safety = crate::Unsafe;
3500 }
3501 ///`reset()` method sets EXTENDED to value 0
3502 impl crate::Resettable for EXTENDED_SPEC {}
3503 }
3504 /**HIGH (rw) register accessor: No Description.
3505
3506You can [`read`](crate::Reg::read) this register and get [`high::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`high::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
3507
3508For information about available fields see [`mod@high`] module*/
3509 pub type HIGH = crate::Reg<high::HIGH_SPEC>;
3510 ///No Description.
3511 pub mod high {
3512 ///Register `HIGH` reader
3513 pub type R = crate::R<HIGH_SPEC>;
3514 ///Register `HIGH` writer
3515 pub type W = crate::W<HIGH_SPEC>;
3516 ///Field `BOOTRST` reader - Boot Reset vector Enabled
3517 pub type BOOTRST_R = crate::BitReader;
3518 ///Field `BOOTRST` writer - Boot Reset vector Enabled
3519 pub type BOOTRST_W<'a, REG> = crate::BitWriter<'a, REG>;
3520 /**Select boot size
3521
3522Value on reset: 0*/
3523 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
3524 #[repr(u8)]
3525 pub enum BOOTSZ_A {
3526 ///0: Boot Flash size=2048 words start address=$3800
3527 _2048W_3800 = 0,
3528 ///1: Boot Flash size=1024 words start address=$3C00
3529 _1024W_3C00 = 1,
3530 ///2: Boot Flash size=512 words start address=$3E00
3531 _512W_3E00 = 2,
3532 ///3: Boot Flash size=256 words start address=$3F00
3533 _256W_3F00 = 3,
3534 }
3535 impl From<BOOTSZ_A> for u8 {
3536 #[inline(always)]
3537 fn from(variant: BOOTSZ_A) -> Self {
3538 variant as _
3539 }
3540 }
3541 impl crate::FieldSpec for BOOTSZ_A {
3542 type Ux = u8;
3543 }
3544 impl crate::IsEnum for BOOTSZ_A {}
3545 ///Field `BOOTSZ` reader - Select boot size
3546 pub type BOOTSZ_R = crate::FieldReader<BOOTSZ_A>;
3547 impl BOOTSZ_R {
3548 ///Get enumerated values variant
3549 #[inline(always)]
3550 pub const fn variant(&self) -> BOOTSZ_A {
3551 match self.bits {
3552 0 => BOOTSZ_A::_2048W_3800,
3553 1 => BOOTSZ_A::_1024W_3C00,
3554 2 => BOOTSZ_A::_512W_3E00,
3555 3 => BOOTSZ_A::_256W_3F00,
3556 _ => unreachable!(),
3557 }
3558 }
3559 ///Boot Flash size=2048 words start address=$3800
3560 #[inline(always)]
3561 pub fn is_2048w_3800(&self) -> bool {
3562 *self == BOOTSZ_A::_2048W_3800
3563 }
3564 ///Boot Flash size=1024 words start address=$3C00
3565 #[inline(always)]
3566 pub fn is_1024w_3c00(&self) -> bool {
3567 *self == BOOTSZ_A::_1024W_3C00
3568 }
3569 ///Boot Flash size=512 words start address=$3E00
3570 #[inline(always)]
3571 pub fn is_512w_3e00(&self) -> bool {
3572 *self == BOOTSZ_A::_512W_3E00
3573 }
3574 ///Boot Flash size=256 words start address=$3F00
3575 #[inline(always)]
3576 pub fn is_256w_3f00(&self) -> bool {
3577 *self == BOOTSZ_A::_256W_3F00
3578 }
3579 }
3580 ///Field `BOOTSZ` writer - Select boot size
3581 pub type BOOTSZ_W<'a, REG> = crate::FieldWriter<
3582 'a,
3583 REG,
3584 2,
3585 BOOTSZ_A,
3586 crate::Safe,
3587 >;
3588 impl<'a, REG> BOOTSZ_W<'a, REG>
3589 where
3590 REG: crate::Writable + crate::RegisterSpec,
3591 REG::Ux: From<u8>,
3592 {
3593 ///Boot Flash size=2048 words start address=$3800
3594 #[inline(always)]
3595 pub fn _2048w_3800(self) -> &'a mut crate::W<REG> {
3596 self.variant(BOOTSZ_A::_2048W_3800)
3597 }
3598 ///Boot Flash size=1024 words start address=$3C00
3599 #[inline(always)]
3600 pub fn _1024w_3c00(self) -> &'a mut crate::W<REG> {
3601 self.variant(BOOTSZ_A::_1024W_3C00)
3602 }
3603 ///Boot Flash size=512 words start address=$3E00
3604 #[inline(always)]
3605 pub fn _512w_3e00(self) -> &'a mut crate::W<REG> {
3606 self.variant(BOOTSZ_A::_512W_3E00)
3607 }
3608 ///Boot Flash size=256 words start address=$3F00
3609 #[inline(always)]
3610 pub fn _256w_3f00(self) -> &'a mut crate::W<REG> {
3611 self.variant(BOOTSZ_A::_256W_3F00)
3612 }
3613 }
3614 ///Field `EESAVE` reader - Preserve EEPROM through the Chip Erase cycle
3615 pub type EESAVE_R = crate::BitReader;
3616 ///Field `EESAVE` writer - Preserve EEPROM through the Chip Erase cycle
3617 pub type EESAVE_W<'a, REG> = crate::BitWriter<'a, REG>;
3618 ///Field `WDTON` reader - Watch-dog Timer always on
3619 pub type WDTON_R = crate::BitReader;
3620 ///Field `WDTON` writer - Watch-dog Timer always on
3621 pub type WDTON_W<'a, REG> = crate::BitWriter<'a, REG>;
3622 ///Field `SPIEN` reader - Serial program downloading (SPI) enabled
3623 pub type SPIEN_R = crate::BitReader;
3624 ///Field `SPIEN` writer - Serial program downloading (SPI) enabled
3625 pub type SPIEN_W<'a, REG> = crate::BitWriter<'a, REG>;
3626 ///Field `DWEN` reader - Debug Wire enable
3627 pub type DWEN_R = crate::BitReader;
3628 ///Field `DWEN` writer - Debug Wire enable
3629 pub type DWEN_W<'a, REG> = crate::BitWriter<'a, REG>;
3630 ///Field `RSTDISBL` reader - Reset Disabled (Enable PC6 as i/o pin)
3631 pub type RSTDISBL_R = crate::BitReader;
3632 ///Field `RSTDISBL` writer - Reset Disabled (Enable PC6 as i/o pin)
3633 pub type RSTDISBL_W<'a, REG> = crate::BitWriter<'a, REG>;
3634 impl R {
3635 ///Bit 0 - Boot Reset vector Enabled
3636 #[inline(always)]
3637 pub fn bootrst(&self) -> BOOTRST_R {
3638 BOOTRST_R::new((self.bits & 1) != 0)
3639 }
3640 ///Bits 1:2 - Select boot size
3641 #[inline(always)]
3642 pub fn bootsz(&self) -> BOOTSZ_R {
3643 BOOTSZ_R::new((self.bits >> 1) & 3)
3644 }
3645 ///Bit 3 - Preserve EEPROM through the Chip Erase cycle
3646 #[inline(always)]
3647 pub fn eesave(&self) -> EESAVE_R {
3648 EESAVE_R::new(((self.bits >> 3) & 1) != 0)
3649 }
3650 ///Bit 4 - Watch-dog Timer always on
3651 #[inline(always)]
3652 pub fn wdton(&self) -> WDTON_R {
3653 WDTON_R::new(((self.bits >> 4) & 1) != 0)
3654 }
3655 ///Bit 5 - Serial program downloading (SPI) enabled
3656 #[inline(always)]
3657 pub fn spien(&self) -> SPIEN_R {
3658 SPIEN_R::new(((self.bits >> 5) & 1) != 0)
3659 }
3660 ///Bit 6 - Debug Wire enable
3661 #[inline(always)]
3662 pub fn dwen(&self) -> DWEN_R {
3663 DWEN_R::new(((self.bits >> 6) & 1) != 0)
3664 }
3665 ///Bit 7 - Reset Disabled (Enable PC6 as i/o pin)
3666 #[inline(always)]
3667 pub fn rstdisbl(&self) -> RSTDISBL_R {
3668 RSTDISBL_R::new(((self.bits >> 7) & 1) != 0)
3669 }
3670 }
3671 impl W {
3672 ///Bit 0 - Boot Reset vector Enabled
3673 #[inline(always)]
3674 pub fn bootrst(&mut self) -> BOOTRST_W<'_, HIGH_SPEC> {
3675 BOOTRST_W::new(self, 0)
3676 }
3677 ///Bits 1:2 - Select boot size
3678 #[inline(always)]
3679 pub fn bootsz(&mut self) -> BOOTSZ_W<'_, HIGH_SPEC> {
3680 BOOTSZ_W::new(self, 1)
3681 }
3682 ///Bit 3 - Preserve EEPROM through the Chip Erase cycle
3683 #[inline(always)]
3684 pub fn eesave(&mut self) -> EESAVE_W<'_, HIGH_SPEC> {
3685 EESAVE_W::new(self, 3)
3686 }
3687 ///Bit 4 - Watch-dog Timer always on
3688 #[inline(always)]
3689 pub fn wdton(&mut self) -> WDTON_W<'_, HIGH_SPEC> {
3690 WDTON_W::new(self, 4)
3691 }
3692 ///Bit 5 - Serial program downloading (SPI) enabled
3693 #[inline(always)]
3694 pub fn spien(&mut self) -> SPIEN_W<'_, HIGH_SPEC> {
3695 SPIEN_W::new(self, 5)
3696 }
3697 ///Bit 6 - Debug Wire enable
3698 #[inline(always)]
3699 pub fn dwen(&mut self) -> DWEN_W<'_, HIGH_SPEC> {
3700 DWEN_W::new(self, 6)
3701 }
3702 ///Bit 7 - Reset Disabled (Enable PC6 as i/o pin)
3703 #[inline(always)]
3704 pub fn rstdisbl(&mut self) -> RSTDISBL_W<'_, HIGH_SPEC> {
3705 RSTDISBL_W::new(self, 7)
3706 }
3707 }
3708 /**No Description.
3709
3710You can [`read`](crate::Reg::read) this register and get [`high::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`high::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
3711 pub struct HIGH_SPEC;
3712 impl crate::RegisterSpec for HIGH_SPEC {
3713 type Ux = u8;
3714 }
3715 ///`read()` method returns [`high::R`](R) reader structure
3716 impl crate::Readable for HIGH_SPEC {}
3717 ///`write(|w| ..)` method takes [`high::W`](W) writer structure
3718 impl crate::Writable for HIGH_SPEC {
3719 type Safety = crate::Unsafe;
3720 }
3721 ///`reset()` method sets HIGH to value 0
3722 impl crate::Resettable for HIGH_SPEC {}
3723 }
3724 /**LOW (rw) register accessor: No Description.
3725
3726You can [`read`](crate::Reg::read) this register and get [`low::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`low::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
3727
3728For information about available fields see [`mod@low`] module*/
3729 pub type LOW = crate::Reg<low::LOW_SPEC>;
3730 ///No Description.
3731 pub mod low {
3732 ///Register `LOW` reader
3733 pub type R = crate::R<LOW_SPEC>;
3734 ///Register `LOW` writer
3735 pub type W = crate::W<LOW_SPEC>;
3736 /**Select Clock Source
3737
3738Value on reset: 0*/
3739 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
3740 #[repr(u8)]
3741 pub enum SUT_CKSEL_A {
3742 ///0: Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms
3743 EXTCLK_6CK_14CK_0MS = 0,
3744 ///2: Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms
3745 INTRCOSC_8MHZ_6CK_14CK_0MS = 2,
3746 ///3: Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms
3747 INTRCOSC_128KHZ_6CK_14CK_0MS = 3,
3748 ///4: Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 0 ms
3749 EXTLOFXTAL_1KCK_14CK_0MS = 4,
3750 ///5: Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 0 ms
3751 EXTLOFXTAL_32KCK_14CK_0MS = 5,
3752 ///6: Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms
3753 EXTFSXTAL_258CK_14CK_4MS1 = 6,
3754 ///7: Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms
3755 EXTFSXTAL_1KCK_14CK_65MS = 7,
3756 ///8: Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms
3757 EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_4MS1 = 8,
3758 ///9: Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms
3759 EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_65MS = 9,
3760 ///10: Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms
3761 EXTXOSC_0MHZ9_3MHZ_258CK_14CK_4MS1 = 10,
3762 ///11: Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms
3763 EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_65MS = 11,
3764 ///12: Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms
3765 EXTXOSC_3MHZ_8MHZ_258CK_14CK_4MS1 = 12,
3766 ///13: Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms
3767 EXTXOSC_3MHZ_8MHZ_1KCK_14CK_65MS = 13,
3768 ///14: Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms
3769 EXTXOSC_8MHZ_XX_258CK_14CK_4MS1 = 14,
3770 ///15: Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms
3771 EXTXOSC_8MHZ_XX_1KCK_14CK_65MS = 15,
3772 ///16: Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms
3773 EXTCLK_6CK_14CK_4MS1 = 16,
3774 ///18: Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms
3775 INTRCOSC_8MHZ_6CK_14CK_4MS1 = 18,
3776 ///19: Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms
3777 INTRCOSC_128KHZ_6CK_14CK_4MS1 = 19,
3778 ///20: Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 4.1 ms
3779 EXTLOFXTAL_1KCK_14CK_4MS1 = 20,
3780 ///21: Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 4.1 ms
3781 EXTLOFXTAL_32KCK_14CK_4MS1 = 21,
3782 ///22: Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms
3783 EXTFSXTAL_258CK_14CK_65MS = 22,
3784 ///23: Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms
3785 EXTFSXTAL_16KCK_14CK_0MS = 23,
3786 ///24: Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms
3787 EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_65MS = 24,
3788 ///25: Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms
3789 EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_0MS = 25,
3790 ///26: Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms
3791 EXTXOSC_0MHZ9_3MHZ_258CK_14CK_65MS = 26,
3792 ///27: Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms
3793 EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_0MS = 27,
3794 ///28: Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms
3795 EXTXOSC_3MHZ_8MHZ_258CK_14CK_65MS = 28,
3796 ///29: Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms
3797 EXTXOSC_3MHZ_8MHZ_16KCK_14CK_0MS = 29,
3798 ///30: Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms
3799 EXTXOSC_8MHZ_XX_258CK_14CK_65MS = 30,
3800 ///31: Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms
3801 EXTXOSC_8MHZ_XX_16KCK_14CK_0MS = 31,
3802 ///32: Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms
3803 EXTCLK_6CK_14CK_65MS = 32,
3804 ///34: Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms
3805 INTRCOSC_8MHZ_6CK_14CK_65MS = 34,
3806 ///35: Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms
3807 INTRCOSC_128KHZ_6CK_14CK_65MS = 35,
3808 ///36: Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 65 ms
3809 EXTLOFXTAL_1KCK_14CK_65MS = 36,
3810 ///37: Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 65 ms
3811 EXTLOFXTAL_32KCK_14CK_65MS = 37,
3812 ///38: Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms
3813 EXTFSXTAL_1KCK_14CK_0MS = 38,
3814 ///39: Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms
3815 EXTFSXTAL_16KCK_14CK_4MS1 = 39,
3816 ///40: Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms
3817 EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_0MS = 40,
3818 ///41: Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms
3819 EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_4MS1 = 41,
3820 ///42: Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms
3821 EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_0MS = 42,
3822 ///43: Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms
3823 EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_4MS1 = 43,
3824 ///44: Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms
3825 EXTXOSC_3MHZ_8MHZ_1KCK_14CK_0MS = 44,
3826 ///45: Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms
3827 EXTXOSC_3MHZ_8MHZ_16KCK_14CK_4MS1 = 45,
3828 ///46: Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms
3829 EXTXOSC_8MHZ_XX_1KCK_14CK_0MS = 46,
3830 ///47: Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms
3831 EXTXOSC_8MHZ_XX_16KCK_14CK_4MS1 = 47,
3832 ///54: Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms
3833 EXTFSXTAL_1KCK_14CK_4MS1 = 54,
3834 ///55: Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms
3835 EXTFSXTAL_16KCK_14CK_65MS = 55,
3836 ///56: Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms
3837 EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_4MS1 = 56,
3838 ///57: Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms
3839 EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_65MS = 57,
3840 ///58: Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms
3841 EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_4MS1 = 58,
3842 ///59: Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms
3843 EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_65MS = 59,
3844 ///60: Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms
3845 EXTXOSC_3MHZ_8MHZ_1KCK_14CK_4MS1 = 60,
3846 ///61: Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms
3847 EXTXOSC_3MHZ_8MHZ_16KCK_14CK_65MS = 61,
3848 ///62: Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms
3849 EXTXOSC_8MHZ_XX_1KCK_14CK_4MS1 = 62,
3850 ///63: Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms
3851 EXTXOSC_8MHZ_XX_16KCK_14CK_65MS = 63,
3852 }
3853 impl From<SUT_CKSEL_A> for u8 {
3854 #[inline(always)]
3855 fn from(variant: SUT_CKSEL_A) -> Self {
3856 variant as _
3857 }
3858 }
3859 impl crate::FieldSpec for SUT_CKSEL_A {
3860 type Ux = u8;
3861 }
3862 impl crate::IsEnum for SUT_CKSEL_A {}
3863 ///Field `SUT_CKSEL` reader - Select Clock Source
3864 pub type SUT_CKSEL_R = crate::FieldReader<SUT_CKSEL_A>;
3865 impl SUT_CKSEL_R {
3866 ///Get enumerated values variant
3867 #[inline(always)]
3868 pub const fn variant(&self) -> Option<SUT_CKSEL_A> {
3869 match self.bits {
3870 0 => Some(SUT_CKSEL_A::EXTCLK_6CK_14CK_0MS),
3871 2 => Some(SUT_CKSEL_A::INTRCOSC_8MHZ_6CK_14CK_0MS),
3872 3 => Some(SUT_CKSEL_A::INTRCOSC_128KHZ_6CK_14CK_0MS),
3873 4 => Some(SUT_CKSEL_A::EXTLOFXTAL_1KCK_14CK_0MS),
3874 5 => Some(SUT_CKSEL_A::EXTLOFXTAL_32KCK_14CK_0MS),
3875 6 => Some(SUT_CKSEL_A::EXTFSXTAL_258CK_14CK_4MS1),
3876 7 => Some(SUT_CKSEL_A::EXTFSXTAL_1KCK_14CK_65MS),
3877 8 => Some(SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_4MS1),
3878 9 => Some(SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_65MS),
3879 10 => Some(SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_258CK_14CK_4MS1),
3880 11 => Some(SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_65MS),
3881 12 => Some(SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_258CK_14CK_4MS1),
3882 13 => Some(SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_1KCK_14CK_65MS),
3883 14 => Some(SUT_CKSEL_A::EXTXOSC_8MHZ_XX_258CK_14CK_4MS1),
3884 15 => Some(SUT_CKSEL_A::EXTXOSC_8MHZ_XX_1KCK_14CK_65MS),
3885 16 => Some(SUT_CKSEL_A::EXTCLK_6CK_14CK_4MS1),
3886 18 => Some(SUT_CKSEL_A::INTRCOSC_8MHZ_6CK_14CK_4MS1),
3887 19 => Some(SUT_CKSEL_A::INTRCOSC_128KHZ_6CK_14CK_4MS1),
3888 20 => Some(SUT_CKSEL_A::EXTLOFXTAL_1KCK_14CK_4MS1),
3889 21 => Some(SUT_CKSEL_A::EXTLOFXTAL_32KCK_14CK_4MS1),
3890 22 => Some(SUT_CKSEL_A::EXTFSXTAL_258CK_14CK_65MS),
3891 23 => Some(SUT_CKSEL_A::EXTFSXTAL_16KCK_14CK_0MS),
3892 24 => Some(SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_65MS),
3893 25 => Some(SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_0MS),
3894 26 => Some(SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_258CK_14CK_65MS),
3895 27 => Some(SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_0MS),
3896 28 => Some(SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_258CK_14CK_65MS),
3897 29 => Some(SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_16KCK_14CK_0MS),
3898 30 => Some(SUT_CKSEL_A::EXTXOSC_8MHZ_XX_258CK_14CK_65MS),
3899 31 => Some(SUT_CKSEL_A::EXTXOSC_8MHZ_XX_16KCK_14CK_0MS),
3900 32 => Some(SUT_CKSEL_A::EXTCLK_6CK_14CK_65MS),
3901 34 => Some(SUT_CKSEL_A::INTRCOSC_8MHZ_6CK_14CK_65MS),
3902 35 => Some(SUT_CKSEL_A::INTRCOSC_128KHZ_6CK_14CK_65MS),
3903 36 => Some(SUT_CKSEL_A::EXTLOFXTAL_1KCK_14CK_65MS),
3904 37 => Some(SUT_CKSEL_A::EXTLOFXTAL_32KCK_14CK_65MS),
3905 38 => Some(SUT_CKSEL_A::EXTFSXTAL_1KCK_14CK_0MS),
3906 39 => Some(SUT_CKSEL_A::EXTFSXTAL_16KCK_14CK_4MS1),
3907 40 => Some(SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_0MS),
3908 41 => Some(SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_4MS1),
3909 42 => Some(SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_0MS),
3910 43 => Some(SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_4MS1),
3911 44 => Some(SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_1KCK_14CK_0MS),
3912 45 => Some(SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_16KCK_14CK_4MS1),
3913 46 => Some(SUT_CKSEL_A::EXTXOSC_8MHZ_XX_1KCK_14CK_0MS),
3914 47 => Some(SUT_CKSEL_A::EXTXOSC_8MHZ_XX_16KCK_14CK_4MS1),
3915 54 => Some(SUT_CKSEL_A::EXTFSXTAL_1KCK_14CK_4MS1),
3916 55 => Some(SUT_CKSEL_A::EXTFSXTAL_16KCK_14CK_65MS),
3917 56 => Some(SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_4MS1),
3918 57 => Some(SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_65MS),
3919 58 => Some(SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_4MS1),
3920 59 => Some(SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_65MS),
3921 60 => Some(SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_1KCK_14CK_4MS1),
3922 61 => Some(SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_16KCK_14CK_65MS),
3923 62 => Some(SUT_CKSEL_A::EXTXOSC_8MHZ_XX_1KCK_14CK_4MS1),
3924 63 => Some(SUT_CKSEL_A::EXTXOSC_8MHZ_XX_16KCK_14CK_65MS),
3925 _ => None,
3926 }
3927 }
3928 ///Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms
3929 #[inline(always)]
3930 pub fn is_extclk_6ck_14ck_0ms(&self) -> bool {
3931 *self == SUT_CKSEL_A::EXTCLK_6CK_14CK_0MS
3932 }
3933 ///Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms
3934 #[inline(always)]
3935 pub fn is_intrcosc_8mhz_6ck_14ck_0ms(&self) -> bool {
3936 *self == SUT_CKSEL_A::INTRCOSC_8MHZ_6CK_14CK_0MS
3937 }
3938 ///Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms
3939 #[inline(always)]
3940 pub fn is_intrcosc_128khz_6ck_14ck_0ms(&self) -> bool {
3941 *self == SUT_CKSEL_A::INTRCOSC_128KHZ_6CK_14CK_0MS
3942 }
3943 ///Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 0 ms
3944 #[inline(always)]
3945 pub fn is_extlofxtal_1kck_14ck_0ms(&self) -> bool {
3946 *self == SUT_CKSEL_A::EXTLOFXTAL_1KCK_14CK_0MS
3947 }
3948 ///Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 0 ms
3949 #[inline(always)]
3950 pub fn is_extlofxtal_32kck_14ck_0ms(&self) -> bool {
3951 *self == SUT_CKSEL_A::EXTLOFXTAL_32KCK_14CK_0MS
3952 }
3953 ///Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms
3954 #[inline(always)]
3955 pub fn is_extfsxtal_258ck_14ck_4ms1(&self) -> bool {
3956 *self == SUT_CKSEL_A::EXTFSXTAL_258CK_14CK_4MS1
3957 }
3958 ///Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms
3959 #[inline(always)]
3960 pub fn is_extfsxtal_1kck_14ck_65ms(&self) -> bool {
3961 *self == SUT_CKSEL_A::EXTFSXTAL_1KCK_14CK_65MS
3962 }
3963 ///Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms
3964 #[inline(always)]
3965 pub fn is_extxosc_0mhz4_0mhz9_258ck_14ck_4ms1(&self) -> bool {
3966 *self == SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_4MS1
3967 }
3968 ///Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms
3969 #[inline(always)]
3970 pub fn is_extxosc_0mhz4_0mhz9_1kck_14ck_65ms(&self) -> bool {
3971 *self == SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_65MS
3972 }
3973 ///Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms
3974 #[inline(always)]
3975 pub fn is_extxosc_0mhz9_3mhz_258ck_14ck_4ms1(&self) -> bool {
3976 *self == SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_258CK_14CK_4MS1
3977 }
3978 ///Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms
3979 #[inline(always)]
3980 pub fn is_extxosc_0mhz9_3mhz_1kck_14ck_65ms(&self) -> bool {
3981 *self == SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_65MS
3982 }
3983 ///Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms
3984 #[inline(always)]
3985 pub fn is_extxosc_3mhz_8mhz_258ck_14ck_4ms1(&self) -> bool {
3986 *self == SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_258CK_14CK_4MS1
3987 }
3988 ///Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms
3989 #[inline(always)]
3990 pub fn is_extxosc_3mhz_8mhz_1kck_14ck_65ms(&self) -> bool {
3991 *self == SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_1KCK_14CK_65MS
3992 }
3993 ///Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms
3994 #[inline(always)]
3995 pub fn is_extxosc_8mhz_xx_258ck_14ck_4ms1(&self) -> bool {
3996 *self == SUT_CKSEL_A::EXTXOSC_8MHZ_XX_258CK_14CK_4MS1
3997 }
3998 ///Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms
3999 #[inline(always)]
4000 pub fn is_extxosc_8mhz_xx_1kck_14ck_65ms(&self) -> bool {
4001 *self == SUT_CKSEL_A::EXTXOSC_8MHZ_XX_1KCK_14CK_65MS
4002 }
4003 ///Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms
4004 #[inline(always)]
4005 pub fn is_extclk_6ck_14ck_4ms1(&self) -> bool {
4006 *self == SUT_CKSEL_A::EXTCLK_6CK_14CK_4MS1
4007 }
4008 ///Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms
4009 #[inline(always)]
4010 pub fn is_intrcosc_8mhz_6ck_14ck_4ms1(&self) -> bool {
4011 *self == SUT_CKSEL_A::INTRCOSC_8MHZ_6CK_14CK_4MS1
4012 }
4013 ///Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms
4014 #[inline(always)]
4015 pub fn is_intrcosc_128khz_6ck_14ck_4ms1(&self) -> bool {
4016 *self == SUT_CKSEL_A::INTRCOSC_128KHZ_6CK_14CK_4MS1
4017 }
4018 ///Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 4.1 ms
4019 #[inline(always)]
4020 pub fn is_extlofxtal_1kck_14ck_4ms1(&self) -> bool {
4021 *self == SUT_CKSEL_A::EXTLOFXTAL_1KCK_14CK_4MS1
4022 }
4023 ///Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 4.1 ms
4024 #[inline(always)]
4025 pub fn is_extlofxtal_32kck_14ck_4ms1(&self) -> bool {
4026 *self == SUT_CKSEL_A::EXTLOFXTAL_32KCK_14CK_4MS1
4027 }
4028 ///Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms
4029 #[inline(always)]
4030 pub fn is_extfsxtal_258ck_14ck_65ms(&self) -> bool {
4031 *self == SUT_CKSEL_A::EXTFSXTAL_258CK_14CK_65MS
4032 }
4033 ///Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms
4034 #[inline(always)]
4035 pub fn is_extfsxtal_16kck_14ck_0ms(&self) -> bool {
4036 *self == SUT_CKSEL_A::EXTFSXTAL_16KCK_14CK_0MS
4037 }
4038 ///Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms
4039 #[inline(always)]
4040 pub fn is_extxosc_0mhz4_0mhz9_258ck_14ck_65ms(&self) -> bool {
4041 *self == SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_65MS
4042 }
4043 ///Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms
4044 #[inline(always)]
4045 pub fn is_extxosc_0mhz4_0mhz9_16kck_14ck_0ms(&self) -> bool {
4046 *self == SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_0MS
4047 }
4048 ///Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms
4049 #[inline(always)]
4050 pub fn is_extxosc_0mhz9_3mhz_258ck_14ck_65ms(&self) -> bool {
4051 *self == SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_258CK_14CK_65MS
4052 }
4053 ///Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms
4054 #[inline(always)]
4055 pub fn is_extxosc_0mhz9_3mhz_16kck_14ck_0ms(&self) -> bool {
4056 *self == SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_0MS
4057 }
4058 ///Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms
4059 #[inline(always)]
4060 pub fn is_extxosc_3mhz_8mhz_258ck_14ck_65ms(&self) -> bool {
4061 *self == SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_258CK_14CK_65MS
4062 }
4063 ///Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms
4064 #[inline(always)]
4065 pub fn is_extxosc_3mhz_8mhz_16kck_14ck_0ms(&self) -> bool {
4066 *self == SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_16KCK_14CK_0MS
4067 }
4068 ///Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms
4069 #[inline(always)]
4070 pub fn is_extxosc_8mhz_xx_258ck_14ck_65ms(&self) -> bool {
4071 *self == SUT_CKSEL_A::EXTXOSC_8MHZ_XX_258CK_14CK_65MS
4072 }
4073 ///Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms
4074 #[inline(always)]
4075 pub fn is_extxosc_8mhz_xx_16kck_14ck_0ms(&self) -> bool {
4076 *self == SUT_CKSEL_A::EXTXOSC_8MHZ_XX_16KCK_14CK_0MS
4077 }
4078 ///Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms
4079 #[inline(always)]
4080 pub fn is_extclk_6ck_14ck_65ms(&self) -> bool {
4081 *self == SUT_CKSEL_A::EXTCLK_6CK_14CK_65MS
4082 }
4083 ///Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms
4084 #[inline(always)]
4085 pub fn is_intrcosc_8mhz_6ck_14ck_65ms(&self) -> bool {
4086 *self == SUT_CKSEL_A::INTRCOSC_8MHZ_6CK_14CK_65MS
4087 }
4088 ///Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms
4089 #[inline(always)]
4090 pub fn is_intrcosc_128khz_6ck_14ck_65ms(&self) -> bool {
4091 *self == SUT_CKSEL_A::INTRCOSC_128KHZ_6CK_14CK_65MS
4092 }
4093 ///Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 65 ms
4094 #[inline(always)]
4095 pub fn is_extlofxtal_1kck_14ck_65ms(&self) -> bool {
4096 *self == SUT_CKSEL_A::EXTLOFXTAL_1KCK_14CK_65MS
4097 }
4098 ///Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 65 ms
4099 #[inline(always)]
4100 pub fn is_extlofxtal_32kck_14ck_65ms(&self) -> bool {
4101 *self == SUT_CKSEL_A::EXTLOFXTAL_32KCK_14CK_65MS
4102 }
4103 ///Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms
4104 #[inline(always)]
4105 pub fn is_extfsxtal_1kck_14ck_0ms(&self) -> bool {
4106 *self == SUT_CKSEL_A::EXTFSXTAL_1KCK_14CK_0MS
4107 }
4108 ///Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms
4109 #[inline(always)]
4110 pub fn is_extfsxtal_16kck_14ck_4ms1(&self) -> bool {
4111 *self == SUT_CKSEL_A::EXTFSXTAL_16KCK_14CK_4MS1
4112 }
4113 ///Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms
4114 #[inline(always)]
4115 pub fn is_extxosc_0mhz4_0mhz9_1kck_14ck_0ms(&self) -> bool {
4116 *self == SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_0MS
4117 }
4118 ///Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms
4119 #[inline(always)]
4120 pub fn is_extxosc_0mhz4_0mhz9_16kck_14ck_4ms1(&self) -> bool {
4121 *self == SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_4MS1
4122 }
4123 ///Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms
4124 #[inline(always)]
4125 pub fn is_extxosc_0mhz9_3mhz_1kck_14ck_0ms(&self) -> bool {
4126 *self == SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_0MS
4127 }
4128 ///Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms
4129 #[inline(always)]
4130 pub fn is_extxosc_0mhz9_3mhz_16kck_14ck_4ms1(&self) -> bool {
4131 *self == SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_4MS1
4132 }
4133 ///Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms
4134 #[inline(always)]
4135 pub fn is_extxosc_3mhz_8mhz_1kck_14ck_0ms(&self) -> bool {
4136 *self == SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_1KCK_14CK_0MS
4137 }
4138 ///Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms
4139 #[inline(always)]
4140 pub fn is_extxosc_3mhz_8mhz_16kck_14ck_4ms1(&self) -> bool {
4141 *self == SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_16KCK_14CK_4MS1
4142 }
4143 ///Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms
4144 #[inline(always)]
4145 pub fn is_extxosc_8mhz_xx_1kck_14ck_0ms(&self) -> bool {
4146 *self == SUT_CKSEL_A::EXTXOSC_8MHZ_XX_1KCK_14CK_0MS
4147 }
4148 ///Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms
4149 #[inline(always)]
4150 pub fn is_extxosc_8mhz_xx_16kck_14ck_4ms1(&self) -> bool {
4151 *self == SUT_CKSEL_A::EXTXOSC_8MHZ_XX_16KCK_14CK_4MS1
4152 }
4153 ///Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms
4154 #[inline(always)]
4155 pub fn is_extfsxtal_1kck_14ck_4ms1(&self) -> bool {
4156 *self == SUT_CKSEL_A::EXTFSXTAL_1KCK_14CK_4MS1
4157 }
4158 ///Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms
4159 #[inline(always)]
4160 pub fn is_extfsxtal_16kck_14ck_65ms(&self) -> bool {
4161 *self == SUT_CKSEL_A::EXTFSXTAL_16KCK_14CK_65MS
4162 }
4163 ///Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms
4164 #[inline(always)]
4165 pub fn is_extxosc_0mhz4_0mhz9_1kck_14ck_4ms1(&self) -> bool {
4166 *self == SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_4MS1
4167 }
4168 ///Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms
4169 #[inline(always)]
4170 pub fn is_extxosc_0mhz4_0mhz9_16kck_14ck_65ms(&self) -> bool {
4171 *self == SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_65MS
4172 }
4173 ///Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms
4174 #[inline(always)]
4175 pub fn is_extxosc_0mhz9_3mhz_1kck_14ck_4ms1(&self) -> bool {
4176 *self == SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_4MS1
4177 }
4178 ///Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms
4179 #[inline(always)]
4180 pub fn is_extxosc_0mhz9_3mhz_16kck_14ck_65ms(&self) -> bool {
4181 *self == SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_65MS
4182 }
4183 ///Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms
4184 #[inline(always)]
4185 pub fn is_extxosc_3mhz_8mhz_1kck_14ck_4ms1(&self) -> bool {
4186 *self == SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_1KCK_14CK_4MS1
4187 }
4188 ///Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms
4189 #[inline(always)]
4190 pub fn is_extxosc_3mhz_8mhz_16kck_14ck_65ms(&self) -> bool {
4191 *self == SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_16KCK_14CK_65MS
4192 }
4193 ///Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms
4194 #[inline(always)]
4195 pub fn is_extxosc_8mhz_xx_1kck_14ck_4ms1(&self) -> bool {
4196 *self == SUT_CKSEL_A::EXTXOSC_8MHZ_XX_1KCK_14CK_4MS1
4197 }
4198 ///Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms
4199 #[inline(always)]
4200 pub fn is_extxosc_8mhz_xx_16kck_14ck_65ms(&self) -> bool {
4201 *self == SUT_CKSEL_A::EXTXOSC_8MHZ_XX_16KCK_14CK_65MS
4202 }
4203 }
4204 ///Field `SUT_CKSEL` writer - Select Clock Source
4205 pub type SUT_CKSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6, SUT_CKSEL_A>;
4206 impl<'a, REG> SUT_CKSEL_W<'a, REG>
4207 where
4208 REG: crate::Writable + crate::RegisterSpec,
4209 REG::Ux: From<u8>,
4210 {
4211 ///Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms
4212 #[inline(always)]
4213 pub fn extclk_6ck_14ck_0ms(self) -> &'a mut crate::W<REG> {
4214 self.variant(SUT_CKSEL_A::EXTCLK_6CK_14CK_0MS)
4215 }
4216 ///Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms
4217 #[inline(always)]
4218 pub fn intrcosc_8mhz_6ck_14ck_0ms(self) -> &'a mut crate::W<REG> {
4219 self.variant(SUT_CKSEL_A::INTRCOSC_8MHZ_6CK_14CK_0MS)
4220 }
4221 ///Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms
4222 #[inline(always)]
4223 pub fn intrcosc_128khz_6ck_14ck_0ms(self) -> &'a mut crate::W<REG> {
4224 self.variant(SUT_CKSEL_A::INTRCOSC_128KHZ_6CK_14CK_0MS)
4225 }
4226 ///Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 0 ms
4227 #[inline(always)]
4228 pub fn extlofxtal_1kck_14ck_0ms(self) -> &'a mut crate::W<REG> {
4229 self.variant(SUT_CKSEL_A::EXTLOFXTAL_1KCK_14CK_0MS)
4230 }
4231 ///Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 0 ms
4232 #[inline(always)]
4233 pub fn extlofxtal_32kck_14ck_0ms(self) -> &'a mut crate::W<REG> {
4234 self.variant(SUT_CKSEL_A::EXTLOFXTAL_32KCK_14CK_0MS)
4235 }
4236 ///Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms
4237 #[inline(always)]
4238 pub fn extfsxtal_258ck_14ck_4ms1(self) -> &'a mut crate::W<REG> {
4239 self.variant(SUT_CKSEL_A::EXTFSXTAL_258CK_14CK_4MS1)
4240 }
4241 ///Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms
4242 #[inline(always)]
4243 pub fn extfsxtal_1kck_14ck_65ms(self) -> &'a mut crate::W<REG> {
4244 self.variant(SUT_CKSEL_A::EXTFSXTAL_1KCK_14CK_65MS)
4245 }
4246 ///Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms
4247 #[inline(always)]
4248 pub fn extxosc_0mhz4_0mhz9_258ck_14ck_4ms1(self) -> &'a mut crate::W<REG> {
4249 self.variant(SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_4MS1)
4250 }
4251 ///Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms
4252 #[inline(always)]
4253 pub fn extxosc_0mhz4_0mhz9_1kck_14ck_65ms(self) -> &'a mut crate::W<REG> {
4254 self.variant(SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_65MS)
4255 }
4256 ///Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms
4257 #[inline(always)]
4258 pub fn extxosc_0mhz9_3mhz_258ck_14ck_4ms1(self) -> &'a mut crate::W<REG> {
4259 self.variant(SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_258CK_14CK_4MS1)
4260 }
4261 ///Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms
4262 #[inline(always)]
4263 pub fn extxosc_0mhz9_3mhz_1kck_14ck_65ms(self) -> &'a mut crate::W<REG> {
4264 self.variant(SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_65MS)
4265 }
4266 ///Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms
4267 #[inline(always)]
4268 pub fn extxosc_3mhz_8mhz_258ck_14ck_4ms1(self) -> &'a mut crate::W<REG> {
4269 self.variant(SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_258CK_14CK_4MS1)
4270 }
4271 ///Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms
4272 #[inline(always)]
4273 pub fn extxosc_3mhz_8mhz_1kck_14ck_65ms(self) -> &'a mut crate::W<REG> {
4274 self.variant(SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_1KCK_14CK_65MS)
4275 }
4276 ///Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms
4277 #[inline(always)]
4278 pub fn extxosc_8mhz_xx_258ck_14ck_4ms1(self) -> &'a mut crate::W<REG> {
4279 self.variant(SUT_CKSEL_A::EXTXOSC_8MHZ_XX_258CK_14CK_4MS1)
4280 }
4281 ///Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms
4282 #[inline(always)]
4283 pub fn extxosc_8mhz_xx_1kck_14ck_65ms(self) -> &'a mut crate::W<REG> {
4284 self.variant(SUT_CKSEL_A::EXTXOSC_8MHZ_XX_1KCK_14CK_65MS)
4285 }
4286 ///Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms
4287 #[inline(always)]
4288 pub fn extclk_6ck_14ck_4ms1(self) -> &'a mut crate::W<REG> {
4289 self.variant(SUT_CKSEL_A::EXTCLK_6CK_14CK_4MS1)
4290 }
4291 ///Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms
4292 #[inline(always)]
4293 pub fn intrcosc_8mhz_6ck_14ck_4ms1(self) -> &'a mut crate::W<REG> {
4294 self.variant(SUT_CKSEL_A::INTRCOSC_8MHZ_6CK_14CK_4MS1)
4295 }
4296 ///Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms
4297 #[inline(always)]
4298 pub fn intrcosc_128khz_6ck_14ck_4ms1(self) -> &'a mut crate::W<REG> {
4299 self.variant(SUT_CKSEL_A::INTRCOSC_128KHZ_6CK_14CK_4MS1)
4300 }
4301 ///Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 4.1 ms
4302 #[inline(always)]
4303 pub fn extlofxtal_1kck_14ck_4ms1(self) -> &'a mut crate::W<REG> {
4304 self.variant(SUT_CKSEL_A::EXTLOFXTAL_1KCK_14CK_4MS1)
4305 }
4306 ///Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 4.1 ms
4307 #[inline(always)]
4308 pub fn extlofxtal_32kck_14ck_4ms1(self) -> &'a mut crate::W<REG> {
4309 self.variant(SUT_CKSEL_A::EXTLOFXTAL_32KCK_14CK_4MS1)
4310 }
4311 ///Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms
4312 #[inline(always)]
4313 pub fn extfsxtal_258ck_14ck_65ms(self) -> &'a mut crate::W<REG> {
4314 self.variant(SUT_CKSEL_A::EXTFSXTAL_258CK_14CK_65MS)
4315 }
4316 ///Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms
4317 #[inline(always)]
4318 pub fn extfsxtal_16kck_14ck_0ms(self) -> &'a mut crate::W<REG> {
4319 self.variant(SUT_CKSEL_A::EXTFSXTAL_16KCK_14CK_0MS)
4320 }
4321 ///Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms
4322 #[inline(always)]
4323 pub fn extxosc_0mhz4_0mhz9_258ck_14ck_65ms(self) -> &'a mut crate::W<REG> {
4324 self.variant(SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_65MS)
4325 }
4326 ///Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms
4327 #[inline(always)]
4328 pub fn extxosc_0mhz4_0mhz9_16kck_14ck_0ms(self) -> &'a mut crate::W<REG> {
4329 self.variant(SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_0MS)
4330 }
4331 ///Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms
4332 #[inline(always)]
4333 pub fn extxosc_0mhz9_3mhz_258ck_14ck_65ms(self) -> &'a mut crate::W<REG> {
4334 self.variant(SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_258CK_14CK_65MS)
4335 }
4336 ///Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms
4337 #[inline(always)]
4338 pub fn extxosc_0mhz9_3mhz_16kck_14ck_0ms(self) -> &'a mut crate::W<REG> {
4339 self.variant(SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_0MS)
4340 }
4341 ///Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms
4342 #[inline(always)]
4343 pub fn extxosc_3mhz_8mhz_258ck_14ck_65ms(self) -> &'a mut crate::W<REG> {
4344 self.variant(SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_258CK_14CK_65MS)
4345 }
4346 ///Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms
4347 #[inline(always)]
4348 pub fn extxosc_3mhz_8mhz_16kck_14ck_0ms(self) -> &'a mut crate::W<REG> {
4349 self.variant(SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_16KCK_14CK_0MS)
4350 }
4351 ///Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms
4352 #[inline(always)]
4353 pub fn extxosc_8mhz_xx_258ck_14ck_65ms(self) -> &'a mut crate::W<REG> {
4354 self.variant(SUT_CKSEL_A::EXTXOSC_8MHZ_XX_258CK_14CK_65MS)
4355 }
4356 ///Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms
4357 #[inline(always)]
4358 pub fn extxosc_8mhz_xx_16kck_14ck_0ms(self) -> &'a mut crate::W<REG> {
4359 self.variant(SUT_CKSEL_A::EXTXOSC_8MHZ_XX_16KCK_14CK_0MS)
4360 }
4361 ///Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms
4362 #[inline(always)]
4363 pub fn extclk_6ck_14ck_65ms(self) -> &'a mut crate::W<REG> {
4364 self.variant(SUT_CKSEL_A::EXTCLK_6CK_14CK_65MS)
4365 }
4366 ///Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms
4367 #[inline(always)]
4368 pub fn intrcosc_8mhz_6ck_14ck_65ms(self) -> &'a mut crate::W<REG> {
4369 self.variant(SUT_CKSEL_A::INTRCOSC_8MHZ_6CK_14CK_65MS)
4370 }
4371 ///Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms
4372 #[inline(always)]
4373 pub fn intrcosc_128khz_6ck_14ck_65ms(self) -> &'a mut crate::W<REG> {
4374 self.variant(SUT_CKSEL_A::INTRCOSC_128KHZ_6CK_14CK_65MS)
4375 }
4376 ///Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 65 ms
4377 #[inline(always)]
4378 pub fn extlofxtal_1kck_14ck_65ms(self) -> &'a mut crate::W<REG> {
4379 self.variant(SUT_CKSEL_A::EXTLOFXTAL_1KCK_14CK_65MS)
4380 }
4381 ///Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 65 ms
4382 #[inline(always)]
4383 pub fn extlofxtal_32kck_14ck_65ms(self) -> &'a mut crate::W<REG> {
4384 self.variant(SUT_CKSEL_A::EXTLOFXTAL_32KCK_14CK_65MS)
4385 }
4386 ///Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms
4387 #[inline(always)]
4388 pub fn extfsxtal_1kck_14ck_0ms(self) -> &'a mut crate::W<REG> {
4389 self.variant(SUT_CKSEL_A::EXTFSXTAL_1KCK_14CK_0MS)
4390 }
4391 ///Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms
4392 #[inline(always)]
4393 pub fn extfsxtal_16kck_14ck_4ms1(self) -> &'a mut crate::W<REG> {
4394 self.variant(SUT_CKSEL_A::EXTFSXTAL_16KCK_14CK_4MS1)
4395 }
4396 ///Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms
4397 #[inline(always)]
4398 pub fn extxosc_0mhz4_0mhz9_1kck_14ck_0ms(self) -> &'a mut crate::W<REG> {
4399 self.variant(SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_0MS)
4400 }
4401 ///Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms
4402 #[inline(always)]
4403 pub fn extxosc_0mhz4_0mhz9_16kck_14ck_4ms1(self) -> &'a mut crate::W<REG> {
4404 self.variant(SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_4MS1)
4405 }
4406 ///Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms
4407 #[inline(always)]
4408 pub fn extxosc_0mhz9_3mhz_1kck_14ck_0ms(self) -> &'a mut crate::W<REG> {
4409 self.variant(SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_0MS)
4410 }
4411 ///Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms
4412 #[inline(always)]
4413 pub fn extxosc_0mhz9_3mhz_16kck_14ck_4ms1(self) -> &'a mut crate::W<REG> {
4414 self.variant(SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_4MS1)
4415 }
4416 ///Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms
4417 #[inline(always)]
4418 pub fn extxosc_3mhz_8mhz_1kck_14ck_0ms(self) -> &'a mut crate::W<REG> {
4419 self.variant(SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_1KCK_14CK_0MS)
4420 }
4421 ///Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms
4422 #[inline(always)]
4423 pub fn extxosc_3mhz_8mhz_16kck_14ck_4ms1(self) -> &'a mut crate::W<REG> {
4424 self.variant(SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_16KCK_14CK_4MS1)
4425 }
4426 ///Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms
4427 #[inline(always)]
4428 pub fn extxosc_8mhz_xx_1kck_14ck_0ms(self) -> &'a mut crate::W<REG> {
4429 self.variant(SUT_CKSEL_A::EXTXOSC_8MHZ_XX_1KCK_14CK_0MS)
4430 }
4431 ///Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms
4432 #[inline(always)]
4433 pub fn extxosc_8mhz_xx_16kck_14ck_4ms1(self) -> &'a mut crate::W<REG> {
4434 self.variant(SUT_CKSEL_A::EXTXOSC_8MHZ_XX_16KCK_14CK_4MS1)
4435 }
4436 ///Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms
4437 #[inline(always)]
4438 pub fn extfsxtal_1kck_14ck_4ms1(self) -> &'a mut crate::W<REG> {
4439 self.variant(SUT_CKSEL_A::EXTFSXTAL_1KCK_14CK_4MS1)
4440 }
4441 ///Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms
4442 #[inline(always)]
4443 pub fn extfsxtal_16kck_14ck_65ms(self) -> &'a mut crate::W<REG> {
4444 self.variant(SUT_CKSEL_A::EXTFSXTAL_16KCK_14CK_65MS)
4445 }
4446 ///Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms
4447 #[inline(always)]
4448 pub fn extxosc_0mhz4_0mhz9_1kck_14ck_4ms1(self) -> &'a mut crate::W<REG> {
4449 self.variant(SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_4MS1)
4450 }
4451 ///Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms
4452 #[inline(always)]
4453 pub fn extxosc_0mhz4_0mhz9_16kck_14ck_65ms(self) -> &'a mut crate::W<REG> {
4454 self.variant(SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_65MS)
4455 }
4456 ///Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms
4457 #[inline(always)]
4458 pub fn extxosc_0mhz9_3mhz_1kck_14ck_4ms1(self) -> &'a mut crate::W<REG> {
4459 self.variant(SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_4MS1)
4460 }
4461 ///Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms
4462 #[inline(always)]
4463 pub fn extxosc_0mhz9_3mhz_16kck_14ck_65ms(self) -> &'a mut crate::W<REG> {
4464 self.variant(SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_65MS)
4465 }
4466 ///Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms
4467 #[inline(always)]
4468 pub fn extxosc_3mhz_8mhz_1kck_14ck_4ms1(self) -> &'a mut crate::W<REG> {
4469 self.variant(SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_1KCK_14CK_4MS1)
4470 }
4471 ///Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms
4472 #[inline(always)]
4473 pub fn extxosc_3mhz_8mhz_16kck_14ck_65ms(self) -> &'a mut crate::W<REG> {
4474 self.variant(SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_16KCK_14CK_65MS)
4475 }
4476 ///Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms
4477 #[inline(always)]
4478 pub fn extxosc_8mhz_xx_1kck_14ck_4ms1(self) -> &'a mut crate::W<REG> {
4479 self.variant(SUT_CKSEL_A::EXTXOSC_8MHZ_XX_1KCK_14CK_4MS1)
4480 }
4481 ///Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms
4482 #[inline(always)]
4483 pub fn extxosc_8mhz_xx_16kck_14ck_65ms(self) -> &'a mut crate::W<REG> {
4484 self.variant(SUT_CKSEL_A::EXTXOSC_8MHZ_XX_16KCK_14CK_65MS)
4485 }
4486 }
4487 ///Field `CKOUT` reader - Clock output on PORTB0
4488 pub type CKOUT_R = crate::BitReader;
4489 ///Field `CKOUT` writer - Clock output on PORTB0
4490 pub type CKOUT_W<'a, REG> = crate::BitWriter<'a, REG>;
4491 ///Field `CKDIV8` reader - Divide clock by 8 internally
4492 pub type CKDIV8_R = crate::BitReader;
4493 ///Field `CKDIV8` writer - Divide clock by 8 internally
4494 pub type CKDIV8_W<'a, REG> = crate::BitWriter<'a, REG>;
4495 impl R {
4496 ///Bits 0:5 - Select Clock Source
4497 #[inline(always)]
4498 pub fn sut_cksel(&self) -> SUT_CKSEL_R {
4499 SUT_CKSEL_R::new(self.bits & 0x3f)
4500 }
4501 ///Bit 6 - Clock output on PORTB0
4502 #[inline(always)]
4503 pub fn ckout(&self) -> CKOUT_R {
4504 CKOUT_R::new(((self.bits >> 6) & 1) != 0)
4505 }
4506 ///Bit 7 - Divide clock by 8 internally
4507 #[inline(always)]
4508 pub fn ckdiv8(&self) -> CKDIV8_R {
4509 CKDIV8_R::new(((self.bits >> 7) & 1) != 0)
4510 }
4511 }
4512 impl W {
4513 ///Bits 0:5 - Select Clock Source
4514 #[inline(always)]
4515 pub fn sut_cksel(&mut self) -> SUT_CKSEL_W<'_, LOW_SPEC> {
4516 SUT_CKSEL_W::new(self, 0)
4517 }
4518 ///Bit 6 - Clock output on PORTB0
4519 #[inline(always)]
4520 pub fn ckout(&mut self) -> CKOUT_W<'_, LOW_SPEC> {
4521 CKOUT_W::new(self, 6)
4522 }
4523 ///Bit 7 - Divide clock by 8 internally
4524 #[inline(always)]
4525 pub fn ckdiv8(&mut self) -> CKDIV8_W<'_, LOW_SPEC> {
4526 CKDIV8_W::new(self, 7)
4527 }
4528 }
4529 /**No Description.
4530
4531You can [`read`](crate::Reg::read) this register and get [`low::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`low::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
4532 pub struct LOW_SPEC;
4533 impl crate::RegisterSpec for LOW_SPEC {
4534 type Ux = u8;
4535 }
4536 ///`read()` method returns [`low::R`](R) reader structure
4537 impl crate::Readable for LOW_SPEC {}
4538 ///`write(|w| ..)` method takes [`low::W`](W) writer structure
4539 impl crate::Writable for LOW_SPEC {
4540 type Safety = crate::Unsafe;
4541 }
4542 ///`reset()` method sets LOW to value 0
4543 impl crate::Resettable for LOW_SPEC {}
4544 }
4545}
4546///Lockbits
4547pub type LOCKBIT = crate::Periph<lockbit::RegisterBlock, 0>;
4548impl core::fmt::Debug for LOCKBIT {
4549 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
4550 f.debug_struct("LOCKBIT").finish()
4551 }
4552}
4553///Lockbits
4554pub mod lockbit {
4555 #[repr(C)]
4556 ///Register block
4557 pub struct RegisterBlock {
4558 lockbit: LOCKBIT,
4559 }
4560 impl RegisterBlock {
4561 ///0x00 - No Description.
4562 #[inline(always)]
4563 pub const fn lockbit(&self) -> &LOCKBIT {
4564 &self.lockbit
4565 }
4566 }
4567 /**LOCKBIT (rw) register accessor: No Description.
4568
4569You can [`read`](crate::Reg::read) this register and get [`lockbit::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lockbit::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
4570
4571For information about available fields see [`mod@lockbit`] module*/
4572 pub type LOCKBIT = crate::Reg<lockbit::LOCKBIT_SPEC>;
4573 ///No Description.
4574 pub mod lockbit {
4575 ///Register `LOCKBIT` reader
4576 pub type R = crate::R<LOCKBIT_SPEC>;
4577 ///Register `LOCKBIT` writer
4578 pub type W = crate::W<LOCKBIT_SPEC>;
4579 /**Memory Lock
4580
4581Value on reset: 0*/
4582 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
4583 #[repr(u8)]
4584 pub enum LB_A {
4585 ///0: Further programming and verification disabled
4586 PROG_VER_DISABLED = 0,
4587 ///2: Further programming disabled
4588 PROG_DISABLED = 2,
4589 ///3: No memory lock features enabled
4590 NO_LOCK = 3,
4591 }
4592 impl From<LB_A> for u8 {
4593 #[inline(always)]
4594 fn from(variant: LB_A) -> Self {
4595 variant as _
4596 }
4597 }
4598 impl crate::FieldSpec for LB_A {
4599 type Ux = u8;
4600 }
4601 impl crate::IsEnum for LB_A {}
4602 ///Field `LB` reader - Memory Lock
4603 pub type LB_R = crate::FieldReader<LB_A>;
4604 impl LB_R {
4605 ///Get enumerated values variant
4606 #[inline(always)]
4607 pub const fn variant(&self) -> Option<LB_A> {
4608 match self.bits {
4609 0 => Some(LB_A::PROG_VER_DISABLED),
4610 2 => Some(LB_A::PROG_DISABLED),
4611 3 => Some(LB_A::NO_LOCK),
4612 _ => None,
4613 }
4614 }
4615 ///Further programming and verification disabled
4616 #[inline(always)]
4617 pub fn is_prog_ver_disabled(&self) -> bool {
4618 *self == LB_A::PROG_VER_DISABLED
4619 }
4620 ///Further programming disabled
4621 #[inline(always)]
4622 pub fn is_prog_disabled(&self) -> bool {
4623 *self == LB_A::PROG_DISABLED
4624 }
4625 ///No memory lock features enabled
4626 #[inline(always)]
4627 pub fn is_no_lock(&self) -> bool {
4628 *self == LB_A::NO_LOCK
4629 }
4630 }
4631 ///Field `LB` writer - Memory Lock
4632 pub type LB_W<'a, REG> = crate::FieldWriter<'a, REG, 2, LB_A>;
4633 impl<'a, REG> LB_W<'a, REG>
4634 where
4635 REG: crate::Writable + crate::RegisterSpec,
4636 REG::Ux: From<u8>,
4637 {
4638 ///Further programming and verification disabled
4639 #[inline(always)]
4640 pub fn prog_ver_disabled(self) -> &'a mut crate::W<REG> {
4641 self.variant(LB_A::PROG_VER_DISABLED)
4642 }
4643 ///Further programming disabled
4644 #[inline(always)]
4645 pub fn prog_disabled(self) -> &'a mut crate::W<REG> {
4646 self.variant(LB_A::PROG_DISABLED)
4647 }
4648 ///No memory lock features enabled
4649 #[inline(always)]
4650 pub fn no_lock(self) -> &'a mut crate::W<REG> {
4651 self.variant(LB_A::NO_LOCK)
4652 }
4653 }
4654 /**Boot Loader Protection Mode
4655
4656Value on reset: 0*/
4657 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
4658 #[repr(u8)]
4659 pub enum BLB0_A {
4660 ///0: LPM and SPM prohibited in Application Section
4661 LPM_SPM_DISABLE = 0,
4662 ///1: LPM prohibited in Application Section
4663 LPM_DISABLE = 1,
4664 ///2: SPM prohibited in Application Section
4665 SPM_DISABLE = 2,
4666 ///3: No lock on SPM and LPM in Application Section
4667 NO_LOCK = 3,
4668 }
4669 impl From<BLB0_A> for u8 {
4670 #[inline(always)]
4671 fn from(variant: BLB0_A) -> Self {
4672 variant as _
4673 }
4674 }
4675 impl crate::FieldSpec for BLB0_A {
4676 type Ux = u8;
4677 }
4678 impl crate::IsEnum for BLB0_A {}
4679 ///Field `BLB0` reader - Boot Loader Protection Mode
4680 pub type BLB0_R = crate::FieldReader<BLB0_A>;
4681 impl BLB0_R {
4682 ///Get enumerated values variant
4683 #[inline(always)]
4684 pub const fn variant(&self) -> BLB0_A {
4685 match self.bits {
4686 0 => BLB0_A::LPM_SPM_DISABLE,
4687 1 => BLB0_A::LPM_DISABLE,
4688 2 => BLB0_A::SPM_DISABLE,
4689 3 => BLB0_A::NO_LOCK,
4690 _ => unreachable!(),
4691 }
4692 }
4693 ///LPM and SPM prohibited in Application Section
4694 #[inline(always)]
4695 pub fn is_lpm_spm_disable(&self) -> bool {
4696 *self == BLB0_A::LPM_SPM_DISABLE
4697 }
4698 ///LPM prohibited in Application Section
4699 #[inline(always)]
4700 pub fn is_lpm_disable(&self) -> bool {
4701 *self == BLB0_A::LPM_DISABLE
4702 }
4703 ///SPM prohibited in Application Section
4704 #[inline(always)]
4705 pub fn is_spm_disable(&self) -> bool {
4706 *self == BLB0_A::SPM_DISABLE
4707 }
4708 ///No lock on SPM and LPM in Application Section
4709 #[inline(always)]
4710 pub fn is_no_lock(&self) -> bool {
4711 *self == BLB0_A::NO_LOCK
4712 }
4713 }
4714 ///Field `BLB0` writer - Boot Loader Protection Mode
4715 pub type BLB0_W<'a, REG> = crate::FieldWriter<'a, REG, 2, BLB0_A, crate::Safe>;
4716 impl<'a, REG> BLB0_W<'a, REG>
4717 where
4718 REG: crate::Writable + crate::RegisterSpec,
4719 REG::Ux: From<u8>,
4720 {
4721 ///LPM and SPM prohibited in Application Section
4722 #[inline(always)]
4723 pub fn lpm_spm_disable(self) -> &'a mut crate::W<REG> {
4724 self.variant(BLB0_A::LPM_SPM_DISABLE)
4725 }
4726 ///LPM prohibited in Application Section
4727 #[inline(always)]
4728 pub fn lpm_disable(self) -> &'a mut crate::W<REG> {
4729 self.variant(BLB0_A::LPM_DISABLE)
4730 }
4731 ///SPM prohibited in Application Section
4732 #[inline(always)]
4733 pub fn spm_disable(self) -> &'a mut crate::W<REG> {
4734 self.variant(BLB0_A::SPM_DISABLE)
4735 }
4736 ///No lock on SPM and LPM in Application Section
4737 #[inline(always)]
4738 pub fn no_lock(self) -> &'a mut crate::W<REG> {
4739 self.variant(BLB0_A::NO_LOCK)
4740 }
4741 }
4742 /**Boot Loader Protection Mode
4743
4744Value on reset: 0*/
4745 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
4746 #[repr(u8)]
4747 pub enum BLB1_A {
4748 ///0: LPM and SPM prohibited in Boot Section
4749 LPM_SPM_DISABLE = 0,
4750 ///1: LPM prohibited in Boot Section
4751 LPM_DISABLE = 1,
4752 ///2: SPM prohibited in Boot Section
4753 SPM_DISABLE = 2,
4754 ///3: No lock on SPM and LPM in Boot Section
4755 NO_LOCK = 3,
4756 }
4757 impl From<BLB1_A> for u8 {
4758 #[inline(always)]
4759 fn from(variant: BLB1_A) -> Self {
4760 variant as _
4761 }
4762 }
4763 impl crate::FieldSpec for BLB1_A {
4764 type Ux = u8;
4765 }
4766 impl crate::IsEnum for BLB1_A {}
4767 ///Field `BLB1` reader - Boot Loader Protection Mode
4768 pub type BLB1_R = crate::FieldReader<BLB1_A>;
4769 impl BLB1_R {
4770 ///Get enumerated values variant
4771 #[inline(always)]
4772 pub const fn variant(&self) -> BLB1_A {
4773 match self.bits {
4774 0 => BLB1_A::LPM_SPM_DISABLE,
4775 1 => BLB1_A::LPM_DISABLE,
4776 2 => BLB1_A::SPM_DISABLE,
4777 3 => BLB1_A::NO_LOCK,
4778 _ => unreachable!(),
4779 }
4780 }
4781 ///LPM and SPM prohibited in Boot Section
4782 #[inline(always)]
4783 pub fn is_lpm_spm_disable(&self) -> bool {
4784 *self == BLB1_A::LPM_SPM_DISABLE
4785 }
4786 ///LPM prohibited in Boot Section
4787 #[inline(always)]
4788 pub fn is_lpm_disable(&self) -> bool {
4789 *self == BLB1_A::LPM_DISABLE
4790 }
4791 ///SPM prohibited in Boot Section
4792 #[inline(always)]
4793 pub fn is_spm_disable(&self) -> bool {
4794 *self == BLB1_A::SPM_DISABLE
4795 }
4796 ///No lock on SPM and LPM in Boot Section
4797 #[inline(always)]
4798 pub fn is_no_lock(&self) -> bool {
4799 *self == BLB1_A::NO_LOCK
4800 }
4801 }
4802 ///Field `BLB1` writer - Boot Loader Protection Mode
4803 pub type BLB1_W<'a, REG> = crate::FieldWriter<'a, REG, 2, BLB1_A, crate::Safe>;
4804 impl<'a, REG> BLB1_W<'a, REG>
4805 where
4806 REG: crate::Writable + crate::RegisterSpec,
4807 REG::Ux: From<u8>,
4808 {
4809 ///LPM and SPM prohibited in Boot Section
4810 #[inline(always)]
4811 pub fn lpm_spm_disable(self) -> &'a mut crate::W<REG> {
4812 self.variant(BLB1_A::LPM_SPM_DISABLE)
4813 }
4814 ///LPM prohibited in Boot Section
4815 #[inline(always)]
4816 pub fn lpm_disable(self) -> &'a mut crate::W<REG> {
4817 self.variant(BLB1_A::LPM_DISABLE)
4818 }
4819 ///SPM prohibited in Boot Section
4820 #[inline(always)]
4821 pub fn spm_disable(self) -> &'a mut crate::W<REG> {
4822 self.variant(BLB1_A::SPM_DISABLE)
4823 }
4824 ///No lock on SPM and LPM in Boot Section
4825 #[inline(always)]
4826 pub fn no_lock(self) -> &'a mut crate::W<REG> {
4827 self.variant(BLB1_A::NO_LOCK)
4828 }
4829 }
4830 impl R {
4831 ///Bits 0:1 - Memory Lock
4832 #[inline(always)]
4833 pub fn lb(&self) -> LB_R {
4834 LB_R::new(self.bits & 3)
4835 }
4836 ///Bits 2:3 - Boot Loader Protection Mode
4837 #[inline(always)]
4838 pub fn blb0(&self) -> BLB0_R {
4839 BLB0_R::new((self.bits >> 2) & 3)
4840 }
4841 ///Bits 4:5 - Boot Loader Protection Mode
4842 #[inline(always)]
4843 pub fn blb1(&self) -> BLB1_R {
4844 BLB1_R::new((self.bits >> 4) & 3)
4845 }
4846 }
4847 impl W {
4848 ///Bits 0:1 - Memory Lock
4849 #[inline(always)]
4850 pub fn lb(&mut self) -> LB_W<'_, LOCKBIT_SPEC> {
4851 LB_W::new(self, 0)
4852 }
4853 ///Bits 2:3 - Boot Loader Protection Mode
4854 #[inline(always)]
4855 pub fn blb0(&mut self) -> BLB0_W<'_, LOCKBIT_SPEC> {
4856 BLB0_W::new(self, 2)
4857 }
4858 ///Bits 4:5 - Boot Loader Protection Mode
4859 #[inline(always)]
4860 pub fn blb1(&mut self) -> BLB1_W<'_, LOCKBIT_SPEC> {
4861 BLB1_W::new(self, 4)
4862 }
4863 }
4864 /**No Description.
4865
4866You can [`read`](crate::Reg::read) this register and get [`lockbit::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lockbit::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
4867 pub struct LOCKBIT_SPEC;
4868 impl crate::RegisterSpec for LOCKBIT_SPEC {
4869 type Ux = u8;
4870 }
4871 ///`read()` method returns [`lockbit::R`](R) reader structure
4872 impl crate::Readable for LOCKBIT_SPEC {}
4873 ///`write(|w| ..)` method takes [`lockbit::W`](W) writer structure
4874 impl crate::Writable for LOCKBIT_SPEC {
4875 type Safety = crate::Unsafe;
4876 }
4877 ///`reset()` method sets LOCKBIT to value 0
4878 impl crate::Resettable for LOCKBIT_SPEC {}
4879 }
4880}
4881///I/O Port
4882pub type PORTB = crate::Periph<portb::RegisterBlock, 0x23>;
4883impl core::fmt::Debug for PORTB {
4884 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
4885 f.debug_struct("PORTB").finish()
4886 }
4887}
4888///I/O Port
4889pub mod portb {
4890 #[repr(C)]
4891 ///Register block
4892 pub struct RegisterBlock {
4893 pinb: PINB,
4894 ddrb: DDRB,
4895 portb: PORTB,
4896 }
4897 impl RegisterBlock {
4898 ///0x00 - Port B Input Pins
4899 #[inline(always)]
4900 pub const fn pinb(&self) -> &PINB {
4901 &self.pinb
4902 }
4903 ///0x01 - Port B Data Direction Register
4904 #[inline(always)]
4905 pub const fn ddrb(&self) -> &DDRB {
4906 &self.ddrb
4907 }
4908 ///0x02 - Port B Data Register
4909 #[inline(always)]
4910 pub const fn portb(&self) -> &PORTB {
4911 &self.portb
4912 }
4913 }
4914 /**DDRB (rw) register accessor: Port B Data Direction Register
4915
4916You can [`read`](crate::Reg::read) this register and get [`ddrb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ddrb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
4917
4918For information about available fields see [`mod@ddrb`] module*/
4919 pub type DDRB = crate::Reg<ddrb::DDRB_SPEC>;
4920 ///Port B Data Direction Register
4921 pub mod ddrb {
4922 ///Register `DDRB` reader
4923 pub type R = crate::R<DDRB_SPEC>;
4924 ///Register `DDRB` writer
4925 pub type W = crate::W<DDRB_SPEC>;
4926 ///Field `PB0` reader - Pin B0
4927 pub type PB0_R = crate::BitReader;
4928 ///Field `PB0` writer - Pin B0
4929 pub type PB0_W<'a, REG> = crate::BitWriter<'a, REG>;
4930 ///Field `PB1` reader - Pin B1
4931 pub type PB1_R = crate::BitReader;
4932 ///Field `PB1` writer - Pin B1
4933 pub type PB1_W<'a, REG> = crate::BitWriter<'a, REG>;
4934 ///Field `PB2` reader - Pin B2
4935 pub type PB2_R = crate::BitReader;
4936 ///Field `PB2` writer - Pin B2
4937 pub type PB2_W<'a, REG> = crate::BitWriter<'a, REG>;
4938 ///Field `PB3` reader - Pin B3
4939 pub type PB3_R = crate::BitReader;
4940 ///Field `PB3` writer - Pin B3
4941 pub type PB3_W<'a, REG> = crate::BitWriter<'a, REG>;
4942 ///Field `PB4` reader - Pin B4
4943 pub type PB4_R = crate::BitReader;
4944 ///Field `PB4` writer - Pin B4
4945 pub type PB4_W<'a, REG> = crate::BitWriter<'a, REG>;
4946 ///Field `PB5` reader - Pin B5
4947 pub type PB5_R = crate::BitReader;
4948 ///Field `PB5` writer - Pin B5
4949 pub type PB5_W<'a, REG> = crate::BitWriter<'a, REG>;
4950 ///Field `PB6` reader - Pin B6
4951 pub type PB6_R = crate::BitReader;
4952 ///Field `PB6` writer - Pin B6
4953 pub type PB6_W<'a, REG> = crate::BitWriter<'a, REG>;
4954 ///Field `PB7` reader - Pin B7
4955 pub type PB7_R = crate::BitReader;
4956 ///Field `PB7` writer - Pin B7
4957 pub type PB7_W<'a, REG> = crate::BitWriter<'a, REG>;
4958 impl R {
4959 ///Bit 0 - Pin B0
4960 #[inline(always)]
4961 pub fn pb0(&self) -> PB0_R {
4962 PB0_R::new((self.bits & 1) != 0)
4963 }
4964 ///Bit 1 - Pin B1
4965 #[inline(always)]
4966 pub fn pb1(&self) -> PB1_R {
4967 PB1_R::new(((self.bits >> 1) & 1) != 0)
4968 }
4969 ///Bit 2 - Pin B2
4970 #[inline(always)]
4971 pub fn pb2(&self) -> PB2_R {
4972 PB2_R::new(((self.bits >> 2) & 1) != 0)
4973 }
4974 ///Bit 3 - Pin B3
4975 #[inline(always)]
4976 pub fn pb3(&self) -> PB3_R {
4977 PB3_R::new(((self.bits >> 3) & 1) != 0)
4978 }
4979 ///Bit 4 - Pin B4
4980 #[inline(always)]
4981 pub fn pb4(&self) -> PB4_R {
4982 PB4_R::new(((self.bits >> 4) & 1) != 0)
4983 }
4984 ///Bit 5 - Pin B5
4985 #[inline(always)]
4986 pub fn pb5(&self) -> PB5_R {
4987 PB5_R::new(((self.bits >> 5) & 1) != 0)
4988 }
4989 ///Bit 6 - Pin B6
4990 #[inline(always)]
4991 pub fn pb6(&self) -> PB6_R {
4992 PB6_R::new(((self.bits >> 6) & 1) != 0)
4993 }
4994 ///Bit 7 - Pin B7
4995 #[inline(always)]
4996 pub fn pb7(&self) -> PB7_R {
4997 PB7_R::new(((self.bits >> 7) & 1) != 0)
4998 }
4999 }
5000 impl W {
5001 ///Bit 0 - Pin B0
5002 #[inline(always)]
5003 pub fn pb0(&mut self) -> PB0_W<'_, DDRB_SPEC> {
5004 PB0_W::new(self, 0)
5005 }
5006 ///Bit 1 - Pin B1
5007 #[inline(always)]
5008 pub fn pb1(&mut self) -> PB1_W<'_, DDRB_SPEC> {
5009 PB1_W::new(self, 1)
5010 }
5011 ///Bit 2 - Pin B2
5012 #[inline(always)]
5013 pub fn pb2(&mut self) -> PB2_W<'_, DDRB_SPEC> {
5014 PB2_W::new(self, 2)
5015 }
5016 ///Bit 3 - Pin B3
5017 #[inline(always)]
5018 pub fn pb3(&mut self) -> PB3_W<'_, DDRB_SPEC> {
5019 PB3_W::new(self, 3)
5020 }
5021 ///Bit 4 - Pin B4
5022 #[inline(always)]
5023 pub fn pb4(&mut self) -> PB4_W<'_, DDRB_SPEC> {
5024 PB4_W::new(self, 4)
5025 }
5026 ///Bit 5 - Pin B5
5027 #[inline(always)]
5028 pub fn pb5(&mut self) -> PB5_W<'_, DDRB_SPEC> {
5029 PB5_W::new(self, 5)
5030 }
5031 ///Bit 6 - Pin B6
5032 #[inline(always)]
5033 pub fn pb6(&mut self) -> PB6_W<'_, DDRB_SPEC> {
5034 PB6_W::new(self, 6)
5035 }
5036 ///Bit 7 - Pin B7
5037 #[inline(always)]
5038 pub fn pb7(&mut self) -> PB7_W<'_, DDRB_SPEC> {
5039 PB7_W::new(self, 7)
5040 }
5041 }
5042 /**Port B Data Direction Register
5043
5044You can [`read`](crate::Reg::read) this register and get [`ddrb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ddrb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
5045 pub struct DDRB_SPEC;
5046 impl crate::RegisterSpec for DDRB_SPEC {
5047 type Ux = u8;
5048 }
5049 ///`read()` method returns [`ddrb::R`](R) reader structure
5050 impl crate::Readable for DDRB_SPEC {}
5051 ///`write(|w| ..)` method takes [`ddrb::W`](W) writer structure
5052 impl crate::Writable for DDRB_SPEC {
5053 type Safety = crate::Unsafe;
5054 }
5055 ///`reset()` method sets DDRB to value 0
5056 impl crate::Resettable for DDRB_SPEC {}
5057 }
5058 /**PINB (rw) register accessor: Port B Input Pins
5059
5060You can [`read`](crate::Reg::read) this register and get [`pinb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pinb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
5061
5062For information about available fields see [`mod@pinb`] module*/
5063 pub type PINB = crate::Reg<pinb::PINB_SPEC>;
5064 ///Port B Input Pins
5065 pub mod pinb {
5066 ///Register `PINB` reader
5067 pub type R = crate::R<PINB_SPEC>;
5068 ///Register `PINB` writer
5069 pub type W = crate::W<PINB_SPEC>;
5070 ///Field `PB0` reader - Pin B0
5071 pub type PB0_R = crate::BitReader;
5072 ///Field `PB0` writer - Pin B0
5073 pub type PB0_W<'a, REG> = crate::BitWriter<'a, REG>;
5074 ///Field `PB1` reader - Pin B1
5075 pub type PB1_R = crate::BitReader;
5076 ///Field `PB1` writer - Pin B1
5077 pub type PB1_W<'a, REG> = crate::BitWriter<'a, REG>;
5078 ///Field `PB2` reader - Pin B2
5079 pub type PB2_R = crate::BitReader;
5080 ///Field `PB2` writer - Pin B2
5081 pub type PB2_W<'a, REG> = crate::BitWriter<'a, REG>;
5082 ///Field `PB3` reader - Pin B3
5083 pub type PB3_R = crate::BitReader;
5084 ///Field `PB3` writer - Pin B3
5085 pub type PB3_W<'a, REG> = crate::BitWriter<'a, REG>;
5086 ///Field `PB4` reader - Pin B4
5087 pub type PB4_R = crate::BitReader;
5088 ///Field `PB4` writer - Pin B4
5089 pub type PB4_W<'a, REG> = crate::BitWriter<'a, REG>;
5090 ///Field `PB5` reader - Pin B5
5091 pub type PB5_R = crate::BitReader;
5092 ///Field `PB5` writer - Pin B5
5093 pub type PB5_W<'a, REG> = crate::BitWriter<'a, REG>;
5094 ///Field `PB6` reader - Pin B6
5095 pub type PB6_R = crate::BitReader;
5096 ///Field `PB6` writer - Pin B6
5097 pub type PB6_W<'a, REG> = crate::BitWriter<'a, REG>;
5098 ///Field `PB7` reader - Pin B7
5099 pub type PB7_R = crate::BitReader;
5100 ///Field `PB7` writer - Pin B7
5101 pub type PB7_W<'a, REG> = crate::BitWriter<'a, REG>;
5102 impl R {
5103 ///Bit 0 - Pin B0
5104 #[inline(always)]
5105 pub fn pb0(&self) -> PB0_R {
5106 PB0_R::new((self.bits & 1) != 0)
5107 }
5108 ///Bit 1 - Pin B1
5109 #[inline(always)]
5110 pub fn pb1(&self) -> PB1_R {
5111 PB1_R::new(((self.bits >> 1) & 1) != 0)
5112 }
5113 ///Bit 2 - Pin B2
5114 #[inline(always)]
5115 pub fn pb2(&self) -> PB2_R {
5116 PB2_R::new(((self.bits >> 2) & 1) != 0)
5117 }
5118 ///Bit 3 - Pin B3
5119 #[inline(always)]
5120 pub fn pb3(&self) -> PB3_R {
5121 PB3_R::new(((self.bits >> 3) & 1) != 0)
5122 }
5123 ///Bit 4 - Pin B4
5124 #[inline(always)]
5125 pub fn pb4(&self) -> PB4_R {
5126 PB4_R::new(((self.bits >> 4) & 1) != 0)
5127 }
5128 ///Bit 5 - Pin B5
5129 #[inline(always)]
5130 pub fn pb5(&self) -> PB5_R {
5131 PB5_R::new(((self.bits >> 5) & 1) != 0)
5132 }
5133 ///Bit 6 - Pin B6
5134 #[inline(always)]
5135 pub fn pb6(&self) -> PB6_R {
5136 PB6_R::new(((self.bits >> 6) & 1) != 0)
5137 }
5138 ///Bit 7 - Pin B7
5139 #[inline(always)]
5140 pub fn pb7(&self) -> PB7_R {
5141 PB7_R::new(((self.bits >> 7) & 1) != 0)
5142 }
5143 }
5144 impl W {
5145 ///Bit 0 - Pin B0
5146 #[inline(always)]
5147 pub fn pb0(&mut self) -> PB0_W<'_, PINB_SPEC> {
5148 PB0_W::new(self, 0)
5149 }
5150 ///Bit 1 - Pin B1
5151 #[inline(always)]
5152 pub fn pb1(&mut self) -> PB1_W<'_, PINB_SPEC> {
5153 PB1_W::new(self, 1)
5154 }
5155 ///Bit 2 - Pin B2
5156 #[inline(always)]
5157 pub fn pb2(&mut self) -> PB2_W<'_, PINB_SPEC> {
5158 PB2_W::new(self, 2)
5159 }
5160 ///Bit 3 - Pin B3
5161 #[inline(always)]
5162 pub fn pb3(&mut self) -> PB3_W<'_, PINB_SPEC> {
5163 PB3_W::new(self, 3)
5164 }
5165 ///Bit 4 - Pin B4
5166 #[inline(always)]
5167 pub fn pb4(&mut self) -> PB4_W<'_, PINB_SPEC> {
5168 PB4_W::new(self, 4)
5169 }
5170 ///Bit 5 - Pin B5
5171 #[inline(always)]
5172 pub fn pb5(&mut self) -> PB5_W<'_, PINB_SPEC> {
5173 PB5_W::new(self, 5)
5174 }
5175 ///Bit 6 - Pin B6
5176 #[inline(always)]
5177 pub fn pb6(&mut self) -> PB6_W<'_, PINB_SPEC> {
5178 PB6_W::new(self, 6)
5179 }
5180 ///Bit 7 - Pin B7
5181 #[inline(always)]
5182 pub fn pb7(&mut self) -> PB7_W<'_, PINB_SPEC> {
5183 PB7_W::new(self, 7)
5184 }
5185 }
5186 /**Port B Input Pins
5187
5188You can [`read`](crate::Reg::read) this register and get [`pinb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pinb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
5189 pub struct PINB_SPEC;
5190 impl crate::RegisterSpec for PINB_SPEC {
5191 type Ux = u8;
5192 }
5193 ///`read()` method returns [`pinb::R`](R) reader structure
5194 impl crate::Readable for PINB_SPEC {}
5195 ///`write(|w| ..)` method takes [`pinb::W`](W) writer structure
5196 impl crate::Writable for PINB_SPEC {
5197 type Safety = crate::Unsafe;
5198 }
5199 ///`reset()` method sets PINB to value 0
5200 impl crate::Resettable for PINB_SPEC {}
5201 }
5202 /**PORTB (rw) register accessor: Port B Data Register
5203
5204You can [`read`](crate::Reg::read) this register and get [`portb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`portb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
5205
5206For information about available fields see [`mod@portb`] module*/
5207 pub type PORTB = crate::Reg<portb::PORTB_SPEC>;
5208 ///Port B Data Register
5209 pub mod portb {
5210 ///Register `PORTB` reader
5211 pub type R = crate::R<PORTB_SPEC>;
5212 ///Register `PORTB` writer
5213 pub type W = crate::W<PORTB_SPEC>;
5214 ///Field `PB0` reader - Pin B0
5215 pub type PB0_R = crate::BitReader;
5216 ///Field `PB0` writer - Pin B0
5217 pub type PB0_W<'a, REG> = crate::BitWriter<'a, REG>;
5218 ///Field `PB1` reader - Pin B1
5219 pub type PB1_R = crate::BitReader;
5220 ///Field `PB1` writer - Pin B1
5221 pub type PB1_W<'a, REG> = crate::BitWriter<'a, REG>;
5222 ///Field `PB2` reader - Pin B2
5223 pub type PB2_R = crate::BitReader;
5224 ///Field `PB2` writer - Pin B2
5225 pub type PB2_W<'a, REG> = crate::BitWriter<'a, REG>;
5226 ///Field `PB3` reader - Pin B3
5227 pub type PB3_R = crate::BitReader;
5228 ///Field `PB3` writer - Pin B3
5229 pub type PB3_W<'a, REG> = crate::BitWriter<'a, REG>;
5230 ///Field `PB4` reader - Pin B4
5231 pub type PB4_R = crate::BitReader;
5232 ///Field `PB4` writer - Pin B4
5233 pub type PB4_W<'a, REG> = crate::BitWriter<'a, REG>;
5234 ///Field `PB5` reader - Pin B5
5235 pub type PB5_R = crate::BitReader;
5236 ///Field `PB5` writer - Pin B5
5237 pub type PB5_W<'a, REG> = crate::BitWriter<'a, REG>;
5238 ///Field `PB6` reader - Pin B6
5239 pub type PB6_R = crate::BitReader;
5240 ///Field `PB6` writer - Pin B6
5241 pub type PB6_W<'a, REG> = crate::BitWriter<'a, REG>;
5242 ///Field `PB7` reader - Pin B7
5243 pub type PB7_R = crate::BitReader;
5244 ///Field `PB7` writer - Pin B7
5245 pub type PB7_W<'a, REG> = crate::BitWriter<'a, REG>;
5246 impl R {
5247 ///Bit 0 - Pin B0
5248 #[inline(always)]
5249 pub fn pb0(&self) -> PB0_R {
5250 PB0_R::new((self.bits & 1) != 0)
5251 }
5252 ///Bit 1 - Pin B1
5253 #[inline(always)]
5254 pub fn pb1(&self) -> PB1_R {
5255 PB1_R::new(((self.bits >> 1) & 1) != 0)
5256 }
5257 ///Bit 2 - Pin B2
5258 #[inline(always)]
5259 pub fn pb2(&self) -> PB2_R {
5260 PB2_R::new(((self.bits >> 2) & 1) != 0)
5261 }
5262 ///Bit 3 - Pin B3
5263 #[inline(always)]
5264 pub fn pb3(&self) -> PB3_R {
5265 PB3_R::new(((self.bits >> 3) & 1) != 0)
5266 }
5267 ///Bit 4 - Pin B4
5268 #[inline(always)]
5269 pub fn pb4(&self) -> PB4_R {
5270 PB4_R::new(((self.bits >> 4) & 1) != 0)
5271 }
5272 ///Bit 5 - Pin B5
5273 #[inline(always)]
5274 pub fn pb5(&self) -> PB5_R {
5275 PB5_R::new(((self.bits >> 5) & 1) != 0)
5276 }
5277 ///Bit 6 - Pin B6
5278 #[inline(always)]
5279 pub fn pb6(&self) -> PB6_R {
5280 PB6_R::new(((self.bits >> 6) & 1) != 0)
5281 }
5282 ///Bit 7 - Pin B7
5283 #[inline(always)]
5284 pub fn pb7(&self) -> PB7_R {
5285 PB7_R::new(((self.bits >> 7) & 1) != 0)
5286 }
5287 }
5288 impl W {
5289 ///Bit 0 - Pin B0
5290 #[inline(always)]
5291 pub fn pb0(&mut self) -> PB0_W<'_, PORTB_SPEC> {
5292 PB0_W::new(self, 0)
5293 }
5294 ///Bit 1 - Pin B1
5295 #[inline(always)]
5296 pub fn pb1(&mut self) -> PB1_W<'_, PORTB_SPEC> {
5297 PB1_W::new(self, 1)
5298 }
5299 ///Bit 2 - Pin B2
5300 #[inline(always)]
5301 pub fn pb2(&mut self) -> PB2_W<'_, PORTB_SPEC> {
5302 PB2_W::new(self, 2)
5303 }
5304 ///Bit 3 - Pin B3
5305 #[inline(always)]
5306 pub fn pb3(&mut self) -> PB3_W<'_, PORTB_SPEC> {
5307 PB3_W::new(self, 3)
5308 }
5309 ///Bit 4 - Pin B4
5310 #[inline(always)]
5311 pub fn pb4(&mut self) -> PB4_W<'_, PORTB_SPEC> {
5312 PB4_W::new(self, 4)
5313 }
5314 ///Bit 5 - Pin B5
5315 #[inline(always)]
5316 pub fn pb5(&mut self) -> PB5_W<'_, PORTB_SPEC> {
5317 PB5_W::new(self, 5)
5318 }
5319 ///Bit 6 - Pin B6
5320 #[inline(always)]
5321 pub fn pb6(&mut self) -> PB6_W<'_, PORTB_SPEC> {
5322 PB6_W::new(self, 6)
5323 }
5324 ///Bit 7 - Pin B7
5325 #[inline(always)]
5326 pub fn pb7(&mut self) -> PB7_W<'_, PORTB_SPEC> {
5327 PB7_W::new(self, 7)
5328 }
5329 }
5330 /**Port B Data Register
5331
5332You can [`read`](crate::Reg::read) this register and get [`portb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`portb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
5333 pub struct PORTB_SPEC;
5334 impl crate::RegisterSpec for PORTB_SPEC {
5335 type Ux = u8;
5336 }
5337 ///`read()` method returns [`portb::R`](R) reader structure
5338 impl crate::Readable for PORTB_SPEC {}
5339 ///`write(|w| ..)` method takes [`portb::W`](W) writer structure
5340 impl crate::Writable for PORTB_SPEC {
5341 type Safety = crate::Unsafe;
5342 }
5343 ///`reset()` method sets PORTB to value 0
5344 impl crate::Resettable for PORTB_SPEC {}
5345 }
5346}
5347///I/O Port
5348pub type PORTC = crate::Periph<portc::RegisterBlock, 0x26>;
5349impl core::fmt::Debug for PORTC {
5350 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
5351 f.debug_struct("PORTC").finish()
5352 }
5353}
5354///I/O Port
5355pub mod portc {
5356 #[repr(C)]
5357 ///Register block
5358 pub struct RegisterBlock {
5359 pinc: PINC,
5360 ddrc: DDRC,
5361 portc: PORTC,
5362 }
5363 impl RegisterBlock {
5364 ///0x00 - Port C Input Pins
5365 #[inline(always)]
5366 pub const fn pinc(&self) -> &PINC {
5367 &self.pinc
5368 }
5369 ///0x01 - Port C Data Direction Register
5370 #[inline(always)]
5371 pub const fn ddrc(&self) -> &DDRC {
5372 &self.ddrc
5373 }
5374 ///0x02 - Port C Data Register
5375 #[inline(always)]
5376 pub const fn portc(&self) -> &PORTC {
5377 &self.portc
5378 }
5379 }
5380 /**DDRC (rw) register accessor: Port C Data Direction Register
5381
5382You can [`read`](crate::Reg::read) this register and get [`ddrc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ddrc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
5383
5384For information about available fields see [`mod@ddrc`] module*/
5385 pub type DDRC = crate::Reg<ddrc::DDRC_SPEC>;
5386 ///Port C Data Direction Register
5387 pub mod ddrc {
5388 ///Register `DDRC` reader
5389 pub type R = crate::R<DDRC_SPEC>;
5390 ///Register `DDRC` writer
5391 pub type W = crate::W<DDRC_SPEC>;
5392 ///Field `PC0` reader - Pin C0
5393 pub type PC0_R = crate::BitReader;
5394 ///Field `PC0` writer - Pin C0
5395 pub type PC0_W<'a, REG> = crate::BitWriter<'a, REG>;
5396 ///Field `PC1` reader - Pin C1
5397 pub type PC1_R = crate::BitReader;
5398 ///Field `PC1` writer - Pin C1
5399 pub type PC1_W<'a, REG> = crate::BitWriter<'a, REG>;
5400 ///Field `PC2` reader - Pin C2
5401 pub type PC2_R = crate::BitReader;
5402 ///Field `PC2` writer - Pin C2
5403 pub type PC2_W<'a, REG> = crate::BitWriter<'a, REG>;
5404 ///Field `PC3` reader - Pin C3
5405 pub type PC3_R = crate::BitReader;
5406 ///Field `PC3` writer - Pin C3
5407 pub type PC3_W<'a, REG> = crate::BitWriter<'a, REG>;
5408 ///Field `PC4` reader - Pin C4
5409 pub type PC4_R = crate::BitReader;
5410 ///Field `PC4` writer - Pin C4
5411 pub type PC4_W<'a, REG> = crate::BitWriter<'a, REG>;
5412 ///Field `PC5` reader - Pin C5
5413 pub type PC5_R = crate::BitReader;
5414 ///Field `PC5` writer - Pin C5
5415 pub type PC5_W<'a, REG> = crate::BitWriter<'a, REG>;
5416 ///Field `PC6` reader - Pin C6
5417 pub type PC6_R = crate::BitReader;
5418 ///Field `PC6` writer - Pin C6
5419 pub type PC6_W<'a, REG> = crate::BitWriter<'a, REG>;
5420 impl R {
5421 ///Bit 0 - Pin C0
5422 #[inline(always)]
5423 pub fn pc0(&self) -> PC0_R {
5424 PC0_R::new((self.bits & 1) != 0)
5425 }
5426 ///Bit 1 - Pin C1
5427 #[inline(always)]
5428 pub fn pc1(&self) -> PC1_R {
5429 PC1_R::new(((self.bits >> 1) & 1) != 0)
5430 }
5431 ///Bit 2 - Pin C2
5432 #[inline(always)]
5433 pub fn pc2(&self) -> PC2_R {
5434 PC2_R::new(((self.bits >> 2) & 1) != 0)
5435 }
5436 ///Bit 3 - Pin C3
5437 #[inline(always)]
5438 pub fn pc3(&self) -> PC3_R {
5439 PC3_R::new(((self.bits >> 3) & 1) != 0)
5440 }
5441 ///Bit 4 - Pin C4
5442 #[inline(always)]
5443 pub fn pc4(&self) -> PC4_R {
5444 PC4_R::new(((self.bits >> 4) & 1) != 0)
5445 }
5446 ///Bit 5 - Pin C5
5447 #[inline(always)]
5448 pub fn pc5(&self) -> PC5_R {
5449 PC5_R::new(((self.bits >> 5) & 1) != 0)
5450 }
5451 ///Bit 6 - Pin C6
5452 #[inline(always)]
5453 pub fn pc6(&self) -> PC6_R {
5454 PC6_R::new(((self.bits >> 6) & 1) != 0)
5455 }
5456 }
5457 impl W {
5458 ///Bit 0 - Pin C0
5459 #[inline(always)]
5460 pub fn pc0(&mut self) -> PC0_W<'_, DDRC_SPEC> {
5461 PC0_W::new(self, 0)
5462 }
5463 ///Bit 1 - Pin C1
5464 #[inline(always)]
5465 pub fn pc1(&mut self) -> PC1_W<'_, DDRC_SPEC> {
5466 PC1_W::new(self, 1)
5467 }
5468 ///Bit 2 - Pin C2
5469 #[inline(always)]
5470 pub fn pc2(&mut self) -> PC2_W<'_, DDRC_SPEC> {
5471 PC2_W::new(self, 2)
5472 }
5473 ///Bit 3 - Pin C3
5474 #[inline(always)]
5475 pub fn pc3(&mut self) -> PC3_W<'_, DDRC_SPEC> {
5476 PC3_W::new(self, 3)
5477 }
5478 ///Bit 4 - Pin C4
5479 #[inline(always)]
5480 pub fn pc4(&mut self) -> PC4_W<'_, DDRC_SPEC> {
5481 PC4_W::new(self, 4)
5482 }
5483 ///Bit 5 - Pin C5
5484 #[inline(always)]
5485 pub fn pc5(&mut self) -> PC5_W<'_, DDRC_SPEC> {
5486 PC5_W::new(self, 5)
5487 }
5488 ///Bit 6 - Pin C6
5489 #[inline(always)]
5490 pub fn pc6(&mut self) -> PC6_W<'_, DDRC_SPEC> {
5491 PC6_W::new(self, 6)
5492 }
5493 }
5494 /**Port C Data Direction Register
5495
5496You can [`read`](crate::Reg::read) this register and get [`ddrc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ddrc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
5497 pub struct DDRC_SPEC;
5498 impl crate::RegisterSpec for DDRC_SPEC {
5499 type Ux = u8;
5500 }
5501 ///`read()` method returns [`ddrc::R`](R) reader structure
5502 impl crate::Readable for DDRC_SPEC {}
5503 ///`write(|w| ..)` method takes [`ddrc::W`](W) writer structure
5504 impl crate::Writable for DDRC_SPEC {
5505 type Safety = crate::Unsafe;
5506 }
5507 ///`reset()` method sets DDRC to value 0
5508 impl crate::Resettable for DDRC_SPEC {}
5509 }
5510 /**PINC (rw) register accessor: Port C Input Pins
5511
5512You can [`read`](crate::Reg::read) this register and get [`pinc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pinc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
5513
5514For information about available fields see [`mod@pinc`] module*/
5515 pub type PINC = crate::Reg<pinc::PINC_SPEC>;
5516 ///Port C Input Pins
5517 pub mod pinc {
5518 ///Register `PINC` reader
5519 pub type R = crate::R<PINC_SPEC>;
5520 ///Register `PINC` writer
5521 pub type W = crate::W<PINC_SPEC>;
5522 ///Field `PC0` reader - Pin C0
5523 pub type PC0_R = crate::BitReader;
5524 ///Field `PC0` writer - Pin C0
5525 pub type PC0_W<'a, REG> = crate::BitWriter<'a, REG>;
5526 ///Field `PC1` reader - Pin C1
5527 pub type PC1_R = crate::BitReader;
5528 ///Field `PC1` writer - Pin C1
5529 pub type PC1_W<'a, REG> = crate::BitWriter<'a, REG>;
5530 ///Field `PC2` reader - Pin C2
5531 pub type PC2_R = crate::BitReader;
5532 ///Field `PC2` writer - Pin C2
5533 pub type PC2_W<'a, REG> = crate::BitWriter<'a, REG>;
5534 ///Field `PC3` reader - Pin C3
5535 pub type PC3_R = crate::BitReader;
5536 ///Field `PC3` writer - Pin C3
5537 pub type PC3_W<'a, REG> = crate::BitWriter<'a, REG>;
5538 ///Field `PC4` reader - Pin C4
5539 pub type PC4_R = crate::BitReader;
5540 ///Field `PC4` writer - Pin C4
5541 pub type PC4_W<'a, REG> = crate::BitWriter<'a, REG>;
5542 ///Field `PC5` reader - Pin C5
5543 pub type PC5_R = crate::BitReader;
5544 ///Field `PC5` writer - Pin C5
5545 pub type PC5_W<'a, REG> = crate::BitWriter<'a, REG>;
5546 ///Field `PC6` reader - Pin C6
5547 pub type PC6_R = crate::BitReader;
5548 ///Field `PC6` writer - Pin C6
5549 pub type PC6_W<'a, REG> = crate::BitWriter<'a, REG>;
5550 impl R {
5551 ///Bit 0 - Pin C0
5552 #[inline(always)]
5553 pub fn pc0(&self) -> PC0_R {
5554 PC0_R::new((self.bits & 1) != 0)
5555 }
5556 ///Bit 1 - Pin C1
5557 #[inline(always)]
5558 pub fn pc1(&self) -> PC1_R {
5559 PC1_R::new(((self.bits >> 1) & 1) != 0)
5560 }
5561 ///Bit 2 - Pin C2
5562 #[inline(always)]
5563 pub fn pc2(&self) -> PC2_R {
5564 PC2_R::new(((self.bits >> 2) & 1) != 0)
5565 }
5566 ///Bit 3 - Pin C3
5567 #[inline(always)]
5568 pub fn pc3(&self) -> PC3_R {
5569 PC3_R::new(((self.bits >> 3) & 1) != 0)
5570 }
5571 ///Bit 4 - Pin C4
5572 #[inline(always)]
5573 pub fn pc4(&self) -> PC4_R {
5574 PC4_R::new(((self.bits >> 4) & 1) != 0)
5575 }
5576 ///Bit 5 - Pin C5
5577 #[inline(always)]
5578 pub fn pc5(&self) -> PC5_R {
5579 PC5_R::new(((self.bits >> 5) & 1) != 0)
5580 }
5581 ///Bit 6 - Pin C6
5582 #[inline(always)]
5583 pub fn pc6(&self) -> PC6_R {
5584 PC6_R::new(((self.bits >> 6) & 1) != 0)
5585 }
5586 }
5587 impl W {
5588 ///Bit 0 - Pin C0
5589 #[inline(always)]
5590 pub fn pc0(&mut self) -> PC0_W<'_, PINC_SPEC> {
5591 PC0_W::new(self, 0)
5592 }
5593 ///Bit 1 - Pin C1
5594 #[inline(always)]
5595 pub fn pc1(&mut self) -> PC1_W<'_, PINC_SPEC> {
5596 PC1_W::new(self, 1)
5597 }
5598 ///Bit 2 - Pin C2
5599 #[inline(always)]
5600 pub fn pc2(&mut self) -> PC2_W<'_, PINC_SPEC> {
5601 PC2_W::new(self, 2)
5602 }
5603 ///Bit 3 - Pin C3
5604 #[inline(always)]
5605 pub fn pc3(&mut self) -> PC3_W<'_, PINC_SPEC> {
5606 PC3_W::new(self, 3)
5607 }
5608 ///Bit 4 - Pin C4
5609 #[inline(always)]
5610 pub fn pc4(&mut self) -> PC4_W<'_, PINC_SPEC> {
5611 PC4_W::new(self, 4)
5612 }
5613 ///Bit 5 - Pin C5
5614 #[inline(always)]
5615 pub fn pc5(&mut self) -> PC5_W<'_, PINC_SPEC> {
5616 PC5_W::new(self, 5)
5617 }
5618 ///Bit 6 - Pin C6
5619 #[inline(always)]
5620 pub fn pc6(&mut self) -> PC6_W<'_, PINC_SPEC> {
5621 PC6_W::new(self, 6)
5622 }
5623 }
5624 /**Port C Input Pins
5625
5626You can [`read`](crate::Reg::read) this register and get [`pinc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pinc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
5627 pub struct PINC_SPEC;
5628 impl crate::RegisterSpec for PINC_SPEC {
5629 type Ux = u8;
5630 }
5631 ///`read()` method returns [`pinc::R`](R) reader structure
5632 impl crate::Readable for PINC_SPEC {}
5633 ///`write(|w| ..)` method takes [`pinc::W`](W) writer structure
5634 impl crate::Writable for PINC_SPEC {
5635 type Safety = crate::Unsafe;
5636 }
5637 ///`reset()` method sets PINC to value 0
5638 impl crate::Resettable for PINC_SPEC {}
5639 }
5640 /**PORTC (rw) register accessor: Port C Data Register
5641
5642You can [`read`](crate::Reg::read) this register and get [`portc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`portc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
5643
5644For information about available fields see [`mod@portc`] module*/
5645 pub type PORTC = crate::Reg<portc::PORTC_SPEC>;
5646 ///Port C Data Register
5647 pub mod portc {
5648 ///Register `PORTC` reader
5649 pub type R = crate::R<PORTC_SPEC>;
5650 ///Register `PORTC` writer
5651 pub type W = crate::W<PORTC_SPEC>;
5652 ///Field `PC0` reader - Pin C0
5653 pub type PC0_R = crate::BitReader;
5654 ///Field `PC0` writer - Pin C0
5655 pub type PC0_W<'a, REG> = crate::BitWriter<'a, REG>;
5656 ///Field `PC1` reader - Pin C1
5657 pub type PC1_R = crate::BitReader;
5658 ///Field `PC1` writer - Pin C1
5659 pub type PC1_W<'a, REG> = crate::BitWriter<'a, REG>;
5660 ///Field `PC2` reader - Pin C2
5661 pub type PC2_R = crate::BitReader;
5662 ///Field `PC2` writer - Pin C2
5663 pub type PC2_W<'a, REG> = crate::BitWriter<'a, REG>;
5664 ///Field `PC3` reader - Pin C3
5665 pub type PC3_R = crate::BitReader;
5666 ///Field `PC3` writer - Pin C3
5667 pub type PC3_W<'a, REG> = crate::BitWriter<'a, REG>;
5668 ///Field `PC4` reader - Pin C4
5669 pub type PC4_R = crate::BitReader;
5670 ///Field `PC4` writer - Pin C4
5671 pub type PC4_W<'a, REG> = crate::BitWriter<'a, REG>;
5672 ///Field `PC5` reader - Pin C5
5673 pub type PC5_R = crate::BitReader;
5674 ///Field `PC5` writer - Pin C5
5675 pub type PC5_W<'a, REG> = crate::BitWriter<'a, REG>;
5676 ///Field `PC6` reader - Pin C6
5677 pub type PC6_R = crate::BitReader;
5678 ///Field `PC6` writer - Pin C6
5679 pub type PC6_W<'a, REG> = crate::BitWriter<'a, REG>;
5680 impl R {
5681 ///Bit 0 - Pin C0
5682 #[inline(always)]
5683 pub fn pc0(&self) -> PC0_R {
5684 PC0_R::new((self.bits & 1) != 0)
5685 }
5686 ///Bit 1 - Pin C1
5687 #[inline(always)]
5688 pub fn pc1(&self) -> PC1_R {
5689 PC1_R::new(((self.bits >> 1) & 1) != 0)
5690 }
5691 ///Bit 2 - Pin C2
5692 #[inline(always)]
5693 pub fn pc2(&self) -> PC2_R {
5694 PC2_R::new(((self.bits >> 2) & 1) != 0)
5695 }
5696 ///Bit 3 - Pin C3
5697 #[inline(always)]
5698 pub fn pc3(&self) -> PC3_R {
5699 PC3_R::new(((self.bits >> 3) & 1) != 0)
5700 }
5701 ///Bit 4 - Pin C4
5702 #[inline(always)]
5703 pub fn pc4(&self) -> PC4_R {
5704 PC4_R::new(((self.bits >> 4) & 1) != 0)
5705 }
5706 ///Bit 5 - Pin C5
5707 #[inline(always)]
5708 pub fn pc5(&self) -> PC5_R {
5709 PC5_R::new(((self.bits >> 5) & 1) != 0)
5710 }
5711 ///Bit 6 - Pin C6
5712 #[inline(always)]
5713 pub fn pc6(&self) -> PC6_R {
5714 PC6_R::new(((self.bits >> 6) & 1) != 0)
5715 }
5716 }
5717 impl W {
5718 ///Bit 0 - Pin C0
5719 #[inline(always)]
5720 pub fn pc0(&mut self) -> PC0_W<'_, PORTC_SPEC> {
5721 PC0_W::new(self, 0)
5722 }
5723 ///Bit 1 - Pin C1
5724 #[inline(always)]
5725 pub fn pc1(&mut self) -> PC1_W<'_, PORTC_SPEC> {
5726 PC1_W::new(self, 1)
5727 }
5728 ///Bit 2 - Pin C2
5729 #[inline(always)]
5730 pub fn pc2(&mut self) -> PC2_W<'_, PORTC_SPEC> {
5731 PC2_W::new(self, 2)
5732 }
5733 ///Bit 3 - Pin C3
5734 #[inline(always)]
5735 pub fn pc3(&mut self) -> PC3_W<'_, PORTC_SPEC> {
5736 PC3_W::new(self, 3)
5737 }
5738 ///Bit 4 - Pin C4
5739 #[inline(always)]
5740 pub fn pc4(&mut self) -> PC4_W<'_, PORTC_SPEC> {
5741 PC4_W::new(self, 4)
5742 }
5743 ///Bit 5 - Pin C5
5744 #[inline(always)]
5745 pub fn pc5(&mut self) -> PC5_W<'_, PORTC_SPEC> {
5746 PC5_W::new(self, 5)
5747 }
5748 ///Bit 6 - Pin C6
5749 #[inline(always)]
5750 pub fn pc6(&mut self) -> PC6_W<'_, PORTC_SPEC> {
5751 PC6_W::new(self, 6)
5752 }
5753 }
5754 /**Port C Data Register
5755
5756You can [`read`](crate::Reg::read) this register and get [`portc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`portc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
5757 pub struct PORTC_SPEC;
5758 impl crate::RegisterSpec for PORTC_SPEC {
5759 type Ux = u8;
5760 }
5761 ///`read()` method returns [`portc::R`](R) reader structure
5762 impl crate::Readable for PORTC_SPEC {}
5763 ///`write(|w| ..)` method takes [`portc::W`](W) writer structure
5764 impl crate::Writable for PORTC_SPEC {
5765 type Safety = crate::Unsafe;
5766 }
5767 ///`reset()` method sets PORTC to value 0
5768 impl crate::Resettable for PORTC_SPEC {}
5769 }
5770}
5771///I/O Port
5772pub type PORTD = crate::Periph<portd::RegisterBlock, 0x29>;
5773impl core::fmt::Debug for PORTD {
5774 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
5775 f.debug_struct("PORTD").finish()
5776 }
5777}
5778///I/O Port
5779pub mod portd {
5780 #[repr(C)]
5781 ///Register block
5782 pub struct RegisterBlock {
5783 pind: PIND,
5784 ddrd: DDRD,
5785 portd: PORTD,
5786 }
5787 impl RegisterBlock {
5788 ///0x00 - Port D Input Pins
5789 #[inline(always)]
5790 pub const fn pind(&self) -> &PIND {
5791 &self.pind
5792 }
5793 ///0x01 - Port D Data Direction Register
5794 #[inline(always)]
5795 pub const fn ddrd(&self) -> &DDRD {
5796 &self.ddrd
5797 }
5798 ///0x02 - Port D Data Register
5799 #[inline(always)]
5800 pub const fn portd(&self) -> &PORTD {
5801 &self.portd
5802 }
5803 }
5804 /**DDRD (rw) register accessor: Port D Data Direction Register
5805
5806You can [`read`](crate::Reg::read) this register and get [`ddrd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ddrd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
5807
5808For information about available fields see [`mod@ddrd`] module*/
5809 pub type DDRD = crate::Reg<ddrd::DDRD_SPEC>;
5810 ///Port D Data Direction Register
5811 pub mod ddrd {
5812 ///Register `DDRD` reader
5813 pub type R = crate::R<DDRD_SPEC>;
5814 ///Register `DDRD` writer
5815 pub type W = crate::W<DDRD_SPEC>;
5816 ///Field `PD0` reader - Pin D0
5817 pub type PD0_R = crate::BitReader;
5818 ///Field `PD0` writer - Pin D0
5819 pub type PD0_W<'a, REG> = crate::BitWriter<'a, REG>;
5820 ///Field `PD1` reader - Pin D1
5821 pub type PD1_R = crate::BitReader;
5822 ///Field `PD1` writer - Pin D1
5823 pub type PD1_W<'a, REG> = crate::BitWriter<'a, REG>;
5824 ///Field `PD2` reader - Pin D2
5825 pub type PD2_R = crate::BitReader;
5826 ///Field `PD2` writer - Pin D2
5827 pub type PD2_W<'a, REG> = crate::BitWriter<'a, REG>;
5828 ///Field `PD3` reader - Pin D3
5829 pub type PD3_R = crate::BitReader;
5830 ///Field `PD3` writer - Pin D3
5831 pub type PD3_W<'a, REG> = crate::BitWriter<'a, REG>;
5832 ///Field `PD4` reader - Pin D4
5833 pub type PD4_R = crate::BitReader;
5834 ///Field `PD4` writer - Pin D4
5835 pub type PD4_W<'a, REG> = crate::BitWriter<'a, REG>;
5836 ///Field `PD5` reader - Pin D5
5837 pub type PD5_R = crate::BitReader;
5838 ///Field `PD5` writer - Pin D5
5839 pub type PD5_W<'a, REG> = crate::BitWriter<'a, REG>;
5840 ///Field `PD6` reader - Pin D6
5841 pub type PD6_R = crate::BitReader;
5842 ///Field `PD6` writer - Pin D6
5843 pub type PD6_W<'a, REG> = crate::BitWriter<'a, REG>;
5844 ///Field `PD7` reader - Pin D7
5845 pub type PD7_R = crate::BitReader;
5846 ///Field `PD7` writer - Pin D7
5847 pub type PD7_W<'a, REG> = crate::BitWriter<'a, REG>;
5848 impl R {
5849 ///Bit 0 - Pin D0
5850 #[inline(always)]
5851 pub fn pd0(&self) -> PD0_R {
5852 PD0_R::new((self.bits & 1) != 0)
5853 }
5854 ///Bit 1 - Pin D1
5855 #[inline(always)]
5856 pub fn pd1(&self) -> PD1_R {
5857 PD1_R::new(((self.bits >> 1) & 1) != 0)
5858 }
5859 ///Bit 2 - Pin D2
5860 #[inline(always)]
5861 pub fn pd2(&self) -> PD2_R {
5862 PD2_R::new(((self.bits >> 2) & 1) != 0)
5863 }
5864 ///Bit 3 - Pin D3
5865 #[inline(always)]
5866 pub fn pd3(&self) -> PD3_R {
5867 PD3_R::new(((self.bits >> 3) & 1) != 0)
5868 }
5869 ///Bit 4 - Pin D4
5870 #[inline(always)]
5871 pub fn pd4(&self) -> PD4_R {
5872 PD4_R::new(((self.bits >> 4) & 1) != 0)
5873 }
5874 ///Bit 5 - Pin D5
5875 #[inline(always)]
5876 pub fn pd5(&self) -> PD5_R {
5877 PD5_R::new(((self.bits >> 5) & 1) != 0)
5878 }
5879 ///Bit 6 - Pin D6
5880 #[inline(always)]
5881 pub fn pd6(&self) -> PD6_R {
5882 PD6_R::new(((self.bits >> 6) & 1) != 0)
5883 }
5884 ///Bit 7 - Pin D7
5885 #[inline(always)]
5886 pub fn pd7(&self) -> PD7_R {
5887 PD7_R::new(((self.bits >> 7) & 1) != 0)
5888 }
5889 }
5890 impl W {
5891 ///Bit 0 - Pin D0
5892 #[inline(always)]
5893 pub fn pd0(&mut self) -> PD0_W<'_, DDRD_SPEC> {
5894 PD0_W::new(self, 0)
5895 }
5896 ///Bit 1 - Pin D1
5897 #[inline(always)]
5898 pub fn pd1(&mut self) -> PD1_W<'_, DDRD_SPEC> {
5899 PD1_W::new(self, 1)
5900 }
5901 ///Bit 2 - Pin D2
5902 #[inline(always)]
5903 pub fn pd2(&mut self) -> PD2_W<'_, DDRD_SPEC> {
5904 PD2_W::new(self, 2)
5905 }
5906 ///Bit 3 - Pin D3
5907 #[inline(always)]
5908 pub fn pd3(&mut self) -> PD3_W<'_, DDRD_SPEC> {
5909 PD3_W::new(self, 3)
5910 }
5911 ///Bit 4 - Pin D4
5912 #[inline(always)]
5913 pub fn pd4(&mut self) -> PD4_W<'_, DDRD_SPEC> {
5914 PD4_W::new(self, 4)
5915 }
5916 ///Bit 5 - Pin D5
5917 #[inline(always)]
5918 pub fn pd5(&mut self) -> PD5_W<'_, DDRD_SPEC> {
5919 PD5_W::new(self, 5)
5920 }
5921 ///Bit 6 - Pin D6
5922 #[inline(always)]
5923 pub fn pd6(&mut self) -> PD6_W<'_, DDRD_SPEC> {
5924 PD6_W::new(self, 6)
5925 }
5926 ///Bit 7 - Pin D7
5927 #[inline(always)]
5928 pub fn pd7(&mut self) -> PD7_W<'_, DDRD_SPEC> {
5929 PD7_W::new(self, 7)
5930 }
5931 }
5932 /**Port D Data Direction Register
5933
5934You can [`read`](crate::Reg::read) this register and get [`ddrd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ddrd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
5935 pub struct DDRD_SPEC;
5936 impl crate::RegisterSpec for DDRD_SPEC {
5937 type Ux = u8;
5938 }
5939 ///`read()` method returns [`ddrd::R`](R) reader structure
5940 impl crate::Readable for DDRD_SPEC {}
5941 ///`write(|w| ..)` method takes [`ddrd::W`](W) writer structure
5942 impl crate::Writable for DDRD_SPEC {
5943 type Safety = crate::Unsafe;
5944 }
5945 ///`reset()` method sets DDRD to value 0
5946 impl crate::Resettable for DDRD_SPEC {}
5947 }
5948 /**PIND (rw) register accessor: Port D Input Pins
5949
5950You can [`read`](crate::Reg::read) this register and get [`pind::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pind::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
5951
5952For information about available fields see [`mod@pind`] module*/
5953 pub type PIND = crate::Reg<pind::PIND_SPEC>;
5954 ///Port D Input Pins
5955 pub mod pind {
5956 ///Register `PIND` reader
5957 pub type R = crate::R<PIND_SPEC>;
5958 ///Register `PIND` writer
5959 pub type W = crate::W<PIND_SPEC>;
5960 ///Field `PD0` reader - Pin D0
5961 pub type PD0_R = crate::BitReader;
5962 ///Field `PD0` writer - Pin D0
5963 pub type PD0_W<'a, REG> = crate::BitWriter<'a, REG>;
5964 ///Field `PD1` reader - Pin D1
5965 pub type PD1_R = crate::BitReader;
5966 ///Field `PD1` writer - Pin D1
5967 pub type PD1_W<'a, REG> = crate::BitWriter<'a, REG>;
5968 ///Field `PD2` reader - Pin D2
5969 pub type PD2_R = crate::BitReader;
5970 ///Field `PD2` writer - Pin D2
5971 pub type PD2_W<'a, REG> = crate::BitWriter<'a, REG>;
5972 ///Field `PD3` reader - Pin D3
5973 pub type PD3_R = crate::BitReader;
5974 ///Field `PD3` writer - Pin D3
5975 pub type PD3_W<'a, REG> = crate::BitWriter<'a, REG>;
5976 ///Field `PD4` reader - Pin D4
5977 pub type PD4_R = crate::BitReader;
5978 ///Field `PD4` writer - Pin D4
5979 pub type PD4_W<'a, REG> = crate::BitWriter<'a, REG>;
5980 ///Field `PD5` reader - Pin D5
5981 pub type PD5_R = crate::BitReader;
5982 ///Field `PD5` writer - Pin D5
5983 pub type PD5_W<'a, REG> = crate::BitWriter<'a, REG>;
5984 ///Field `PD6` reader - Pin D6
5985 pub type PD6_R = crate::BitReader;
5986 ///Field `PD6` writer - Pin D6
5987 pub type PD6_W<'a, REG> = crate::BitWriter<'a, REG>;
5988 ///Field `PD7` reader - Pin D7
5989 pub type PD7_R = crate::BitReader;
5990 ///Field `PD7` writer - Pin D7
5991 pub type PD7_W<'a, REG> = crate::BitWriter<'a, REG>;
5992 impl R {
5993 ///Bit 0 - Pin D0
5994 #[inline(always)]
5995 pub fn pd0(&self) -> PD0_R {
5996 PD0_R::new((self.bits & 1) != 0)
5997 }
5998 ///Bit 1 - Pin D1
5999 #[inline(always)]
6000 pub fn pd1(&self) -> PD1_R {
6001 PD1_R::new(((self.bits >> 1) & 1) != 0)
6002 }
6003 ///Bit 2 - Pin D2
6004 #[inline(always)]
6005 pub fn pd2(&self) -> PD2_R {
6006 PD2_R::new(((self.bits >> 2) & 1) != 0)
6007 }
6008 ///Bit 3 - Pin D3
6009 #[inline(always)]
6010 pub fn pd3(&self) -> PD3_R {
6011 PD3_R::new(((self.bits >> 3) & 1) != 0)
6012 }
6013 ///Bit 4 - Pin D4
6014 #[inline(always)]
6015 pub fn pd4(&self) -> PD4_R {
6016 PD4_R::new(((self.bits >> 4) & 1) != 0)
6017 }
6018 ///Bit 5 - Pin D5
6019 #[inline(always)]
6020 pub fn pd5(&self) -> PD5_R {
6021 PD5_R::new(((self.bits >> 5) & 1) != 0)
6022 }
6023 ///Bit 6 - Pin D6
6024 #[inline(always)]
6025 pub fn pd6(&self) -> PD6_R {
6026 PD6_R::new(((self.bits >> 6) & 1) != 0)
6027 }
6028 ///Bit 7 - Pin D7
6029 #[inline(always)]
6030 pub fn pd7(&self) -> PD7_R {
6031 PD7_R::new(((self.bits >> 7) & 1) != 0)
6032 }
6033 }
6034 impl W {
6035 ///Bit 0 - Pin D0
6036 #[inline(always)]
6037 pub fn pd0(&mut self) -> PD0_W<'_, PIND_SPEC> {
6038 PD0_W::new(self, 0)
6039 }
6040 ///Bit 1 - Pin D1
6041 #[inline(always)]
6042 pub fn pd1(&mut self) -> PD1_W<'_, PIND_SPEC> {
6043 PD1_W::new(self, 1)
6044 }
6045 ///Bit 2 - Pin D2
6046 #[inline(always)]
6047 pub fn pd2(&mut self) -> PD2_W<'_, PIND_SPEC> {
6048 PD2_W::new(self, 2)
6049 }
6050 ///Bit 3 - Pin D3
6051 #[inline(always)]
6052 pub fn pd3(&mut self) -> PD3_W<'_, PIND_SPEC> {
6053 PD3_W::new(self, 3)
6054 }
6055 ///Bit 4 - Pin D4
6056 #[inline(always)]
6057 pub fn pd4(&mut self) -> PD4_W<'_, PIND_SPEC> {
6058 PD4_W::new(self, 4)
6059 }
6060 ///Bit 5 - Pin D5
6061 #[inline(always)]
6062 pub fn pd5(&mut self) -> PD5_W<'_, PIND_SPEC> {
6063 PD5_W::new(self, 5)
6064 }
6065 ///Bit 6 - Pin D6
6066 #[inline(always)]
6067 pub fn pd6(&mut self) -> PD6_W<'_, PIND_SPEC> {
6068 PD6_W::new(self, 6)
6069 }
6070 ///Bit 7 - Pin D7
6071 #[inline(always)]
6072 pub fn pd7(&mut self) -> PD7_W<'_, PIND_SPEC> {
6073 PD7_W::new(self, 7)
6074 }
6075 }
6076 /**Port D Input Pins
6077
6078You can [`read`](crate::Reg::read) this register and get [`pind::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pind::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
6079 pub struct PIND_SPEC;
6080 impl crate::RegisterSpec for PIND_SPEC {
6081 type Ux = u8;
6082 }
6083 ///`read()` method returns [`pind::R`](R) reader structure
6084 impl crate::Readable for PIND_SPEC {}
6085 ///`write(|w| ..)` method takes [`pind::W`](W) writer structure
6086 impl crate::Writable for PIND_SPEC {
6087 type Safety = crate::Unsafe;
6088 }
6089 ///`reset()` method sets PIND to value 0
6090 impl crate::Resettable for PIND_SPEC {}
6091 }
6092 /**PORTD (rw) register accessor: Port D Data Register
6093
6094You can [`read`](crate::Reg::read) this register and get [`portd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`portd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
6095
6096For information about available fields see [`mod@portd`] module*/
6097 pub type PORTD = crate::Reg<portd::PORTD_SPEC>;
6098 ///Port D Data Register
6099 pub mod portd {
6100 ///Register `PORTD` reader
6101 pub type R = crate::R<PORTD_SPEC>;
6102 ///Register `PORTD` writer
6103 pub type W = crate::W<PORTD_SPEC>;
6104 ///Field `PD0` reader - Pin D0
6105 pub type PD0_R = crate::BitReader;
6106 ///Field `PD0` writer - Pin D0
6107 pub type PD0_W<'a, REG> = crate::BitWriter<'a, REG>;
6108 ///Field `PD1` reader - Pin D1
6109 pub type PD1_R = crate::BitReader;
6110 ///Field `PD1` writer - Pin D1
6111 pub type PD1_W<'a, REG> = crate::BitWriter<'a, REG>;
6112 ///Field `PD2` reader - Pin D2
6113 pub type PD2_R = crate::BitReader;
6114 ///Field `PD2` writer - Pin D2
6115 pub type PD2_W<'a, REG> = crate::BitWriter<'a, REG>;
6116 ///Field `PD3` reader - Pin D3
6117 pub type PD3_R = crate::BitReader;
6118 ///Field `PD3` writer - Pin D3
6119 pub type PD3_W<'a, REG> = crate::BitWriter<'a, REG>;
6120 ///Field `PD4` reader - Pin D4
6121 pub type PD4_R = crate::BitReader;
6122 ///Field `PD4` writer - Pin D4
6123 pub type PD4_W<'a, REG> = crate::BitWriter<'a, REG>;
6124 ///Field `PD5` reader - Pin D5
6125 pub type PD5_R = crate::BitReader;
6126 ///Field `PD5` writer - Pin D5
6127 pub type PD5_W<'a, REG> = crate::BitWriter<'a, REG>;
6128 ///Field `PD6` reader - Pin D6
6129 pub type PD6_R = crate::BitReader;
6130 ///Field `PD6` writer - Pin D6
6131 pub type PD6_W<'a, REG> = crate::BitWriter<'a, REG>;
6132 ///Field `PD7` reader - Pin D7
6133 pub type PD7_R = crate::BitReader;
6134 ///Field `PD7` writer - Pin D7
6135 pub type PD7_W<'a, REG> = crate::BitWriter<'a, REG>;
6136 impl R {
6137 ///Bit 0 - Pin D0
6138 #[inline(always)]
6139 pub fn pd0(&self) -> PD0_R {
6140 PD0_R::new((self.bits & 1) != 0)
6141 }
6142 ///Bit 1 - Pin D1
6143 #[inline(always)]
6144 pub fn pd1(&self) -> PD1_R {
6145 PD1_R::new(((self.bits >> 1) & 1) != 0)
6146 }
6147 ///Bit 2 - Pin D2
6148 #[inline(always)]
6149 pub fn pd2(&self) -> PD2_R {
6150 PD2_R::new(((self.bits >> 2) & 1) != 0)
6151 }
6152 ///Bit 3 - Pin D3
6153 #[inline(always)]
6154 pub fn pd3(&self) -> PD3_R {
6155 PD3_R::new(((self.bits >> 3) & 1) != 0)
6156 }
6157 ///Bit 4 - Pin D4
6158 #[inline(always)]
6159 pub fn pd4(&self) -> PD4_R {
6160 PD4_R::new(((self.bits >> 4) & 1) != 0)
6161 }
6162 ///Bit 5 - Pin D5
6163 #[inline(always)]
6164 pub fn pd5(&self) -> PD5_R {
6165 PD5_R::new(((self.bits >> 5) & 1) != 0)
6166 }
6167 ///Bit 6 - Pin D6
6168 #[inline(always)]
6169 pub fn pd6(&self) -> PD6_R {
6170 PD6_R::new(((self.bits >> 6) & 1) != 0)
6171 }
6172 ///Bit 7 - Pin D7
6173 #[inline(always)]
6174 pub fn pd7(&self) -> PD7_R {
6175 PD7_R::new(((self.bits >> 7) & 1) != 0)
6176 }
6177 }
6178 impl W {
6179 ///Bit 0 - Pin D0
6180 #[inline(always)]
6181 pub fn pd0(&mut self) -> PD0_W<'_, PORTD_SPEC> {
6182 PD0_W::new(self, 0)
6183 }
6184 ///Bit 1 - Pin D1
6185 #[inline(always)]
6186 pub fn pd1(&mut self) -> PD1_W<'_, PORTD_SPEC> {
6187 PD1_W::new(self, 1)
6188 }
6189 ///Bit 2 - Pin D2
6190 #[inline(always)]
6191 pub fn pd2(&mut self) -> PD2_W<'_, PORTD_SPEC> {
6192 PD2_W::new(self, 2)
6193 }
6194 ///Bit 3 - Pin D3
6195 #[inline(always)]
6196 pub fn pd3(&mut self) -> PD3_W<'_, PORTD_SPEC> {
6197 PD3_W::new(self, 3)
6198 }
6199 ///Bit 4 - Pin D4
6200 #[inline(always)]
6201 pub fn pd4(&mut self) -> PD4_W<'_, PORTD_SPEC> {
6202 PD4_W::new(self, 4)
6203 }
6204 ///Bit 5 - Pin D5
6205 #[inline(always)]
6206 pub fn pd5(&mut self) -> PD5_W<'_, PORTD_SPEC> {
6207 PD5_W::new(self, 5)
6208 }
6209 ///Bit 6 - Pin D6
6210 #[inline(always)]
6211 pub fn pd6(&mut self) -> PD6_W<'_, PORTD_SPEC> {
6212 PD6_W::new(self, 6)
6213 }
6214 ///Bit 7 - Pin D7
6215 #[inline(always)]
6216 pub fn pd7(&mut self) -> PD7_W<'_, PORTD_SPEC> {
6217 PD7_W::new(self, 7)
6218 }
6219 }
6220 /**Port D Data Register
6221
6222You can [`read`](crate::Reg::read) this register and get [`portd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`portd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
6223 pub struct PORTD_SPEC;
6224 impl crate::RegisterSpec for PORTD_SPEC {
6225 type Ux = u8;
6226 }
6227 ///`read()` method returns [`portd::R`](R) reader structure
6228 impl crate::Readable for PORTD_SPEC {}
6229 ///`write(|w| ..)` method takes [`portd::W`](W) writer structure
6230 impl crate::Writable for PORTD_SPEC {
6231 type Safety = crate::Unsafe;
6232 }
6233 ///`reset()` method sets PORTD to value 0
6234 impl crate::Resettable for PORTD_SPEC {}
6235 }
6236}
6237///Serial Peripheral Interface
6238pub type SPI = crate::Periph<spi::RegisterBlock, 0x4c>;
6239impl core::fmt::Debug for SPI {
6240 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
6241 f.debug_struct("SPI").finish()
6242 }
6243}
6244///Serial Peripheral Interface
6245pub mod spi {
6246 #[repr(C)]
6247 ///Register block
6248 pub struct RegisterBlock {
6249 spcr: SPCR,
6250 spsr: SPSR,
6251 spdr: SPDR,
6252 }
6253 impl RegisterBlock {
6254 ///0x00 - SPI Control Register
6255 #[inline(always)]
6256 pub const fn spcr(&self) -> &SPCR {
6257 &self.spcr
6258 }
6259 ///0x01 - SPI Status Register
6260 #[inline(always)]
6261 pub const fn spsr(&self) -> &SPSR {
6262 &self.spsr
6263 }
6264 ///0x02 - SPI Data Register
6265 #[inline(always)]
6266 pub const fn spdr(&self) -> &SPDR {
6267 &self.spdr
6268 }
6269 }
6270 /**SPCR (rw) register accessor: SPI Control Register
6271
6272You can [`read`](crate::Reg::read) this register and get [`spcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
6273
6274For information about available fields see [`mod@spcr`] module*/
6275 pub type SPCR = crate::Reg<spcr::SPCR_SPEC>;
6276 ///SPI Control Register
6277 pub mod spcr {
6278 ///Register `SPCR` reader
6279 pub type R = crate::R<SPCR_SPEC>;
6280 ///Register `SPCR` writer
6281 pub type W = crate::W<SPCR_SPEC>;
6282 /**SPI Clock Rate Selects
6283
6284Value on reset: 0*/
6285 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
6286 #[repr(u8)]
6287 pub enum SPR_A {
6288 ///0: Fosc/4 if SPI2X == 0 else Fosc/2
6289 FOSC_4_2 = 0,
6290 ///1: Fosc/16 if SPI2X == 0 else Fosc/8
6291 FOSC_16_8 = 1,
6292 ///2: Fosc/64 if SPI2X == 0 else Fosc/32
6293 FOSC_64_32 = 2,
6294 ///3: Fosc/128 if SPI2X == 0 else Fosc/64
6295 FOSC_128_64 = 3,
6296 }
6297 impl From<SPR_A> for u8 {
6298 #[inline(always)]
6299 fn from(variant: SPR_A) -> Self {
6300 variant as _
6301 }
6302 }
6303 impl crate::FieldSpec for SPR_A {
6304 type Ux = u8;
6305 }
6306 impl crate::IsEnum for SPR_A {}
6307 ///Field `SPR` reader - SPI Clock Rate Selects
6308 pub type SPR_R = crate::FieldReader<SPR_A>;
6309 impl SPR_R {
6310 ///Get enumerated values variant
6311 #[inline(always)]
6312 pub const fn variant(&self) -> SPR_A {
6313 match self.bits {
6314 0 => SPR_A::FOSC_4_2,
6315 1 => SPR_A::FOSC_16_8,
6316 2 => SPR_A::FOSC_64_32,
6317 3 => SPR_A::FOSC_128_64,
6318 _ => unreachable!(),
6319 }
6320 }
6321 ///Fosc/4 if SPI2X == 0 else Fosc/2
6322 #[inline(always)]
6323 pub fn is_fosc_4_2(&self) -> bool {
6324 *self == SPR_A::FOSC_4_2
6325 }
6326 ///Fosc/16 if SPI2X == 0 else Fosc/8
6327 #[inline(always)]
6328 pub fn is_fosc_16_8(&self) -> bool {
6329 *self == SPR_A::FOSC_16_8
6330 }
6331 ///Fosc/64 if SPI2X == 0 else Fosc/32
6332 #[inline(always)]
6333 pub fn is_fosc_64_32(&self) -> bool {
6334 *self == SPR_A::FOSC_64_32
6335 }
6336 ///Fosc/128 if SPI2X == 0 else Fosc/64
6337 #[inline(always)]
6338 pub fn is_fosc_128_64(&self) -> bool {
6339 *self == SPR_A::FOSC_128_64
6340 }
6341 }
6342 ///Field `SPR` writer - SPI Clock Rate Selects
6343 pub type SPR_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SPR_A, crate::Safe>;
6344 impl<'a, REG> SPR_W<'a, REG>
6345 where
6346 REG: crate::Writable + crate::RegisterSpec,
6347 REG::Ux: From<u8>,
6348 {
6349 ///Fosc/4 if SPI2X == 0 else Fosc/2
6350 #[inline(always)]
6351 pub fn fosc_4_2(self) -> &'a mut crate::W<REG> {
6352 self.variant(SPR_A::FOSC_4_2)
6353 }
6354 ///Fosc/16 if SPI2X == 0 else Fosc/8
6355 #[inline(always)]
6356 pub fn fosc_16_8(self) -> &'a mut crate::W<REG> {
6357 self.variant(SPR_A::FOSC_16_8)
6358 }
6359 ///Fosc/64 if SPI2X == 0 else Fosc/32
6360 #[inline(always)]
6361 pub fn fosc_64_32(self) -> &'a mut crate::W<REG> {
6362 self.variant(SPR_A::FOSC_64_32)
6363 }
6364 ///Fosc/128 if SPI2X == 0 else Fosc/64
6365 #[inline(always)]
6366 pub fn fosc_128_64(self) -> &'a mut crate::W<REG> {
6367 self.variant(SPR_A::FOSC_128_64)
6368 }
6369 }
6370 ///Field `CPHA` reader - Clock Phase
6371 pub type CPHA_R = crate::BitReader;
6372 ///Field `CPHA` writer - Clock Phase
6373 pub type CPHA_W<'a, REG> = crate::BitWriter<'a, REG>;
6374 ///Field `CPOL` reader - Clock polarity
6375 pub type CPOL_R = crate::BitReader;
6376 ///Field `CPOL` writer - Clock polarity
6377 pub type CPOL_W<'a, REG> = crate::BitWriter<'a, REG>;
6378 ///Field `MSTR` reader - Master/Slave Select
6379 pub type MSTR_R = crate::BitReader;
6380 ///Field `MSTR` writer - Master/Slave Select
6381 pub type MSTR_W<'a, REG> = crate::BitWriter<'a, REG>;
6382 ///Field `DORD` reader - Data Order
6383 pub type DORD_R = crate::BitReader;
6384 ///Field `DORD` writer - Data Order
6385 pub type DORD_W<'a, REG> = crate::BitWriter<'a, REG>;
6386 ///Field `SPE` reader - SPI Enable
6387 pub type SPE_R = crate::BitReader;
6388 ///Field `SPE` writer - SPI Enable
6389 pub type SPE_W<'a, REG> = crate::BitWriter<'a, REG>;
6390 ///Field `SPIE` reader - SPI Interrupt Enable
6391 pub type SPIE_R = crate::BitReader;
6392 ///Field `SPIE` writer - SPI Interrupt Enable
6393 pub type SPIE_W<'a, REG> = crate::BitWriter<'a, REG>;
6394 impl R {
6395 ///Bits 0:1 - SPI Clock Rate Selects
6396 #[inline(always)]
6397 pub fn spr(&self) -> SPR_R {
6398 SPR_R::new(self.bits & 3)
6399 }
6400 ///Bit 2 - Clock Phase
6401 #[inline(always)]
6402 pub fn cpha(&self) -> CPHA_R {
6403 CPHA_R::new(((self.bits >> 2) & 1) != 0)
6404 }
6405 ///Bit 3 - Clock polarity
6406 #[inline(always)]
6407 pub fn cpol(&self) -> CPOL_R {
6408 CPOL_R::new(((self.bits >> 3) & 1) != 0)
6409 }
6410 ///Bit 4 - Master/Slave Select
6411 #[inline(always)]
6412 pub fn mstr(&self) -> MSTR_R {
6413 MSTR_R::new(((self.bits >> 4) & 1) != 0)
6414 }
6415 ///Bit 5 - Data Order
6416 #[inline(always)]
6417 pub fn dord(&self) -> DORD_R {
6418 DORD_R::new(((self.bits >> 5) & 1) != 0)
6419 }
6420 ///Bit 6 - SPI Enable
6421 #[inline(always)]
6422 pub fn spe(&self) -> SPE_R {
6423 SPE_R::new(((self.bits >> 6) & 1) != 0)
6424 }
6425 ///Bit 7 - SPI Interrupt Enable
6426 #[inline(always)]
6427 pub fn spie(&self) -> SPIE_R {
6428 SPIE_R::new(((self.bits >> 7) & 1) != 0)
6429 }
6430 }
6431 impl W {
6432 ///Bits 0:1 - SPI Clock Rate Selects
6433 #[inline(always)]
6434 pub fn spr(&mut self) -> SPR_W<'_, SPCR_SPEC> {
6435 SPR_W::new(self, 0)
6436 }
6437 ///Bit 2 - Clock Phase
6438 #[inline(always)]
6439 pub fn cpha(&mut self) -> CPHA_W<'_, SPCR_SPEC> {
6440 CPHA_W::new(self, 2)
6441 }
6442 ///Bit 3 - Clock polarity
6443 #[inline(always)]
6444 pub fn cpol(&mut self) -> CPOL_W<'_, SPCR_SPEC> {
6445 CPOL_W::new(self, 3)
6446 }
6447 ///Bit 4 - Master/Slave Select
6448 #[inline(always)]
6449 pub fn mstr(&mut self) -> MSTR_W<'_, SPCR_SPEC> {
6450 MSTR_W::new(self, 4)
6451 }
6452 ///Bit 5 - Data Order
6453 #[inline(always)]
6454 pub fn dord(&mut self) -> DORD_W<'_, SPCR_SPEC> {
6455 DORD_W::new(self, 5)
6456 }
6457 ///Bit 6 - SPI Enable
6458 #[inline(always)]
6459 pub fn spe(&mut self) -> SPE_W<'_, SPCR_SPEC> {
6460 SPE_W::new(self, 6)
6461 }
6462 ///Bit 7 - SPI Interrupt Enable
6463 #[inline(always)]
6464 pub fn spie(&mut self) -> SPIE_W<'_, SPCR_SPEC> {
6465 SPIE_W::new(self, 7)
6466 }
6467 }
6468 /**SPI Control Register
6469
6470You can [`read`](crate::Reg::read) this register and get [`spcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
6471 pub struct SPCR_SPEC;
6472 impl crate::RegisterSpec for SPCR_SPEC {
6473 type Ux = u8;
6474 }
6475 ///`read()` method returns [`spcr::R`](R) reader structure
6476 impl crate::Readable for SPCR_SPEC {}
6477 ///`write(|w| ..)` method takes [`spcr::W`](W) writer structure
6478 impl crate::Writable for SPCR_SPEC {
6479 type Safety = crate::Unsafe;
6480 }
6481 ///`reset()` method sets SPCR to value 0
6482 impl crate::Resettable for SPCR_SPEC {}
6483 }
6484 /**SPDR (rw) register accessor: SPI Data Register
6485
6486You can [`read`](crate::Reg::read) this register and get [`spdr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spdr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
6487
6488For information about available fields see [`mod@spdr`] module*/
6489 pub type SPDR = crate::Reg<spdr::SPDR_SPEC>;
6490 ///SPI Data Register
6491 pub mod spdr {
6492 ///Register `SPDR` reader
6493 pub type R = crate::R<SPDR_SPEC>;
6494 ///Register `SPDR` writer
6495 pub type W = crate::W<SPDR_SPEC>;
6496 impl core::fmt::Debug for R {
6497 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
6498 write!(f, "{}", self.bits())
6499 }
6500 }
6501 impl W {}
6502 /**SPI Data Register
6503
6504You can [`read`](crate::Reg::read) this register and get [`spdr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spdr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
6505 pub struct SPDR_SPEC;
6506 impl crate::RegisterSpec for SPDR_SPEC {
6507 type Ux = u8;
6508 }
6509 ///`read()` method returns [`spdr::R`](R) reader structure
6510 impl crate::Readable for SPDR_SPEC {}
6511 ///`write(|w| ..)` method takes [`spdr::W`](W) writer structure
6512 impl crate::Writable for SPDR_SPEC {
6513 type Safety = crate::Safe;
6514 }
6515 ///`reset()` method sets SPDR to value 0
6516 impl crate::Resettable for SPDR_SPEC {}
6517 }
6518 /**SPSR (rw) register accessor: SPI Status Register
6519
6520You can [`read`](crate::Reg::read) this register and get [`spsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
6521
6522For information about available fields see [`mod@spsr`] module*/
6523 pub type SPSR = crate::Reg<spsr::SPSR_SPEC>;
6524 ///SPI Status Register
6525 pub mod spsr {
6526 ///Register `SPSR` reader
6527 pub type R = crate::R<SPSR_SPEC>;
6528 ///Register `SPSR` writer
6529 pub type W = crate::W<SPSR_SPEC>;
6530 ///Field `SPI2X` reader - Double SPI Speed Bit
6531 pub type SPI2X_R = crate::BitReader;
6532 ///Field `SPI2X` writer - Double SPI Speed Bit
6533 pub type SPI2X_W<'a, REG> = crate::BitWriter<'a, REG>;
6534 ///Field `WCOL` reader - Write Collision Flag
6535 pub type WCOL_R = crate::BitReader;
6536 ///Field `SPIF` reader - SPI Interrupt Flag
6537 pub type SPIF_R = crate::BitReader;
6538 impl R {
6539 ///Bit 0 - Double SPI Speed Bit
6540 #[inline(always)]
6541 pub fn spi2x(&self) -> SPI2X_R {
6542 SPI2X_R::new((self.bits & 1) != 0)
6543 }
6544 ///Bit 6 - Write Collision Flag
6545 #[inline(always)]
6546 pub fn wcol(&self) -> WCOL_R {
6547 WCOL_R::new(((self.bits >> 6) & 1) != 0)
6548 }
6549 ///Bit 7 - SPI Interrupt Flag
6550 #[inline(always)]
6551 pub fn spif(&self) -> SPIF_R {
6552 SPIF_R::new(((self.bits >> 7) & 1) != 0)
6553 }
6554 }
6555 impl W {
6556 ///Bit 0 - Double SPI Speed Bit
6557 #[inline(always)]
6558 pub fn spi2x(&mut self) -> SPI2X_W<'_, SPSR_SPEC> {
6559 SPI2X_W::new(self, 0)
6560 }
6561 }
6562 /**SPI Status Register
6563
6564You can [`read`](crate::Reg::read) this register and get [`spsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
6565 pub struct SPSR_SPEC;
6566 impl crate::RegisterSpec for SPSR_SPEC {
6567 type Ux = u8;
6568 }
6569 ///`read()` method returns [`spsr::R`](R) reader structure
6570 impl crate::Readable for SPSR_SPEC {}
6571 ///`write(|w| ..)` method takes [`spsr::W`](W) writer structure
6572 impl crate::Writable for SPSR_SPEC {
6573 type Safety = crate::Unsafe;
6574 }
6575 ///`reset()` method sets SPSR to value 0
6576 impl crate::Resettable for SPSR_SPEC {}
6577 }
6578}
6579///Timer/Counter, 8-bit
6580pub type TC0 = crate::Periph<tc0::RegisterBlock, 0x35>;
6581impl core::fmt::Debug for TC0 {
6582 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
6583 f.debug_struct("TC0").finish()
6584 }
6585}
6586///Timer/Counter, 8-bit
6587pub mod tc0 {
6588 #[repr(C)]
6589 ///Register block
6590 pub struct RegisterBlock {
6591 tifr0: TIFR0,
6592 _reserved1: [u8; 0x0d],
6593 gtccr: GTCCR,
6594 tccr0a: TCCR0A,
6595 tccr0b: TCCR0B,
6596 tcnt0: TCNT0,
6597 ocr0a: OCR0A,
6598 ocr0b: OCR0B,
6599 _reserved7: [u8; 0x25],
6600 timsk0: TIMSK0,
6601 }
6602 impl RegisterBlock {
6603 ///0x00 - Timer/Counter0 Interrupt Flag register
6604 #[inline(always)]
6605 pub const fn tifr0(&self) -> &TIFR0 {
6606 &self.tifr0
6607 }
6608 ///0x0e - General Timer/Counter Control Register
6609 #[inline(always)]
6610 pub const fn gtccr(&self) -> >CCR {
6611 &self.gtccr
6612 }
6613 ///0x0f - Timer/Counter Control Register A
6614 #[inline(always)]
6615 pub const fn tccr0a(&self) -> &TCCR0A {
6616 &self.tccr0a
6617 }
6618 ///0x10 - Timer/Counter Control Register B
6619 #[inline(always)]
6620 pub const fn tccr0b(&self) -> &TCCR0B {
6621 &self.tccr0b
6622 }
6623 ///0x11 - Timer/Counter0
6624 #[inline(always)]
6625 pub const fn tcnt0(&self) -> &TCNT0 {
6626 &self.tcnt0
6627 }
6628 ///0x12 - Timer/Counter0 Output Compare Register
6629 #[inline(always)]
6630 pub const fn ocr0a(&self) -> &OCR0A {
6631 &self.ocr0a
6632 }
6633 ///0x13 - Timer/Counter0 Output Compare Register
6634 #[inline(always)]
6635 pub const fn ocr0b(&self) -> &OCR0B {
6636 &self.ocr0b
6637 }
6638 ///0x39 - Timer/Counter0 Interrupt Mask Register
6639 #[inline(always)]
6640 pub const fn timsk0(&self) -> &TIMSK0 {
6641 &self.timsk0
6642 }
6643 }
6644 /**GTCCR (rw) register accessor: General Timer/Counter Control Register
6645
6646You can [`read`](crate::Reg::read) this register and get [`gtccr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gtccr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
6647
6648For information about available fields see [`mod@gtccr`] module*/
6649 pub type GTCCR = crate::Reg<gtccr::GTCCR_SPEC>;
6650 ///General Timer/Counter Control Register
6651 pub mod gtccr {
6652 ///Register `GTCCR` reader
6653 pub type R = crate::R<GTCCR_SPEC>;
6654 ///Register `GTCCR` writer
6655 pub type W = crate::W<GTCCR_SPEC>;
6656 ///Field `PSRSYNC` reader - Prescaler Reset Timer/Counter1 and Timer/Counter0
6657 pub type PSRSYNC_R = crate::BitReader;
6658 ///Field `PSRSYNC` writer - Prescaler Reset Timer/Counter1 and Timer/Counter0
6659 pub type PSRSYNC_W<'a, REG> = crate::BitWriter<'a, REG>;
6660 ///Field `TSM` reader - Timer/Counter Synchronization Mode
6661 pub type TSM_R = crate::BitReader;
6662 ///Field `TSM` writer - Timer/Counter Synchronization Mode
6663 pub type TSM_W<'a, REG> = crate::BitWriter<'a, REG>;
6664 impl R {
6665 ///Bit 0 - Prescaler Reset Timer/Counter1 and Timer/Counter0
6666 #[inline(always)]
6667 pub fn psrsync(&self) -> PSRSYNC_R {
6668 PSRSYNC_R::new((self.bits & 1) != 0)
6669 }
6670 ///Bit 7 - Timer/Counter Synchronization Mode
6671 #[inline(always)]
6672 pub fn tsm(&self) -> TSM_R {
6673 TSM_R::new(((self.bits >> 7) & 1) != 0)
6674 }
6675 }
6676 impl W {
6677 ///Bit 0 - Prescaler Reset Timer/Counter1 and Timer/Counter0
6678 #[inline(always)]
6679 pub fn psrsync(&mut self) -> PSRSYNC_W<'_, GTCCR_SPEC> {
6680 PSRSYNC_W::new(self, 0)
6681 }
6682 ///Bit 7 - Timer/Counter Synchronization Mode
6683 #[inline(always)]
6684 pub fn tsm(&mut self) -> TSM_W<'_, GTCCR_SPEC> {
6685 TSM_W::new(self, 7)
6686 }
6687 }
6688 /**General Timer/Counter Control Register
6689
6690You can [`read`](crate::Reg::read) this register and get [`gtccr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gtccr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
6691 pub struct GTCCR_SPEC;
6692 impl crate::RegisterSpec for GTCCR_SPEC {
6693 type Ux = u8;
6694 }
6695 ///`read()` method returns [`gtccr::R`](R) reader structure
6696 impl crate::Readable for GTCCR_SPEC {}
6697 ///`write(|w| ..)` method takes [`gtccr::W`](W) writer structure
6698 impl crate::Writable for GTCCR_SPEC {
6699 type Safety = crate::Unsafe;
6700 }
6701 ///`reset()` method sets GTCCR to value 0
6702 impl crate::Resettable for GTCCR_SPEC {}
6703 }
6704 /**OCR0A (rw) register accessor: Timer/Counter0 Output Compare Register
6705
6706You can [`read`](crate::Reg::read) this register and get [`ocr0a::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ocr0a::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
6707
6708For information about available fields see [`mod@ocr0a`] module*/
6709 pub type OCR0A = crate::Reg<ocr0a::OCR0A_SPEC>;
6710 ///Timer/Counter0 Output Compare Register
6711 pub mod ocr0a {
6712 ///Register `OCR0A` reader
6713 pub type R = crate::R<OCR0A_SPEC>;
6714 ///Register `OCR0A` writer
6715 pub type W = crate::W<OCR0A_SPEC>;
6716 impl core::fmt::Debug for R {
6717 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
6718 write!(f, "{}", self.bits())
6719 }
6720 }
6721 impl W {}
6722 /**Timer/Counter0 Output Compare Register
6723
6724You can [`read`](crate::Reg::read) this register and get [`ocr0a::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ocr0a::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
6725 pub struct OCR0A_SPEC;
6726 impl crate::RegisterSpec for OCR0A_SPEC {
6727 type Ux = u8;
6728 }
6729 ///`read()` method returns [`ocr0a::R`](R) reader structure
6730 impl crate::Readable for OCR0A_SPEC {}
6731 ///`write(|w| ..)` method takes [`ocr0a::W`](W) writer structure
6732 impl crate::Writable for OCR0A_SPEC {
6733 type Safety = crate::Safe;
6734 }
6735 ///`reset()` method sets OCR0A to value 0
6736 impl crate::Resettable for OCR0A_SPEC {}
6737 }
6738 /**OCR0B (rw) register accessor: Timer/Counter0 Output Compare Register
6739
6740You can [`read`](crate::Reg::read) this register and get [`ocr0b::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ocr0b::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
6741
6742For information about available fields see [`mod@ocr0b`] module*/
6743 pub type OCR0B = crate::Reg<ocr0b::OCR0B_SPEC>;
6744 ///Timer/Counter0 Output Compare Register
6745 pub mod ocr0b {
6746 ///Register `OCR0B` reader
6747 pub type R = crate::R<OCR0B_SPEC>;
6748 ///Register `OCR0B` writer
6749 pub type W = crate::W<OCR0B_SPEC>;
6750 impl core::fmt::Debug for R {
6751 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
6752 write!(f, "{}", self.bits())
6753 }
6754 }
6755 impl W {}
6756 /**Timer/Counter0 Output Compare Register
6757
6758You can [`read`](crate::Reg::read) this register and get [`ocr0b::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ocr0b::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
6759 pub struct OCR0B_SPEC;
6760 impl crate::RegisterSpec for OCR0B_SPEC {
6761 type Ux = u8;
6762 }
6763 ///`read()` method returns [`ocr0b::R`](R) reader structure
6764 impl crate::Readable for OCR0B_SPEC {}
6765 ///`write(|w| ..)` method takes [`ocr0b::W`](W) writer structure
6766 impl crate::Writable for OCR0B_SPEC {
6767 type Safety = crate::Safe;
6768 }
6769 ///`reset()` method sets OCR0B to value 0
6770 impl crate::Resettable for OCR0B_SPEC {}
6771 }
6772 /**TCCR0A (rw) register accessor: Timer/Counter Control Register A
6773
6774You can [`read`](crate::Reg::read) this register and get [`tccr0a::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tccr0a::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
6775
6776For information about available fields see [`mod@tccr0a`] module*/
6777 pub type TCCR0A = crate::Reg<tccr0a::TCCR0A_SPEC>;
6778 ///Timer/Counter Control Register A
6779 pub mod tccr0a {
6780 ///Register `TCCR0A` reader
6781 pub type R = crate::R<TCCR0A_SPEC>;
6782 ///Register `TCCR0A` writer
6783 pub type W = crate::W<TCCR0A_SPEC>;
6784 /**Waveform Generation Mode
6785
6786Value on reset: 0*/
6787 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
6788 #[repr(u8)]
6789 pub enum WGM0_A {
6790 ///0: Normal, Top: `0xff`, Update: *Immediate*, Flag: *MAX*
6791 NORMAL_TOP = 0,
6792 ///1: Phase Correct PWM, Top: `0xff`, Update: *TOP*, Flag: *BOTTOM*
6793 PWM_PHASE = 1,
6794 ///2: CTC, Top: *OCRA*, Update: *Immediate*, Flag: *MAX*
6795 CTC = 2,
6796 ///3: Fast PWM, Top: `0xff`, Update: *TOP*, Flag: *MAX*
6797 PWM_FAST = 3,
6798 }
6799 impl From<WGM0_A> for u8 {
6800 #[inline(always)]
6801 fn from(variant: WGM0_A) -> Self {
6802 variant as _
6803 }
6804 }
6805 impl crate::FieldSpec for WGM0_A {
6806 type Ux = u8;
6807 }
6808 impl crate::IsEnum for WGM0_A {}
6809 ///Field `WGM0` reader - Waveform Generation Mode
6810 pub type WGM0_R = crate::FieldReader<WGM0_A>;
6811 impl WGM0_R {
6812 ///Get enumerated values variant
6813 #[inline(always)]
6814 pub const fn variant(&self) -> WGM0_A {
6815 match self.bits {
6816 0 => WGM0_A::NORMAL_TOP,
6817 1 => WGM0_A::PWM_PHASE,
6818 2 => WGM0_A::CTC,
6819 3 => WGM0_A::PWM_FAST,
6820 _ => unreachable!(),
6821 }
6822 }
6823 ///Normal, Top: `0xff`, Update: *Immediate*, Flag: *MAX*
6824 #[inline(always)]
6825 pub fn is_normal_top(&self) -> bool {
6826 *self == WGM0_A::NORMAL_TOP
6827 }
6828 ///Phase Correct PWM, Top: `0xff`, Update: *TOP*, Flag: *BOTTOM*
6829 #[inline(always)]
6830 pub fn is_pwm_phase(&self) -> bool {
6831 *self == WGM0_A::PWM_PHASE
6832 }
6833 ///CTC, Top: *OCRA*, Update: *Immediate*, Flag: *MAX*
6834 #[inline(always)]
6835 pub fn is_ctc(&self) -> bool {
6836 *self == WGM0_A::CTC
6837 }
6838 ///Fast PWM, Top: `0xff`, Update: *TOP*, Flag: *MAX*
6839 #[inline(always)]
6840 pub fn is_pwm_fast(&self) -> bool {
6841 *self == WGM0_A::PWM_FAST
6842 }
6843 }
6844 ///Field `WGM0` writer - Waveform Generation Mode
6845 pub type WGM0_W<'a, REG> = crate::FieldWriter<'a, REG, 2, WGM0_A, crate::Safe>;
6846 impl<'a, REG> WGM0_W<'a, REG>
6847 where
6848 REG: crate::Writable + crate::RegisterSpec,
6849 REG::Ux: From<u8>,
6850 {
6851 ///Normal, Top: `0xff`, Update: *Immediate*, Flag: *MAX*
6852 #[inline(always)]
6853 pub fn normal_top(self) -> &'a mut crate::W<REG> {
6854 self.variant(WGM0_A::NORMAL_TOP)
6855 }
6856 ///Phase Correct PWM, Top: `0xff`, Update: *TOP*, Flag: *BOTTOM*
6857 #[inline(always)]
6858 pub fn pwm_phase(self) -> &'a mut crate::W<REG> {
6859 self.variant(WGM0_A::PWM_PHASE)
6860 }
6861 ///CTC, Top: *OCRA*, Update: *Immediate*, Flag: *MAX*
6862 #[inline(always)]
6863 pub fn ctc(self) -> &'a mut crate::W<REG> {
6864 self.variant(WGM0_A::CTC)
6865 }
6866 ///Fast PWM, Top: `0xff`, Update: *TOP*, Flag: *MAX*
6867 #[inline(always)]
6868 pub fn pwm_fast(self) -> &'a mut crate::W<REG> {
6869 self.variant(WGM0_A::PWM_FAST)
6870 }
6871 }
6872 /**Compare Output B Mode
6873
6874Value on reset: 0*/
6875 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
6876 #[repr(u8)]
6877 pub enum COM0B_A {
6878 ///0: Normal port operation, OCix disconnected
6879 DISCONNECTED = 0,
6880 ///1: Toggle OCix on Compare Match (Might depend on WGM)
6881 MATCH_TOGGLE = 1,
6882 ///2: Clear OCix on Compare Match (If PWM is enabled, OCix is set at TOP)
6883 MATCH_CLEAR = 2,
6884 ///3: Set OCix on Compare Match (If PWM is enabled, OCix is cleared at TOP)
6885 MATCH_SET = 3,
6886 }
6887 impl From<COM0B_A> for u8 {
6888 #[inline(always)]
6889 fn from(variant: COM0B_A) -> Self {
6890 variant as _
6891 }
6892 }
6893 impl crate::FieldSpec for COM0B_A {
6894 type Ux = u8;
6895 }
6896 impl crate::IsEnum for COM0B_A {}
6897 ///Field `COM0B` reader - Compare Output B Mode
6898 pub type COM0B_R = crate::FieldReader<COM0B_A>;
6899 impl COM0B_R {
6900 ///Get enumerated values variant
6901 #[inline(always)]
6902 pub const fn variant(&self) -> COM0B_A {
6903 match self.bits {
6904 0 => COM0B_A::DISCONNECTED,
6905 1 => COM0B_A::MATCH_TOGGLE,
6906 2 => COM0B_A::MATCH_CLEAR,
6907 3 => COM0B_A::MATCH_SET,
6908 _ => unreachable!(),
6909 }
6910 }
6911 ///Normal port operation, OCix disconnected
6912 #[inline(always)]
6913 pub fn is_disconnected(&self) -> bool {
6914 *self == COM0B_A::DISCONNECTED
6915 }
6916 ///Toggle OCix on Compare Match (Might depend on WGM)
6917 #[inline(always)]
6918 pub fn is_match_toggle(&self) -> bool {
6919 *self == COM0B_A::MATCH_TOGGLE
6920 }
6921 ///Clear OCix on Compare Match (If PWM is enabled, OCix is set at TOP)
6922 #[inline(always)]
6923 pub fn is_match_clear(&self) -> bool {
6924 *self == COM0B_A::MATCH_CLEAR
6925 }
6926 ///Set OCix on Compare Match (If PWM is enabled, OCix is cleared at TOP)
6927 #[inline(always)]
6928 pub fn is_match_set(&self) -> bool {
6929 *self == COM0B_A::MATCH_SET
6930 }
6931 }
6932 ///Field `COM0B` writer - Compare Output B Mode
6933 pub type COM0B_W<'a, REG> = crate::FieldWriter<'a, REG, 2, COM0B_A, crate::Safe>;
6934 impl<'a, REG> COM0B_W<'a, REG>
6935 where
6936 REG: crate::Writable + crate::RegisterSpec,
6937 REG::Ux: From<u8>,
6938 {
6939 ///Normal port operation, OCix disconnected
6940 #[inline(always)]
6941 pub fn disconnected(self) -> &'a mut crate::W<REG> {
6942 self.variant(COM0B_A::DISCONNECTED)
6943 }
6944 ///Toggle OCix on Compare Match (Might depend on WGM)
6945 #[inline(always)]
6946 pub fn match_toggle(self) -> &'a mut crate::W<REG> {
6947 self.variant(COM0B_A::MATCH_TOGGLE)
6948 }
6949 ///Clear OCix on Compare Match (If PWM is enabled, OCix is set at TOP)
6950 #[inline(always)]
6951 pub fn match_clear(self) -> &'a mut crate::W<REG> {
6952 self.variant(COM0B_A::MATCH_CLEAR)
6953 }
6954 ///Set OCix on Compare Match (If PWM is enabled, OCix is cleared at TOP)
6955 #[inline(always)]
6956 pub fn match_set(self) -> &'a mut crate::W<REG> {
6957 self.variant(COM0B_A::MATCH_SET)
6958 }
6959 }
6960 ///Field `COM0A` reader - Compare Output A Mode
6961 pub use COM0B_R as COM0A_R;
6962 ///Field `COM0A` writer - Compare Output A Mode
6963 pub use COM0B_W as COM0A_W;
6964 impl R {
6965 ///Bits 0:1 - Waveform Generation Mode
6966 #[inline(always)]
6967 pub fn wgm0(&self) -> WGM0_R {
6968 WGM0_R::new(self.bits & 3)
6969 }
6970 ///Bits 4:5 - Compare Output B Mode
6971 #[inline(always)]
6972 pub fn com0b(&self) -> COM0B_R {
6973 COM0B_R::new((self.bits >> 4) & 3)
6974 }
6975 ///Bits 6:7 - Compare Output A Mode
6976 #[inline(always)]
6977 pub fn com0a(&self) -> COM0A_R {
6978 COM0A_R::new((self.bits >> 6) & 3)
6979 }
6980 }
6981 impl W {
6982 ///Bits 0:1 - Waveform Generation Mode
6983 #[inline(always)]
6984 pub fn wgm0(&mut self) -> WGM0_W<'_, TCCR0A_SPEC> {
6985 WGM0_W::new(self, 0)
6986 }
6987 ///Bits 4:5 - Compare Output B Mode
6988 #[inline(always)]
6989 pub fn com0b(&mut self) -> COM0B_W<'_, TCCR0A_SPEC> {
6990 COM0B_W::new(self, 4)
6991 }
6992 ///Bits 6:7 - Compare Output A Mode
6993 #[inline(always)]
6994 pub fn com0a(&mut self) -> COM0A_W<'_, TCCR0A_SPEC> {
6995 COM0A_W::new(self, 6)
6996 }
6997 }
6998 /**Timer/Counter Control Register A
6999
7000You can [`read`](crate::Reg::read) this register and get [`tccr0a::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tccr0a::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
7001 pub struct TCCR0A_SPEC;
7002 impl crate::RegisterSpec for TCCR0A_SPEC {
7003 type Ux = u8;
7004 }
7005 ///`read()` method returns [`tccr0a::R`](R) reader structure
7006 impl crate::Readable for TCCR0A_SPEC {}
7007 ///`write(|w| ..)` method takes [`tccr0a::W`](W) writer structure
7008 impl crate::Writable for TCCR0A_SPEC {
7009 type Safety = crate::Unsafe;
7010 }
7011 ///`reset()` method sets TCCR0A to value 0
7012 impl crate::Resettable for TCCR0A_SPEC {}
7013 }
7014 /**TCCR0B (rw) register accessor: Timer/Counter Control Register B
7015
7016You can [`read`](crate::Reg::read) this register and get [`tccr0b::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tccr0b::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
7017
7018For information about available fields see [`mod@tccr0b`] module*/
7019 pub type TCCR0B = crate::Reg<tccr0b::TCCR0B_SPEC>;
7020 ///Timer/Counter Control Register B
7021 pub mod tccr0b {
7022 ///Register `TCCR0B` reader
7023 pub type R = crate::R<TCCR0B_SPEC>;
7024 ///Register `TCCR0B` writer
7025 pub type W = crate::W<TCCR0B_SPEC>;
7026 /**Clock Select
7027
7028Value on reset: 0*/
7029 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
7030 #[repr(u8)]
7031 pub enum CS0_A {
7032 ///0: No clock source (Timer/Counter stopped)
7033 NO_CLOCK = 0,
7034 ///1: Running, No Prescaling
7035 DIRECT = 1,
7036 ///2: Running, CLK/8
7037 PRESCALE_8 = 2,
7038 ///3: Running, CLK/64
7039 PRESCALE_64 = 3,
7040 ///4: Running, CLK/256
7041 PRESCALE_256 = 4,
7042 ///5: Running, CLK/1024
7043 PRESCALE_1024 = 5,
7044 ///6: Running, ExtClk Tx Falling Edge
7045 EXT_FALLING = 6,
7046 ///7: Running, ExtClk Tx Rising Edge
7047 EXT_RISING = 7,
7048 }
7049 impl From<CS0_A> for u8 {
7050 #[inline(always)]
7051 fn from(variant: CS0_A) -> Self {
7052 variant as _
7053 }
7054 }
7055 impl crate::FieldSpec for CS0_A {
7056 type Ux = u8;
7057 }
7058 impl crate::IsEnum for CS0_A {}
7059 ///Field `CS0` reader - Clock Select
7060 pub type CS0_R = crate::FieldReader<CS0_A>;
7061 impl CS0_R {
7062 ///Get enumerated values variant
7063 #[inline(always)]
7064 pub const fn variant(&self) -> CS0_A {
7065 match self.bits {
7066 0 => CS0_A::NO_CLOCK,
7067 1 => CS0_A::DIRECT,
7068 2 => CS0_A::PRESCALE_8,
7069 3 => CS0_A::PRESCALE_64,
7070 4 => CS0_A::PRESCALE_256,
7071 5 => CS0_A::PRESCALE_1024,
7072 6 => CS0_A::EXT_FALLING,
7073 7 => CS0_A::EXT_RISING,
7074 _ => unreachable!(),
7075 }
7076 }
7077 ///No clock source (Timer/Counter stopped)
7078 #[inline(always)]
7079 pub fn is_no_clock(&self) -> bool {
7080 *self == CS0_A::NO_CLOCK
7081 }
7082 ///Running, No Prescaling
7083 #[inline(always)]
7084 pub fn is_direct(&self) -> bool {
7085 *self == CS0_A::DIRECT
7086 }
7087 ///Running, CLK/8
7088 #[inline(always)]
7089 pub fn is_prescale_8(&self) -> bool {
7090 *self == CS0_A::PRESCALE_8
7091 }
7092 ///Running, CLK/64
7093 #[inline(always)]
7094 pub fn is_prescale_64(&self) -> bool {
7095 *self == CS0_A::PRESCALE_64
7096 }
7097 ///Running, CLK/256
7098 #[inline(always)]
7099 pub fn is_prescale_256(&self) -> bool {
7100 *self == CS0_A::PRESCALE_256
7101 }
7102 ///Running, CLK/1024
7103 #[inline(always)]
7104 pub fn is_prescale_1024(&self) -> bool {
7105 *self == CS0_A::PRESCALE_1024
7106 }
7107 ///Running, ExtClk Tx Falling Edge
7108 #[inline(always)]
7109 pub fn is_ext_falling(&self) -> bool {
7110 *self == CS0_A::EXT_FALLING
7111 }
7112 ///Running, ExtClk Tx Rising Edge
7113 #[inline(always)]
7114 pub fn is_ext_rising(&self) -> bool {
7115 *self == CS0_A::EXT_RISING
7116 }
7117 }
7118 ///Field `CS0` writer - Clock Select
7119 pub type CS0_W<'a, REG> = crate::FieldWriter<'a, REG, 3, CS0_A, crate::Safe>;
7120 impl<'a, REG> CS0_W<'a, REG>
7121 where
7122 REG: crate::Writable + crate::RegisterSpec,
7123 REG::Ux: From<u8>,
7124 {
7125 ///No clock source (Timer/Counter stopped)
7126 #[inline(always)]
7127 pub fn no_clock(self) -> &'a mut crate::W<REG> {
7128 self.variant(CS0_A::NO_CLOCK)
7129 }
7130 ///Running, No Prescaling
7131 #[inline(always)]
7132 pub fn direct(self) -> &'a mut crate::W<REG> {
7133 self.variant(CS0_A::DIRECT)
7134 }
7135 ///Running, CLK/8
7136 #[inline(always)]
7137 pub fn prescale_8(self) -> &'a mut crate::W<REG> {
7138 self.variant(CS0_A::PRESCALE_8)
7139 }
7140 ///Running, CLK/64
7141 #[inline(always)]
7142 pub fn prescale_64(self) -> &'a mut crate::W<REG> {
7143 self.variant(CS0_A::PRESCALE_64)
7144 }
7145 ///Running, CLK/256
7146 #[inline(always)]
7147 pub fn prescale_256(self) -> &'a mut crate::W<REG> {
7148 self.variant(CS0_A::PRESCALE_256)
7149 }
7150 ///Running, CLK/1024
7151 #[inline(always)]
7152 pub fn prescale_1024(self) -> &'a mut crate::W<REG> {
7153 self.variant(CS0_A::PRESCALE_1024)
7154 }
7155 ///Running, ExtClk Tx Falling Edge
7156 #[inline(always)]
7157 pub fn ext_falling(self) -> &'a mut crate::W<REG> {
7158 self.variant(CS0_A::EXT_FALLING)
7159 }
7160 ///Running, ExtClk Tx Rising Edge
7161 #[inline(always)]
7162 pub fn ext_rising(self) -> &'a mut crate::W<REG> {
7163 self.variant(CS0_A::EXT_RISING)
7164 }
7165 }
7166 ///Field `WGM02` reader - Waveform Generation Mode High Bit (Enable Top: *OCRA* for `PWM` modes)
7167 pub type WGM02_R = crate::BitReader;
7168 ///Field `WGM02` writer - Waveform Generation Mode High Bit (Enable Top: *OCRA* for `PWM` modes)
7169 pub type WGM02_W<'a, REG> = crate::BitWriter<'a, REG>;
7170 ///Field `FOC0B` writer - Force Output Compare B
7171 pub type FOC0B_W<'a, REG> = crate::BitWriter<'a, REG>;
7172 ///Field `FOC0A` writer - Force Output Compare A
7173 pub type FOC0A_W<'a, REG> = crate::BitWriter<'a, REG>;
7174 impl R {
7175 ///Bits 0:2 - Clock Select
7176 #[inline(always)]
7177 pub fn cs0(&self) -> CS0_R {
7178 CS0_R::new(self.bits & 7)
7179 }
7180 ///Bit 3 - Waveform Generation Mode High Bit (Enable Top: *OCRA* for `PWM` modes)
7181 #[inline(always)]
7182 pub fn wgm02(&self) -> WGM02_R {
7183 WGM02_R::new(((self.bits >> 3) & 1) != 0)
7184 }
7185 }
7186 impl W {
7187 ///Bits 0:2 - Clock Select
7188 #[inline(always)]
7189 pub fn cs0(&mut self) -> CS0_W<'_, TCCR0B_SPEC> {
7190 CS0_W::new(self, 0)
7191 }
7192 ///Bit 3 - Waveform Generation Mode High Bit (Enable Top: *OCRA* for `PWM` modes)
7193 #[inline(always)]
7194 pub fn wgm02(&mut self) -> WGM02_W<'_, TCCR0B_SPEC> {
7195 WGM02_W::new(self, 3)
7196 }
7197 ///Bit 6 - Force Output Compare B
7198 #[inline(always)]
7199 pub fn foc0b(&mut self) -> FOC0B_W<'_, TCCR0B_SPEC> {
7200 FOC0B_W::new(self, 6)
7201 }
7202 ///Bit 7 - Force Output Compare A
7203 #[inline(always)]
7204 pub fn foc0a(&mut self) -> FOC0A_W<'_, TCCR0B_SPEC> {
7205 FOC0A_W::new(self, 7)
7206 }
7207 }
7208 /**Timer/Counter Control Register B
7209
7210You can [`read`](crate::Reg::read) this register and get [`tccr0b::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tccr0b::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
7211 pub struct TCCR0B_SPEC;
7212 impl crate::RegisterSpec for TCCR0B_SPEC {
7213 type Ux = u8;
7214 }
7215 ///`read()` method returns [`tccr0b::R`](R) reader structure
7216 impl crate::Readable for TCCR0B_SPEC {}
7217 ///`write(|w| ..)` method takes [`tccr0b::W`](W) writer structure
7218 impl crate::Writable for TCCR0B_SPEC {
7219 type Safety = crate::Unsafe;
7220 }
7221 ///`reset()` method sets TCCR0B to value 0
7222 impl crate::Resettable for TCCR0B_SPEC {}
7223 }
7224 /**TCNT0 (rw) register accessor: Timer/Counter0
7225
7226You can [`read`](crate::Reg::read) this register and get [`tcnt0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcnt0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
7227
7228For information about available fields see [`mod@tcnt0`] module*/
7229 pub type TCNT0 = crate::Reg<tcnt0::TCNT0_SPEC>;
7230 ///Timer/Counter0
7231 pub mod tcnt0 {
7232 ///Register `TCNT0` reader
7233 pub type R = crate::R<TCNT0_SPEC>;
7234 ///Register `TCNT0` writer
7235 pub type W = crate::W<TCNT0_SPEC>;
7236 impl core::fmt::Debug for R {
7237 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
7238 write!(f, "{}", self.bits())
7239 }
7240 }
7241 impl W {}
7242 /**Timer/Counter0
7243
7244You can [`read`](crate::Reg::read) this register and get [`tcnt0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcnt0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
7245 pub struct TCNT0_SPEC;
7246 impl crate::RegisterSpec for TCNT0_SPEC {
7247 type Ux = u8;
7248 }
7249 ///`read()` method returns [`tcnt0::R`](R) reader structure
7250 impl crate::Readable for TCNT0_SPEC {}
7251 ///`write(|w| ..)` method takes [`tcnt0::W`](W) writer structure
7252 impl crate::Writable for TCNT0_SPEC {
7253 type Safety = crate::Safe;
7254 }
7255 ///`reset()` method sets TCNT0 to value 0
7256 impl crate::Resettable for TCNT0_SPEC {}
7257 }
7258 /**TIFR0 (rw) register accessor: Timer/Counter0 Interrupt Flag register
7259
7260You can [`read`](crate::Reg::read) this register and get [`tifr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tifr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
7261
7262For information about available fields see [`mod@tifr0`] module*/
7263 pub type TIFR0 = crate::Reg<tifr0::TIFR0_SPEC>;
7264 ///Timer/Counter0 Interrupt Flag register
7265 pub mod tifr0 {
7266 ///Register `TIFR0` reader
7267 pub type R = crate::R<TIFR0_SPEC>;
7268 ///Register `TIFR0` writer
7269 pub type W = crate::W<TIFR0_SPEC>;
7270 ///Field `TOV0` reader - Timer/Counter0 Overflow Flag
7271 pub type TOV0_R = crate::BitReader;
7272 ///Field `TOV0` writer - Timer/Counter0 Overflow Flag
7273 pub type TOV0_W<'a, REG> = crate::BitWriter<'a, REG>;
7274 ///Field `OCF0A` reader - Timer/Counter0 Output Compare Flag 0A
7275 pub type OCF0A_R = crate::BitReader;
7276 ///Field `OCF0A` writer - Timer/Counter0 Output Compare Flag 0A
7277 pub type OCF0A_W<'a, REG> = crate::BitWriter<'a, REG>;
7278 ///Field `OCF0B` reader - Timer/Counter0 Output Compare Flag 0B
7279 pub type OCF0B_R = crate::BitReader;
7280 ///Field `OCF0B` writer - Timer/Counter0 Output Compare Flag 0B
7281 pub type OCF0B_W<'a, REG> = crate::BitWriter<'a, REG>;
7282 impl R {
7283 ///Bit 0 - Timer/Counter0 Overflow Flag
7284 #[inline(always)]
7285 pub fn tov0(&self) -> TOV0_R {
7286 TOV0_R::new((self.bits & 1) != 0)
7287 }
7288 ///Bit 1 - Timer/Counter0 Output Compare Flag 0A
7289 #[inline(always)]
7290 pub fn ocf0a(&self) -> OCF0A_R {
7291 OCF0A_R::new(((self.bits >> 1) & 1) != 0)
7292 }
7293 ///Bit 2 - Timer/Counter0 Output Compare Flag 0B
7294 #[inline(always)]
7295 pub fn ocf0b(&self) -> OCF0B_R {
7296 OCF0B_R::new(((self.bits >> 2) & 1) != 0)
7297 }
7298 }
7299 impl W {
7300 ///Bit 0 - Timer/Counter0 Overflow Flag
7301 #[inline(always)]
7302 pub fn tov0(&mut self) -> TOV0_W<'_, TIFR0_SPEC> {
7303 TOV0_W::new(self, 0)
7304 }
7305 ///Bit 1 - Timer/Counter0 Output Compare Flag 0A
7306 #[inline(always)]
7307 pub fn ocf0a(&mut self) -> OCF0A_W<'_, TIFR0_SPEC> {
7308 OCF0A_W::new(self, 1)
7309 }
7310 ///Bit 2 - Timer/Counter0 Output Compare Flag 0B
7311 #[inline(always)]
7312 pub fn ocf0b(&mut self) -> OCF0B_W<'_, TIFR0_SPEC> {
7313 OCF0B_W::new(self, 2)
7314 }
7315 }
7316 /**Timer/Counter0 Interrupt Flag register
7317
7318You can [`read`](crate::Reg::read) this register and get [`tifr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tifr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
7319 pub struct TIFR0_SPEC;
7320 impl crate::RegisterSpec for TIFR0_SPEC {
7321 type Ux = u8;
7322 }
7323 ///`read()` method returns [`tifr0::R`](R) reader structure
7324 impl crate::Readable for TIFR0_SPEC {}
7325 ///`write(|w| ..)` method takes [`tifr0::W`](W) writer structure
7326 impl crate::Writable for TIFR0_SPEC {
7327 type Safety = crate::Unsafe;
7328 }
7329 ///`reset()` method sets TIFR0 to value 0
7330 impl crate::Resettable for TIFR0_SPEC {}
7331 }
7332 /**TIMSK0 (rw) register accessor: Timer/Counter0 Interrupt Mask Register
7333
7334You can [`read`](crate::Reg::read) this register and get [`timsk0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timsk0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
7335
7336For information about available fields see [`mod@timsk0`] module*/
7337 pub type TIMSK0 = crate::Reg<timsk0::TIMSK0_SPEC>;
7338 ///Timer/Counter0 Interrupt Mask Register
7339 pub mod timsk0 {
7340 ///Register `TIMSK0` reader
7341 pub type R = crate::R<TIMSK0_SPEC>;
7342 ///Register `TIMSK0` writer
7343 pub type W = crate::W<TIMSK0_SPEC>;
7344 ///Field `TOIE0` reader - Timer/Counter0 Overflow Interrupt Enable
7345 pub type TOIE0_R = crate::BitReader;
7346 ///Field `TOIE0` writer - Timer/Counter0 Overflow Interrupt Enable
7347 pub type TOIE0_W<'a, REG> = crate::BitWriter<'a, REG>;
7348 ///Field `OCIE0A` reader - Timer/Counter0 Output Compare Match A Interrupt Enable
7349 pub type OCIE0A_R = crate::BitReader;
7350 ///Field `OCIE0A` writer - Timer/Counter0 Output Compare Match A Interrupt Enable
7351 pub type OCIE0A_W<'a, REG> = crate::BitWriter<'a, REG>;
7352 ///Field `OCIE0B` reader - Timer/Counter0 Output Compare Match B Interrupt Enable
7353 pub type OCIE0B_R = crate::BitReader;
7354 ///Field `OCIE0B` writer - Timer/Counter0 Output Compare Match B Interrupt Enable
7355 pub type OCIE0B_W<'a, REG> = crate::BitWriter<'a, REG>;
7356 impl R {
7357 ///Bit 0 - Timer/Counter0 Overflow Interrupt Enable
7358 #[inline(always)]
7359 pub fn toie0(&self) -> TOIE0_R {
7360 TOIE0_R::new((self.bits & 1) != 0)
7361 }
7362 ///Bit 1 - Timer/Counter0 Output Compare Match A Interrupt Enable
7363 #[inline(always)]
7364 pub fn ocie0a(&self) -> OCIE0A_R {
7365 OCIE0A_R::new(((self.bits >> 1) & 1) != 0)
7366 }
7367 ///Bit 2 - Timer/Counter0 Output Compare Match B Interrupt Enable
7368 #[inline(always)]
7369 pub fn ocie0b(&self) -> OCIE0B_R {
7370 OCIE0B_R::new(((self.bits >> 2) & 1) != 0)
7371 }
7372 }
7373 impl W {
7374 ///Bit 0 - Timer/Counter0 Overflow Interrupt Enable
7375 #[inline(always)]
7376 pub fn toie0(&mut self) -> TOIE0_W<'_, TIMSK0_SPEC> {
7377 TOIE0_W::new(self, 0)
7378 }
7379 ///Bit 1 - Timer/Counter0 Output Compare Match A Interrupt Enable
7380 #[inline(always)]
7381 pub fn ocie0a(&mut self) -> OCIE0A_W<'_, TIMSK0_SPEC> {
7382 OCIE0A_W::new(self, 1)
7383 }
7384 ///Bit 2 - Timer/Counter0 Output Compare Match B Interrupt Enable
7385 #[inline(always)]
7386 pub fn ocie0b(&mut self) -> OCIE0B_W<'_, TIMSK0_SPEC> {
7387 OCIE0B_W::new(self, 2)
7388 }
7389 }
7390 /**Timer/Counter0 Interrupt Mask Register
7391
7392You can [`read`](crate::Reg::read) this register and get [`timsk0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timsk0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
7393 pub struct TIMSK0_SPEC;
7394 impl crate::RegisterSpec for TIMSK0_SPEC {
7395 type Ux = u8;
7396 }
7397 ///`read()` method returns [`timsk0::R`](R) reader structure
7398 impl crate::Readable for TIMSK0_SPEC {}
7399 ///`write(|w| ..)` method takes [`timsk0::W`](W) writer structure
7400 impl crate::Writable for TIMSK0_SPEC {
7401 type Safety = crate::Unsafe;
7402 }
7403 ///`reset()` method sets TIMSK0 to value 0
7404 impl crate::Resettable for TIMSK0_SPEC {}
7405 }
7406}
7407///Timer/Counter, 16-bit
7408pub type TC1 = crate::Periph<tc1::RegisterBlock, 0x36>;
7409impl core::fmt::Debug for TC1 {
7410 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
7411 f.debug_struct("TC1").finish()
7412 }
7413}
7414///Timer/Counter, 16-bit
7415pub mod tc1 {
7416 #[repr(C)]
7417 ///Register block
7418 pub struct RegisterBlock {
7419 tifr1: TIFR1,
7420 _reserved1: [u8; 0x0c],
7421 gtccr: GTCCR,
7422 _reserved2: [u8; 0x2b],
7423 timsk1: TIMSK1,
7424 _reserved3: [u8; 0x10],
7425 tccr1a: TCCR1A,
7426 tccr1b: TCCR1B,
7427 tccr1c: TCCR1C,
7428 _reserved6: [u8; 0x01],
7429 tcnt1: TCNT1,
7430 icr1: ICR1,
7431 ocr1a: OCR1A,
7432 ocr1b: OCR1B,
7433 }
7434 impl RegisterBlock {
7435 ///0x00 - Timer/Counter Interrupt Flag register
7436 #[inline(always)]
7437 pub const fn tifr1(&self) -> &TIFR1 {
7438 &self.tifr1
7439 }
7440 ///0x0d - General Timer/Counter Control Register
7441 #[inline(always)]
7442 pub const fn gtccr(&self) -> >CCR {
7443 &self.gtccr
7444 }
7445 ///0x39 - Timer/Counter Interrupt Mask Register
7446 #[inline(always)]
7447 pub const fn timsk1(&self) -> &TIMSK1 {
7448 &self.timsk1
7449 }
7450 ///0x4a - Timer/Counter1 Control Register A
7451 #[inline(always)]
7452 pub const fn tccr1a(&self) -> &TCCR1A {
7453 &self.tccr1a
7454 }
7455 ///0x4b - Timer/Counter1 Control Register B
7456 #[inline(always)]
7457 pub const fn tccr1b(&self) -> &TCCR1B {
7458 &self.tccr1b
7459 }
7460 ///0x4c - Timer/Counter1 Control Register C
7461 #[inline(always)]
7462 pub const fn tccr1c(&self) -> &TCCR1C {
7463 &self.tccr1c
7464 }
7465 ///0x4e - Timer/Counter1 Bytes
7466 #[inline(always)]
7467 pub const fn tcnt1(&self) -> &TCNT1 {
7468 &self.tcnt1
7469 }
7470 ///0x50 - Timer/Counter1 Input Capture Register Bytes
7471 #[inline(always)]
7472 pub const fn icr1(&self) -> &ICR1 {
7473 &self.icr1
7474 }
7475 ///0x52 - Timer/Counter1 Output Compare Register Bytes
7476 #[inline(always)]
7477 pub const fn ocr1a(&self) -> &OCR1A {
7478 &self.ocr1a
7479 }
7480 ///0x54 - Timer/Counter1 Output Compare Register Bytes
7481 #[inline(always)]
7482 pub const fn ocr1b(&self) -> &OCR1B {
7483 &self.ocr1b
7484 }
7485 }
7486 /**GTCCR (rw) register accessor: General Timer/Counter Control Register
7487
7488You can [`read`](crate::Reg::read) this register and get [`gtccr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gtccr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
7489
7490For information about available fields see [`mod@gtccr`] module*/
7491 pub type GTCCR = crate::Reg<gtccr::GTCCR_SPEC>;
7492 ///General Timer/Counter Control Register
7493 pub mod gtccr {
7494 ///Register `GTCCR` reader
7495 pub type R = crate::R<GTCCR_SPEC>;
7496 ///Register `GTCCR` writer
7497 pub type W = crate::W<GTCCR_SPEC>;
7498 ///Field `PSRSYNC` reader - Prescaler Reset Timer/Counter1 and Timer/Counter0
7499 pub type PSRSYNC_R = crate::BitReader;
7500 ///Field `PSRSYNC` writer - Prescaler Reset Timer/Counter1 and Timer/Counter0
7501 pub type PSRSYNC_W<'a, REG> = crate::BitWriter<'a, REG>;
7502 ///Field `TSM` reader - Timer/Counter Synchronization Mode
7503 pub type TSM_R = crate::BitReader;
7504 ///Field `TSM` writer - Timer/Counter Synchronization Mode
7505 pub type TSM_W<'a, REG> = crate::BitWriter<'a, REG>;
7506 impl R {
7507 ///Bit 0 - Prescaler Reset Timer/Counter1 and Timer/Counter0
7508 #[inline(always)]
7509 pub fn psrsync(&self) -> PSRSYNC_R {
7510 PSRSYNC_R::new((self.bits & 1) != 0)
7511 }
7512 ///Bit 7 - Timer/Counter Synchronization Mode
7513 #[inline(always)]
7514 pub fn tsm(&self) -> TSM_R {
7515 TSM_R::new(((self.bits >> 7) & 1) != 0)
7516 }
7517 }
7518 impl W {
7519 ///Bit 0 - Prescaler Reset Timer/Counter1 and Timer/Counter0
7520 #[inline(always)]
7521 pub fn psrsync(&mut self) -> PSRSYNC_W<'_, GTCCR_SPEC> {
7522 PSRSYNC_W::new(self, 0)
7523 }
7524 ///Bit 7 - Timer/Counter Synchronization Mode
7525 #[inline(always)]
7526 pub fn tsm(&mut self) -> TSM_W<'_, GTCCR_SPEC> {
7527 TSM_W::new(self, 7)
7528 }
7529 }
7530 /**General Timer/Counter Control Register
7531
7532You can [`read`](crate::Reg::read) this register and get [`gtccr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gtccr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
7533 pub struct GTCCR_SPEC;
7534 impl crate::RegisterSpec for GTCCR_SPEC {
7535 type Ux = u8;
7536 }
7537 ///`read()` method returns [`gtccr::R`](R) reader structure
7538 impl crate::Readable for GTCCR_SPEC {}
7539 ///`write(|w| ..)` method takes [`gtccr::W`](W) writer structure
7540 impl crate::Writable for GTCCR_SPEC {
7541 type Safety = crate::Unsafe;
7542 }
7543 ///`reset()` method sets GTCCR to value 0
7544 impl crate::Resettable for GTCCR_SPEC {}
7545 }
7546 /**ICR1 (rw) register accessor: Timer/Counter1 Input Capture Register Bytes
7547
7548You can [`read`](crate::Reg::read) this register and get [`icr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
7549
7550For information about available fields see [`mod@icr1`] module*/
7551 pub type ICR1 = crate::Reg<icr1::ICR1_SPEC>;
7552 ///Timer/Counter1 Input Capture Register Bytes
7553 pub mod icr1 {
7554 ///Register `ICR1` reader
7555 pub type R = crate::R<ICR1_SPEC>;
7556 ///Register `ICR1` writer
7557 pub type W = crate::W<ICR1_SPEC>;
7558 impl core::fmt::Debug for R {
7559 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
7560 write!(f, "{}", self.bits())
7561 }
7562 }
7563 impl W {}
7564 /**Timer/Counter1 Input Capture Register Bytes
7565
7566You can [`read`](crate::Reg::read) this register and get [`icr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
7567 pub struct ICR1_SPEC;
7568 impl crate::RegisterSpec for ICR1_SPEC {
7569 type Ux = u16;
7570 }
7571 ///`read()` method returns [`icr1::R`](R) reader structure
7572 impl crate::Readable for ICR1_SPEC {}
7573 ///`write(|w| ..)` method takes [`icr1::W`](W) writer structure
7574 impl crate::Writable for ICR1_SPEC {
7575 type Safety = crate::Safe;
7576 }
7577 ///`reset()` method sets ICR1 to value 0
7578 impl crate::Resettable for ICR1_SPEC {}
7579 }
7580 /**OCR1A (rw) register accessor: Timer/Counter1 Output Compare Register Bytes
7581
7582You can [`read`](crate::Reg::read) this register and get [`ocr1a::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ocr1a::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
7583
7584For information about available fields see [`mod@ocr1a`] module*/
7585 pub type OCR1A = crate::Reg<ocr1a::OCR1A_SPEC>;
7586 ///Timer/Counter1 Output Compare Register Bytes
7587 pub mod ocr1a {
7588 ///Register `OCR1A` reader
7589 pub type R = crate::R<OCR1A_SPEC>;
7590 ///Register `OCR1A` writer
7591 pub type W = crate::W<OCR1A_SPEC>;
7592 impl core::fmt::Debug for R {
7593 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
7594 write!(f, "{}", self.bits())
7595 }
7596 }
7597 impl W {}
7598 /**Timer/Counter1 Output Compare Register Bytes
7599
7600You can [`read`](crate::Reg::read) this register and get [`ocr1a::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ocr1a::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
7601 pub struct OCR1A_SPEC;
7602 impl crate::RegisterSpec for OCR1A_SPEC {
7603 type Ux = u16;
7604 }
7605 ///`read()` method returns [`ocr1a::R`](R) reader structure
7606 impl crate::Readable for OCR1A_SPEC {}
7607 ///`write(|w| ..)` method takes [`ocr1a::W`](W) writer structure
7608 impl crate::Writable for OCR1A_SPEC {
7609 type Safety = crate::Safe;
7610 }
7611 ///`reset()` method sets OCR1A to value 0
7612 impl crate::Resettable for OCR1A_SPEC {}
7613 }
7614 /**OCR1B (rw) register accessor: Timer/Counter1 Output Compare Register Bytes
7615
7616You can [`read`](crate::Reg::read) this register and get [`ocr1b::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ocr1b::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
7617
7618For information about available fields see [`mod@ocr1b`] module*/
7619 pub type OCR1B = crate::Reg<ocr1b::OCR1B_SPEC>;
7620 ///Timer/Counter1 Output Compare Register Bytes
7621 pub mod ocr1b {
7622 ///Register `OCR1B` reader
7623 pub type R = crate::R<OCR1B_SPEC>;
7624 ///Register `OCR1B` writer
7625 pub type W = crate::W<OCR1B_SPEC>;
7626 impl core::fmt::Debug for R {
7627 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
7628 write!(f, "{}", self.bits())
7629 }
7630 }
7631 impl W {}
7632 /**Timer/Counter1 Output Compare Register Bytes
7633
7634You can [`read`](crate::Reg::read) this register and get [`ocr1b::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ocr1b::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
7635 pub struct OCR1B_SPEC;
7636 impl crate::RegisterSpec for OCR1B_SPEC {
7637 type Ux = u16;
7638 }
7639 ///`read()` method returns [`ocr1b::R`](R) reader structure
7640 impl crate::Readable for OCR1B_SPEC {}
7641 ///`write(|w| ..)` method takes [`ocr1b::W`](W) writer structure
7642 impl crate::Writable for OCR1B_SPEC {
7643 type Safety = crate::Safe;
7644 }
7645 ///`reset()` method sets OCR1B to value 0
7646 impl crate::Resettable for OCR1B_SPEC {}
7647 }
7648 /**TCCR1A (rw) register accessor: Timer/Counter1 Control Register A
7649
7650You can [`read`](crate::Reg::read) this register and get [`tccr1a::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tccr1a::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
7651
7652For information about available fields see [`mod@tccr1a`] module*/
7653 pub type TCCR1A = crate::Reg<tccr1a::TCCR1A_SPEC>;
7654 ///Timer/Counter1 Control Register A
7655 pub mod tccr1a {
7656 ///Register `TCCR1A` reader
7657 pub type R = crate::R<TCCR1A_SPEC>;
7658 ///Register `TCCR1A` writer
7659 pub type W = crate::W<TCCR1A_SPEC>;
7660 ///Field `WGM1` reader - Waveform Generation Mode
7661 pub type WGM1_R = crate::FieldReader;
7662 ///Field `WGM1` writer - Waveform Generation Mode
7663 pub type WGM1_W<'a, REG> = crate::FieldWriter<'a, REG, 2, u8, crate::Safe>;
7664 /**Compare Output Mode 1B, bits
7665
7666Value on reset: 0*/
7667 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
7668 #[repr(u8)]
7669 pub enum COM1B_A {
7670 ///0: Normal port operation, OCix disconnected
7671 DISCONNECTED = 0,
7672 ///1: Toggle OCix on Compare Match (Might depend on WGM)
7673 MATCH_TOGGLE = 1,
7674 ///2: Clear OCix on Compare Match (If PWM is enabled, OCix is set at BOTTOM)
7675 MATCH_CLEAR = 2,
7676 ///3: Set OCix on Compare Match (If PWM is enabled, OCix is cleared at BOTTOM)
7677 MATCH_SET = 3,
7678 }
7679 impl From<COM1B_A> for u8 {
7680 #[inline(always)]
7681 fn from(variant: COM1B_A) -> Self {
7682 variant as _
7683 }
7684 }
7685 impl crate::FieldSpec for COM1B_A {
7686 type Ux = u8;
7687 }
7688 impl crate::IsEnum for COM1B_A {}
7689 ///Field `COM1B` reader - Compare Output Mode 1B, bits
7690 pub type COM1B_R = crate::FieldReader<COM1B_A>;
7691 impl COM1B_R {
7692 ///Get enumerated values variant
7693 #[inline(always)]
7694 pub const fn variant(&self) -> COM1B_A {
7695 match self.bits {
7696 0 => COM1B_A::DISCONNECTED,
7697 1 => COM1B_A::MATCH_TOGGLE,
7698 2 => COM1B_A::MATCH_CLEAR,
7699 3 => COM1B_A::MATCH_SET,
7700 _ => unreachable!(),
7701 }
7702 }
7703 ///Normal port operation, OCix disconnected
7704 #[inline(always)]
7705 pub fn is_disconnected(&self) -> bool {
7706 *self == COM1B_A::DISCONNECTED
7707 }
7708 ///Toggle OCix on Compare Match (Might depend on WGM)
7709 #[inline(always)]
7710 pub fn is_match_toggle(&self) -> bool {
7711 *self == COM1B_A::MATCH_TOGGLE
7712 }
7713 ///Clear OCix on Compare Match (If PWM is enabled, OCix is set at BOTTOM)
7714 #[inline(always)]
7715 pub fn is_match_clear(&self) -> bool {
7716 *self == COM1B_A::MATCH_CLEAR
7717 }
7718 ///Set OCix on Compare Match (If PWM is enabled, OCix is cleared at BOTTOM)
7719 #[inline(always)]
7720 pub fn is_match_set(&self) -> bool {
7721 *self == COM1B_A::MATCH_SET
7722 }
7723 }
7724 ///Field `COM1B` writer - Compare Output Mode 1B, bits
7725 pub type COM1B_W<'a, REG> = crate::FieldWriter<'a, REG, 2, COM1B_A, crate::Safe>;
7726 impl<'a, REG> COM1B_W<'a, REG>
7727 where
7728 REG: crate::Writable + crate::RegisterSpec,
7729 REG::Ux: From<u8>,
7730 {
7731 ///Normal port operation, OCix disconnected
7732 #[inline(always)]
7733 pub fn disconnected(self) -> &'a mut crate::W<REG> {
7734 self.variant(COM1B_A::DISCONNECTED)
7735 }
7736 ///Toggle OCix on Compare Match (Might depend on WGM)
7737 #[inline(always)]
7738 pub fn match_toggle(self) -> &'a mut crate::W<REG> {
7739 self.variant(COM1B_A::MATCH_TOGGLE)
7740 }
7741 ///Clear OCix on Compare Match (If PWM is enabled, OCix is set at BOTTOM)
7742 #[inline(always)]
7743 pub fn match_clear(self) -> &'a mut crate::W<REG> {
7744 self.variant(COM1B_A::MATCH_CLEAR)
7745 }
7746 ///Set OCix on Compare Match (If PWM is enabled, OCix is cleared at BOTTOM)
7747 #[inline(always)]
7748 pub fn match_set(self) -> &'a mut crate::W<REG> {
7749 self.variant(COM1B_A::MATCH_SET)
7750 }
7751 }
7752 ///Field `COM1A` reader - Compare Output Mode 1A, bits
7753 pub use COM1B_R as COM1A_R;
7754 ///Field `COM1A` writer - Compare Output Mode 1A, bits
7755 pub use COM1B_W as COM1A_W;
7756 impl R {
7757 ///Bits 0:1 - Waveform Generation Mode
7758 #[inline(always)]
7759 pub fn wgm1(&self) -> WGM1_R {
7760 WGM1_R::new(self.bits & 3)
7761 }
7762 ///Bits 4:5 - Compare Output Mode 1B, bits
7763 #[inline(always)]
7764 pub fn com1b(&self) -> COM1B_R {
7765 COM1B_R::new((self.bits >> 4) & 3)
7766 }
7767 ///Bits 6:7 - Compare Output Mode 1A, bits
7768 #[inline(always)]
7769 pub fn com1a(&self) -> COM1A_R {
7770 COM1A_R::new((self.bits >> 6) & 3)
7771 }
7772 }
7773 impl W {
7774 ///Bits 0:1 - Waveform Generation Mode
7775 #[inline(always)]
7776 pub fn wgm1(&mut self) -> WGM1_W<'_, TCCR1A_SPEC> {
7777 WGM1_W::new(self, 0)
7778 }
7779 ///Bits 4:5 - Compare Output Mode 1B, bits
7780 #[inline(always)]
7781 pub fn com1b(&mut self) -> COM1B_W<'_, TCCR1A_SPEC> {
7782 COM1B_W::new(self, 4)
7783 }
7784 ///Bits 6:7 - Compare Output Mode 1A, bits
7785 #[inline(always)]
7786 pub fn com1a(&mut self) -> COM1A_W<'_, TCCR1A_SPEC> {
7787 COM1A_W::new(self, 6)
7788 }
7789 }
7790 /**Timer/Counter1 Control Register A
7791
7792You can [`read`](crate::Reg::read) this register and get [`tccr1a::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tccr1a::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
7793 pub struct TCCR1A_SPEC;
7794 impl crate::RegisterSpec for TCCR1A_SPEC {
7795 type Ux = u8;
7796 }
7797 ///`read()` method returns [`tccr1a::R`](R) reader structure
7798 impl crate::Readable for TCCR1A_SPEC {}
7799 ///`write(|w| ..)` method takes [`tccr1a::W`](W) writer structure
7800 impl crate::Writable for TCCR1A_SPEC {
7801 type Safety = crate::Unsafe;
7802 }
7803 ///`reset()` method sets TCCR1A to value 0
7804 impl crate::Resettable for TCCR1A_SPEC {}
7805 }
7806 /**TCCR1B (rw) register accessor: Timer/Counter1 Control Register B
7807
7808You can [`read`](crate::Reg::read) this register and get [`tccr1b::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tccr1b::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
7809
7810For information about available fields see [`mod@tccr1b`] module*/
7811 pub type TCCR1B = crate::Reg<tccr1b::TCCR1B_SPEC>;
7812 ///Timer/Counter1 Control Register B
7813 pub mod tccr1b {
7814 ///Register `TCCR1B` reader
7815 pub type R = crate::R<TCCR1B_SPEC>;
7816 ///Register `TCCR1B` writer
7817 pub type W = crate::W<TCCR1B_SPEC>;
7818 /**Prescaler source of Timer/Counter 1
7819
7820Value on reset: 0*/
7821 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
7822 #[repr(u8)]
7823 pub enum CS1_A {
7824 ///0: No clock source (Timer/Counter stopped)
7825 NO_CLOCK = 0,
7826 ///1: Running, No Prescaling
7827 DIRECT = 1,
7828 ///2: Running, CLK/8
7829 PRESCALE_8 = 2,
7830 ///3: Running, CLK/64
7831 PRESCALE_64 = 3,
7832 ///4: Running, CLK/256
7833 PRESCALE_256 = 4,
7834 ///5: Running, CLK/1024
7835 PRESCALE_1024 = 5,
7836 ///6: Running, ExtClk Tx Falling Edge
7837 EXT_FALLING = 6,
7838 ///7: Running, ExtClk Tx Rising Edge
7839 EXT_RISING = 7,
7840 }
7841 impl From<CS1_A> for u8 {
7842 #[inline(always)]
7843 fn from(variant: CS1_A) -> Self {
7844 variant as _
7845 }
7846 }
7847 impl crate::FieldSpec for CS1_A {
7848 type Ux = u8;
7849 }
7850 impl crate::IsEnum for CS1_A {}
7851 ///Field `CS1` reader - Prescaler source of Timer/Counter 1
7852 pub type CS1_R = crate::FieldReader<CS1_A>;
7853 impl CS1_R {
7854 ///Get enumerated values variant
7855 #[inline(always)]
7856 pub const fn variant(&self) -> CS1_A {
7857 match self.bits {
7858 0 => CS1_A::NO_CLOCK,
7859 1 => CS1_A::DIRECT,
7860 2 => CS1_A::PRESCALE_8,
7861 3 => CS1_A::PRESCALE_64,
7862 4 => CS1_A::PRESCALE_256,
7863 5 => CS1_A::PRESCALE_1024,
7864 6 => CS1_A::EXT_FALLING,
7865 7 => CS1_A::EXT_RISING,
7866 _ => unreachable!(),
7867 }
7868 }
7869 ///No clock source (Timer/Counter stopped)
7870 #[inline(always)]
7871 pub fn is_no_clock(&self) -> bool {
7872 *self == CS1_A::NO_CLOCK
7873 }
7874 ///Running, No Prescaling
7875 #[inline(always)]
7876 pub fn is_direct(&self) -> bool {
7877 *self == CS1_A::DIRECT
7878 }
7879 ///Running, CLK/8
7880 #[inline(always)]
7881 pub fn is_prescale_8(&self) -> bool {
7882 *self == CS1_A::PRESCALE_8
7883 }
7884 ///Running, CLK/64
7885 #[inline(always)]
7886 pub fn is_prescale_64(&self) -> bool {
7887 *self == CS1_A::PRESCALE_64
7888 }
7889 ///Running, CLK/256
7890 #[inline(always)]
7891 pub fn is_prescale_256(&self) -> bool {
7892 *self == CS1_A::PRESCALE_256
7893 }
7894 ///Running, CLK/1024
7895 #[inline(always)]
7896 pub fn is_prescale_1024(&self) -> bool {
7897 *self == CS1_A::PRESCALE_1024
7898 }
7899 ///Running, ExtClk Tx Falling Edge
7900 #[inline(always)]
7901 pub fn is_ext_falling(&self) -> bool {
7902 *self == CS1_A::EXT_FALLING
7903 }
7904 ///Running, ExtClk Tx Rising Edge
7905 #[inline(always)]
7906 pub fn is_ext_rising(&self) -> bool {
7907 *self == CS1_A::EXT_RISING
7908 }
7909 }
7910 ///Field `CS1` writer - Prescaler source of Timer/Counter 1
7911 pub type CS1_W<'a, REG> = crate::FieldWriter<'a, REG, 3, CS1_A, crate::Safe>;
7912 impl<'a, REG> CS1_W<'a, REG>
7913 where
7914 REG: crate::Writable + crate::RegisterSpec,
7915 REG::Ux: From<u8>,
7916 {
7917 ///No clock source (Timer/Counter stopped)
7918 #[inline(always)]
7919 pub fn no_clock(self) -> &'a mut crate::W<REG> {
7920 self.variant(CS1_A::NO_CLOCK)
7921 }
7922 ///Running, No Prescaling
7923 #[inline(always)]
7924 pub fn direct(self) -> &'a mut crate::W<REG> {
7925 self.variant(CS1_A::DIRECT)
7926 }
7927 ///Running, CLK/8
7928 #[inline(always)]
7929 pub fn prescale_8(self) -> &'a mut crate::W<REG> {
7930 self.variant(CS1_A::PRESCALE_8)
7931 }
7932 ///Running, CLK/64
7933 #[inline(always)]
7934 pub fn prescale_64(self) -> &'a mut crate::W<REG> {
7935 self.variant(CS1_A::PRESCALE_64)
7936 }
7937 ///Running, CLK/256
7938 #[inline(always)]
7939 pub fn prescale_256(self) -> &'a mut crate::W<REG> {
7940 self.variant(CS1_A::PRESCALE_256)
7941 }
7942 ///Running, CLK/1024
7943 #[inline(always)]
7944 pub fn prescale_1024(self) -> &'a mut crate::W<REG> {
7945 self.variant(CS1_A::PRESCALE_1024)
7946 }
7947 ///Running, ExtClk Tx Falling Edge
7948 #[inline(always)]
7949 pub fn ext_falling(self) -> &'a mut crate::W<REG> {
7950 self.variant(CS1_A::EXT_FALLING)
7951 }
7952 ///Running, ExtClk Tx Rising Edge
7953 #[inline(always)]
7954 pub fn ext_rising(self) -> &'a mut crate::W<REG> {
7955 self.variant(CS1_A::EXT_RISING)
7956 }
7957 }
7958 ///Field `WGM1` reader - Waveform Generation Mode
7959 pub type WGM1_R = crate::FieldReader;
7960 ///Field `WGM1` writer - Waveform Generation Mode
7961 pub type WGM1_W<'a, REG> = crate::FieldWriter<'a, REG, 2, u8, crate::Safe>;
7962 ///Field `ICES1` reader - Input Capture 1 Edge Select
7963 pub type ICES1_R = crate::BitReader;
7964 ///Field `ICES1` writer - Input Capture 1 Edge Select
7965 pub type ICES1_W<'a, REG> = crate::BitWriter<'a, REG>;
7966 ///Field `ICNC1` reader - Input Capture 1 Noise Canceler
7967 pub type ICNC1_R = crate::BitReader;
7968 ///Field `ICNC1` writer - Input Capture 1 Noise Canceler
7969 pub type ICNC1_W<'a, REG> = crate::BitWriter<'a, REG>;
7970 impl R {
7971 ///Bits 0:2 - Prescaler source of Timer/Counter 1
7972 #[inline(always)]
7973 pub fn cs1(&self) -> CS1_R {
7974 CS1_R::new(self.bits & 7)
7975 }
7976 ///Bits 3:4 - Waveform Generation Mode
7977 #[inline(always)]
7978 pub fn wgm1(&self) -> WGM1_R {
7979 WGM1_R::new((self.bits >> 3) & 3)
7980 }
7981 ///Bit 6 - Input Capture 1 Edge Select
7982 #[inline(always)]
7983 pub fn ices1(&self) -> ICES1_R {
7984 ICES1_R::new(((self.bits >> 6) & 1) != 0)
7985 }
7986 ///Bit 7 - Input Capture 1 Noise Canceler
7987 #[inline(always)]
7988 pub fn icnc1(&self) -> ICNC1_R {
7989 ICNC1_R::new(((self.bits >> 7) & 1) != 0)
7990 }
7991 }
7992 impl W {
7993 ///Bits 0:2 - Prescaler source of Timer/Counter 1
7994 #[inline(always)]
7995 pub fn cs1(&mut self) -> CS1_W<'_, TCCR1B_SPEC> {
7996 CS1_W::new(self, 0)
7997 }
7998 ///Bits 3:4 - Waveform Generation Mode
7999 #[inline(always)]
8000 pub fn wgm1(&mut self) -> WGM1_W<'_, TCCR1B_SPEC> {
8001 WGM1_W::new(self, 3)
8002 }
8003 ///Bit 6 - Input Capture 1 Edge Select
8004 #[inline(always)]
8005 pub fn ices1(&mut self) -> ICES1_W<'_, TCCR1B_SPEC> {
8006 ICES1_W::new(self, 6)
8007 }
8008 ///Bit 7 - Input Capture 1 Noise Canceler
8009 #[inline(always)]
8010 pub fn icnc1(&mut self) -> ICNC1_W<'_, TCCR1B_SPEC> {
8011 ICNC1_W::new(self, 7)
8012 }
8013 }
8014 /**Timer/Counter1 Control Register B
8015
8016You can [`read`](crate::Reg::read) this register and get [`tccr1b::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tccr1b::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
8017 pub struct TCCR1B_SPEC;
8018 impl crate::RegisterSpec for TCCR1B_SPEC {
8019 type Ux = u8;
8020 }
8021 ///`read()` method returns [`tccr1b::R`](R) reader structure
8022 impl crate::Readable for TCCR1B_SPEC {}
8023 ///`write(|w| ..)` method takes [`tccr1b::W`](W) writer structure
8024 impl crate::Writable for TCCR1B_SPEC {
8025 type Safety = crate::Unsafe;
8026 }
8027 ///`reset()` method sets TCCR1B to value 0
8028 impl crate::Resettable for TCCR1B_SPEC {}
8029 }
8030 /**TCCR1C (rw) register accessor: Timer/Counter1 Control Register C
8031
8032You can [`read`](crate::Reg::read) this register and get [`tccr1c::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tccr1c::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
8033
8034For information about available fields see [`mod@tccr1c`] module*/
8035 pub type TCCR1C = crate::Reg<tccr1c::TCCR1C_SPEC>;
8036 ///Timer/Counter1 Control Register C
8037 pub mod tccr1c {
8038 ///Register `TCCR1C` reader
8039 pub type R = crate::R<TCCR1C_SPEC>;
8040 ///Register `TCCR1C` writer
8041 pub type W = crate::W<TCCR1C_SPEC>;
8042 ///Field `FOC1B` writer - No Description.
8043 pub type FOC1B_W<'a, REG> = crate::BitWriter<'a, REG>;
8044 ///Field `FOC1A` writer - No Description.
8045 pub type FOC1A_W<'a, REG> = crate::BitWriter<'a, REG>;
8046 impl W {
8047 ///Bit 6 - No Description.
8048 #[inline(always)]
8049 pub fn foc1b(&mut self) -> FOC1B_W<'_, TCCR1C_SPEC> {
8050 FOC1B_W::new(self, 6)
8051 }
8052 ///Bit 7 - No Description.
8053 #[inline(always)]
8054 pub fn foc1a(&mut self) -> FOC1A_W<'_, TCCR1C_SPEC> {
8055 FOC1A_W::new(self, 7)
8056 }
8057 }
8058 /**Timer/Counter1 Control Register C
8059
8060You can [`read`](crate::Reg::read) this register and get [`tccr1c::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tccr1c::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
8061 pub struct TCCR1C_SPEC;
8062 impl crate::RegisterSpec for TCCR1C_SPEC {
8063 type Ux = u8;
8064 }
8065 ///`read()` method returns [`tccr1c::R`](R) reader structure
8066 impl crate::Readable for TCCR1C_SPEC {}
8067 ///`write(|w| ..)` method takes [`tccr1c::W`](W) writer structure
8068 impl crate::Writable for TCCR1C_SPEC {
8069 type Safety = crate::Unsafe;
8070 }
8071 ///`reset()` method sets TCCR1C to value 0
8072 impl crate::Resettable for TCCR1C_SPEC {}
8073 }
8074 /**TCNT1 (rw) register accessor: Timer/Counter1 Bytes
8075
8076You can [`read`](crate::Reg::read) this register and get [`tcnt1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcnt1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
8077
8078For information about available fields see [`mod@tcnt1`] module*/
8079 pub type TCNT1 = crate::Reg<tcnt1::TCNT1_SPEC>;
8080 ///Timer/Counter1 Bytes
8081 pub mod tcnt1 {
8082 ///Register `TCNT1` reader
8083 pub type R = crate::R<TCNT1_SPEC>;
8084 ///Register `TCNT1` writer
8085 pub type W = crate::W<TCNT1_SPEC>;
8086 impl core::fmt::Debug for R {
8087 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
8088 write!(f, "{}", self.bits())
8089 }
8090 }
8091 impl W {}
8092 /**Timer/Counter1 Bytes
8093
8094You can [`read`](crate::Reg::read) this register and get [`tcnt1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcnt1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
8095 pub struct TCNT1_SPEC;
8096 impl crate::RegisterSpec for TCNT1_SPEC {
8097 type Ux = u16;
8098 }
8099 ///`read()` method returns [`tcnt1::R`](R) reader structure
8100 impl crate::Readable for TCNT1_SPEC {}
8101 ///`write(|w| ..)` method takes [`tcnt1::W`](W) writer structure
8102 impl crate::Writable for TCNT1_SPEC {
8103 type Safety = crate::Safe;
8104 }
8105 ///`reset()` method sets TCNT1 to value 0
8106 impl crate::Resettable for TCNT1_SPEC {}
8107 }
8108 /**TIFR1 (rw) register accessor: Timer/Counter Interrupt Flag register
8109
8110You can [`read`](crate::Reg::read) this register and get [`tifr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tifr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
8111
8112For information about available fields see [`mod@tifr1`] module*/
8113 pub type TIFR1 = crate::Reg<tifr1::TIFR1_SPEC>;
8114 ///Timer/Counter Interrupt Flag register
8115 pub mod tifr1 {
8116 ///Register `TIFR1` reader
8117 pub type R = crate::R<TIFR1_SPEC>;
8118 ///Register `TIFR1` writer
8119 pub type W = crate::W<TIFR1_SPEC>;
8120 ///Field `TOV1` reader - Timer/Counter1 Overflow Flag
8121 pub type TOV1_R = crate::BitReader;
8122 ///Field `TOV1` writer - Timer/Counter1 Overflow Flag
8123 pub type TOV1_W<'a, REG> = crate::BitWriter<'a, REG>;
8124 ///Field `OCF1A` reader - Output Compare Flag 1A
8125 pub type OCF1A_R = crate::BitReader;
8126 ///Field `OCF1A` writer - Output Compare Flag 1A
8127 pub type OCF1A_W<'a, REG> = crate::BitWriter<'a, REG>;
8128 ///Field `OCF1B` reader - Output Compare Flag 1B
8129 pub type OCF1B_R = crate::BitReader;
8130 ///Field `OCF1B` writer - Output Compare Flag 1B
8131 pub type OCF1B_W<'a, REG> = crate::BitWriter<'a, REG>;
8132 ///Field `ICF1` reader - Input Capture Flag 1
8133 pub type ICF1_R = crate::BitReader;
8134 ///Field `ICF1` writer - Input Capture Flag 1
8135 pub type ICF1_W<'a, REG> = crate::BitWriter<'a, REG>;
8136 impl R {
8137 ///Bit 0 - Timer/Counter1 Overflow Flag
8138 #[inline(always)]
8139 pub fn tov1(&self) -> TOV1_R {
8140 TOV1_R::new((self.bits & 1) != 0)
8141 }
8142 ///Bit 1 - Output Compare Flag 1A
8143 #[inline(always)]
8144 pub fn ocf1a(&self) -> OCF1A_R {
8145 OCF1A_R::new(((self.bits >> 1) & 1) != 0)
8146 }
8147 ///Bit 2 - Output Compare Flag 1B
8148 #[inline(always)]
8149 pub fn ocf1b(&self) -> OCF1B_R {
8150 OCF1B_R::new(((self.bits >> 2) & 1) != 0)
8151 }
8152 ///Bit 5 - Input Capture Flag 1
8153 #[inline(always)]
8154 pub fn icf1(&self) -> ICF1_R {
8155 ICF1_R::new(((self.bits >> 5) & 1) != 0)
8156 }
8157 }
8158 impl W {
8159 ///Bit 0 - Timer/Counter1 Overflow Flag
8160 #[inline(always)]
8161 pub fn tov1(&mut self) -> TOV1_W<'_, TIFR1_SPEC> {
8162 TOV1_W::new(self, 0)
8163 }
8164 ///Bit 1 - Output Compare Flag 1A
8165 #[inline(always)]
8166 pub fn ocf1a(&mut self) -> OCF1A_W<'_, TIFR1_SPEC> {
8167 OCF1A_W::new(self, 1)
8168 }
8169 ///Bit 2 - Output Compare Flag 1B
8170 #[inline(always)]
8171 pub fn ocf1b(&mut self) -> OCF1B_W<'_, TIFR1_SPEC> {
8172 OCF1B_W::new(self, 2)
8173 }
8174 ///Bit 5 - Input Capture Flag 1
8175 #[inline(always)]
8176 pub fn icf1(&mut self) -> ICF1_W<'_, TIFR1_SPEC> {
8177 ICF1_W::new(self, 5)
8178 }
8179 }
8180 /**Timer/Counter Interrupt Flag register
8181
8182You can [`read`](crate::Reg::read) this register and get [`tifr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tifr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
8183 pub struct TIFR1_SPEC;
8184 impl crate::RegisterSpec for TIFR1_SPEC {
8185 type Ux = u8;
8186 }
8187 ///`read()` method returns [`tifr1::R`](R) reader structure
8188 impl crate::Readable for TIFR1_SPEC {}
8189 ///`write(|w| ..)` method takes [`tifr1::W`](W) writer structure
8190 impl crate::Writable for TIFR1_SPEC {
8191 type Safety = crate::Unsafe;
8192 }
8193 ///`reset()` method sets TIFR1 to value 0
8194 impl crate::Resettable for TIFR1_SPEC {}
8195 }
8196 /**TIMSK1 (rw) register accessor: Timer/Counter Interrupt Mask Register
8197
8198You can [`read`](crate::Reg::read) this register and get [`timsk1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timsk1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
8199
8200For information about available fields see [`mod@timsk1`] module*/
8201 pub type TIMSK1 = crate::Reg<timsk1::TIMSK1_SPEC>;
8202 ///Timer/Counter Interrupt Mask Register
8203 pub mod timsk1 {
8204 ///Register `TIMSK1` reader
8205 pub type R = crate::R<TIMSK1_SPEC>;
8206 ///Register `TIMSK1` writer
8207 pub type W = crate::W<TIMSK1_SPEC>;
8208 ///Field `TOIE1` reader - Timer/Counter1 Overflow Interrupt Enable
8209 pub type TOIE1_R = crate::BitReader;
8210 ///Field `TOIE1` writer - Timer/Counter1 Overflow Interrupt Enable
8211 pub type TOIE1_W<'a, REG> = crate::BitWriter<'a, REG>;
8212 ///Field `OCIE1A` reader - Timer/Counter1 Output CompareA Match Interrupt Enable
8213 pub type OCIE1A_R = crate::BitReader;
8214 ///Field `OCIE1A` writer - Timer/Counter1 Output CompareA Match Interrupt Enable
8215 pub type OCIE1A_W<'a, REG> = crate::BitWriter<'a, REG>;
8216 ///Field `OCIE1B` reader - Timer/Counter1 Output CompareB Match Interrupt Enable
8217 pub type OCIE1B_R = crate::BitReader;
8218 ///Field `OCIE1B` writer - Timer/Counter1 Output CompareB Match Interrupt Enable
8219 pub type OCIE1B_W<'a, REG> = crate::BitWriter<'a, REG>;
8220 ///Field `ICIE1` reader - Timer/Counter1 Input Capture Interrupt Enable
8221 pub type ICIE1_R = crate::BitReader;
8222 ///Field `ICIE1` writer - Timer/Counter1 Input Capture Interrupt Enable
8223 pub type ICIE1_W<'a, REG> = crate::BitWriter<'a, REG>;
8224 impl R {
8225 ///Bit 0 - Timer/Counter1 Overflow Interrupt Enable
8226 #[inline(always)]
8227 pub fn toie1(&self) -> TOIE1_R {
8228 TOIE1_R::new((self.bits & 1) != 0)
8229 }
8230 ///Bit 1 - Timer/Counter1 Output CompareA Match Interrupt Enable
8231 #[inline(always)]
8232 pub fn ocie1a(&self) -> OCIE1A_R {
8233 OCIE1A_R::new(((self.bits >> 1) & 1) != 0)
8234 }
8235 ///Bit 2 - Timer/Counter1 Output CompareB Match Interrupt Enable
8236 #[inline(always)]
8237 pub fn ocie1b(&self) -> OCIE1B_R {
8238 OCIE1B_R::new(((self.bits >> 2) & 1) != 0)
8239 }
8240 ///Bit 5 - Timer/Counter1 Input Capture Interrupt Enable
8241 #[inline(always)]
8242 pub fn icie1(&self) -> ICIE1_R {
8243 ICIE1_R::new(((self.bits >> 5) & 1) != 0)
8244 }
8245 }
8246 impl W {
8247 ///Bit 0 - Timer/Counter1 Overflow Interrupt Enable
8248 #[inline(always)]
8249 pub fn toie1(&mut self) -> TOIE1_W<'_, TIMSK1_SPEC> {
8250 TOIE1_W::new(self, 0)
8251 }
8252 ///Bit 1 - Timer/Counter1 Output CompareA Match Interrupt Enable
8253 #[inline(always)]
8254 pub fn ocie1a(&mut self) -> OCIE1A_W<'_, TIMSK1_SPEC> {
8255 OCIE1A_W::new(self, 1)
8256 }
8257 ///Bit 2 - Timer/Counter1 Output CompareB Match Interrupt Enable
8258 #[inline(always)]
8259 pub fn ocie1b(&mut self) -> OCIE1B_W<'_, TIMSK1_SPEC> {
8260 OCIE1B_W::new(self, 2)
8261 }
8262 ///Bit 5 - Timer/Counter1 Input Capture Interrupt Enable
8263 #[inline(always)]
8264 pub fn icie1(&mut self) -> ICIE1_W<'_, TIMSK1_SPEC> {
8265 ICIE1_W::new(self, 5)
8266 }
8267 }
8268 /**Timer/Counter Interrupt Mask Register
8269
8270You can [`read`](crate::Reg::read) this register and get [`timsk1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timsk1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
8271 pub struct TIMSK1_SPEC;
8272 impl crate::RegisterSpec for TIMSK1_SPEC {
8273 type Ux = u8;
8274 }
8275 ///`read()` method returns [`timsk1::R`](R) reader structure
8276 impl crate::Readable for TIMSK1_SPEC {}
8277 ///`write(|w| ..)` method takes [`timsk1::W`](W) writer structure
8278 impl crate::Writable for TIMSK1_SPEC {
8279 type Safety = crate::Unsafe;
8280 }
8281 ///`reset()` method sets TIMSK1 to value 0
8282 impl crate::Resettable for TIMSK1_SPEC {}
8283 }
8284}
8285///Timer/Counter, 8-bit Async
8286pub type TC2 = crate::Periph<tc2::RegisterBlock, 0x37>;
8287impl core::fmt::Debug for TC2 {
8288 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
8289 f.debug_struct("TC2").finish()
8290 }
8291}
8292///Timer/Counter, 8-bit Async
8293pub mod tc2 {
8294 #[repr(C)]
8295 ///Register block
8296 pub struct RegisterBlock {
8297 tifr2: TIFR2,
8298 _reserved1: [u8; 0x0b],
8299 gtccr: GTCCR,
8300 _reserved2: [u8; 0x2c],
8301 timsk2: TIMSK2,
8302 _reserved3: [u8; 0x3f],
8303 tccr2a: TCCR2A,
8304 tccr2b: TCCR2B,
8305 tcnt2: TCNT2,
8306 ocr2a: OCR2A,
8307 ocr2b: OCR2B,
8308 _reserved8: [u8; 0x01],
8309 assr: ASSR,
8310 }
8311 impl RegisterBlock {
8312 ///0x00 - Timer/Counter Interrupt Flag Register
8313 #[inline(always)]
8314 pub const fn tifr2(&self) -> &TIFR2 {
8315 &self.tifr2
8316 }
8317 ///0x0c - General Timer Counter Control register
8318 #[inline(always)]
8319 pub const fn gtccr(&self) -> >CCR {
8320 &self.gtccr
8321 }
8322 ///0x39 - Timer/Counter Interrupt Mask register
8323 #[inline(always)]
8324 pub const fn timsk2(&self) -> &TIMSK2 {
8325 &self.timsk2
8326 }
8327 ///0x79 - Timer/Counter2 Control Register A
8328 #[inline(always)]
8329 pub const fn tccr2a(&self) -> &TCCR2A {
8330 &self.tccr2a
8331 }
8332 ///0x7a - Timer/Counter2 Control Register B
8333 #[inline(always)]
8334 pub const fn tccr2b(&self) -> &TCCR2B {
8335 &self.tccr2b
8336 }
8337 ///0x7b - Timer/Counter2
8338 #[inline(always)]
8339 pub const fn tcnt2(&self) -> &TCNT2 {
8340 &self.tcnt2
8341 }
8342 ///0x7c - Timer/Counter2 Output Compare Register A
8343 #[inline(always)]
8344 pub const fn ocr2a(&self) -> &OCR2A {
8345 &self.ocr2a
8346 }
8347 ///0x7d - Timer/Counter2 Output Compare Register B
8348 #[inline(always)]
8349 pub const fn ocr2b(&self) -> &OCR2B {
8350 &self.ocr2b
8351 }
8352 ///0x7f - Asynchronous Status Register
8353 #[inline(always)]
8354 pub const fn assr(&self) -> &ASSR {
8355 &self.assr
8356 }
8357 }
8358 /**ASSR (rw) register accessor: Asynchronous Status Register
8359
8360You can [`read`](crate::Reg::read) this register and get [`assr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`assr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
8361
8362For information about available fields see [`mod@assr`] module*/
8363 pub type ASSR = crate::Reg<assr::ASSR_SPEC>;
8364 ///Asynchronous Status Register
8365 pub mod assr {
8366 ///Register `ASSR` reader
8367 pub type R = crate::R<ASSR_SPEC>;
8368 ///Register `ASSR` writer
8369 pub type W = crate::W<ASSR_SPEC>;
8370 ///Field `TCR2BUB` reader - Timer/Counter Control Register2 Update Busy
8371 pub type TCR2BUB_R = crate::BitReader;
8372 ///Field `TCR2BUB` writer - Timer/Counter Control Register2 Update Busy
8373 pub type TCR2BUB_W<'a, REG> = crate::BitWriter<'a, REG>;
8374 ///Field `TCR2AUB` reader - Timer/Counter Control Register2 Update Busy
8375 pub type TCR2AUB_R = crate::BitReader;
8376 ///Field `TCR2AUB` writer - Timer/Counter Control Register2 Update Busy
8377 pub type TCR2AUB_W<'a, REG> = crate::BitWriter<'a, REG>;
8378 ///Field `OCR2BUB` reader - Output Compare Register 2 Update Busy
8379 pub type OCR2BUB_R = crate::BitReader;
8380 ///Field `OCR2BUB` writer - Output Compare Register 2 Update Busy
8381 pub type OCR2BUB_W<'a, REG> = crate::BitWriter<'a, REG>;
8382 ///Field `OCR2AUB` reader - Output Compare Register2 Update Busy
8383 pub type OCR2AUB_R = crate::BitReader;
8384 ///Field `OCR2AUB` writer - Output Compare Register2 Update Busy
8385 pub type OCR2AUB_W<'a, REG> = crate::BitWriter<'a, REG>;
8386 ///Field `TCN2UB` reader - Timer/Counter2 Update Busy
8387 pub type TCN2UB_R = crate::BitReader;
8388 ///Field `TCN2UB` writer - Timer/Counter2 Update Busy
8389 pub type TCN2UB_W<'a, REG> = crate::BitWriter<'a, REG>;
8390 ///Field `AS2` reader - Asynchronous Timer/Counter2
8391 pub type AS2_R = crate::BitReader;
8392 ///Field `AS2` writer - Asynchronous Timer/Counter2
8393 pub type AS2_W<'a, REG> = crate::BitWriter<'a, REG>;
8394 ///Field `EXCLK` reader - Enable External Clock Input
8395 pub type EXCLK_R = crate::BitReader;
8396 ///Field `EXCLK` writer - Enable External Clock Input
8397 pub type EXCLK_W<'a, REG> = crate::BitWriter<'a, REG>;
8398 impl R {
8399 ///Bit 0 - Timer/Counter Control Register2 Update Busy
8400 #[inline(always)]
8401 pub fn tcr2bub(&self) -> TCR2BUB_R {
8402 TCR2BUB_R::new((self.bits & 1) != 0)
8403 }
8404 ///Bit 1 - Timer/Counter Control Register2 Update Busy
8405 #[inline(always)]
8406 pub fn tcr2aub(&self) -> TCR2AUB_R {
8407 TCR2AUB_R::new(((self.bits >> 1) & 1) != 0)
8408 }
8409 ///Bit 2 - Output Compare Register 2 Update Busy
8410 #[inline(always)]
8411 pub fn ocr2bub(&self) -> OCR2BUB_R {
8412 OCR2BUB_R::new(((self.bits >> 2) & 1) != 0)
8413 }
8414 ///Bit 3 - Output Compare Register2 Update Busy
8415 #[inline(always)]
8416 pub fn ocr2aub(&self) -> OCR2AUB_R {
8417 OCR2AUB_R::new(((self.bits >> 3) & 1) != 0)
8418 }
8419 ///Bit 4 - Timer/Counter2 Update Busy
8420 #[inline(always)]
8421 pub fn tcn2ub(&self) -> TCN2UB_R {
8422 TCN2UB_R::new(((self.bits >> 4) & 1) != 0)
8423 }
8424 ///Bit 5 - Asynchronous Timer/Counter2
8425 #[inline(always)]
8426 pub fn as2(&self) -> AS2_R {
8427 AS2_R::new(((self.bits >> 5) & 1) != 0)
8428 }
8429 ///Bit 6 - Enable External Clock Input
8430 #[inline(always)]
8431 pub fn exclk(&self) -> EXCLK_R {
8432 EXCLK_R::new(((self.bits >> 6) & 1) != 0)
8433 }
8434 }
8435 impl W {
8436 ///Bit 0 - Timer/Counter Control Register2 Update Busy
8437 #[inline(always)]
8438 pub fn tcr2bub(&mut self) -> TCR2BUB_W<'_, ASSR_SPEC> {
8439 TCR2BUB_W::new(self, 0)
8440 }
8441 ///Bit 1 - Timer/Counter Control Register2 Update Busy
8442 #[inline(always)]
8443 pub fn tcr2aub(&mut self) -> TCR2AUB_W<'_, ASSR_SPEC> {
8444 TCR2AUB_W::new(self, 1)
8445 }
8446 ///Bit 2 - Output Compare Register 2 Update Busy
8447 #[inline(always)]
8448 pub fn ocr2bub(&mut self) -> OCR2BUB_W<'_, ASSR_SPEC> {
8449 OCR2BUB_W::new(self, 2)
8450 }
8451 ///Bit 3 - Output Compare Register2 Update Busy
8452 #[inline(always)]
8453 pub fn ocr2aub(&mut self) -> OCR2AUB_W<'_, ASSR_SPEC> {
8454 OCR2AUB_W::new(self, 3)
8455 }
8456 ///Bit 4 - Timer/Counter2 Update Busy
8457 #[inline(always)]
8458 pub fn tcn2ub(&mut self) -> TCN2UB_W<'_, ASSR_SPEC> {
8459 TCN2UB_W::new(self, 4)
8460 }
8461 ///Bit 5 - Asynchronous Timer/Counter2
8462 #[inline(always)]
8463 pub fn as2(&mut self) -> AS2_W<'_, ASSR_SPEC> {
8464 AS2_W::new(self, 5)
8465 }
8466 ///Bit 6 - Enable External Clock Input
8467 #[inline(always)]
8468 pub fn exclk(&mut self) -> EXCLK_W<'_, ASSR_SPEC> {
8469 EXCLK_W::new(self, 6)
8470 }
8471 }
8472 /**Asynchronous Status Register
8473
8474You can [`read`](crate::Reg::read) this register and get [`assr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`assr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
8475 pub struct ASSR_SPEC;
8476 impl crate::RegisterSpec for ASSR_SPEC {
8477 type Ux = u8;
8478 }
8479 ///`read()` method returns [`assr::R`](R) reader structure
8480 impl crate::Readable for ASSR_SPEC {}
8481 ///`write(|w| ..)` method takes [`assr::W`](W) writer structure
8482 impl crate::Writable for ASSR_SPEC {
8483 type Safety = crate::Unsafe;
8484 }
8485 ///`reset()` method sets ASSR to value 0
8486 impl crate::Resettable for ASSR_SPEC {}
8487 }
8488 /**GTCCR (rw) register accessor: General Timer Counter Control register
8489
8490You can [`read`](crate::Reg::read) this register and get [`gtccr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gtccr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
8491
8492For information about available fields see [`mod@gtccr`] module*/
8493 pub type GTCCR = crate::Reg<gtccr::GTCCR_SPEC>;
8494 ///General Timer Counter Control register
8495 pub mod gtccr {
8496 ///Register `GTCCR` reader
8497 pub type R = crate::R<GTCCR_SPEC>;
8498 ///Register `GTCCR` writer
8499 pub type W = crate::W<GTCCR_SPEC>;
8500 ///Field `PSRASY` reader - Prescaler Reset Timer/Counter2
8501 pub type PSRASY_R = crate::BitReader;
8502 ///Field `PSRASY` writer - Prescaler Reset Timer/Counter2
8503 pub type PSRASY_W<'a, REG> = crate::BitWriter<'a, REG>;
8504 ///Field `TSM` reader - Timer/Counter Synchronization Mode
8505 pub type TSM_R = crate::BitReader;
8506 ///Field `TSM` writer - Timer/Counter Synchronization Mode
8507 pub type TSM_W<'a, REG> = crate::BitWriter<'a, REG>;
8508 impl R {
8509 ///Bit 1 - Prescaler Reset Timer/Counter2
8510 #[inline(always)]
8511 pub fn psrasy(&self) -> PSRASY_R {
8512 PSRASY_R::new(((self.bits >> 1) & 1) != 0)
8513 }
8514 ///Bit 7 - Timer/Counter Synchronization Mode
8515 #[inline(always)]
8516 pub fn tsm(&self) -> TSM_R {
8517 TSM_R::new(((self.bits >> 7) & 1) != 0)
8518 }
8519 }
8520 impl W {
8521 ///Bit 1 - Prescaler Reset Timer/Counter2
8522 #[inline(always)]
8523 pub fn psrasy(&mut self) -> PSRASY_W<'_, GTCCR_SPEC> {
8524 PSRASY_W::new(self, 1)
8525 }
8526 ///Bit 7 - Timer/Counter Synchronization Mode
8527 #[inline(always)]
8528 pub fn tsm(&mut self) -> TSM_W<'_, GTCCR_SPEC> {
8529 TSM_W::new(self, 7)
8530 }
8531 }
8532 /**General Timer Counter Control register
8533
8534You can [`read`](crate::Reg::read) this register and get [`gtccr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gtccr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
8535 pub struct GTCCR_SPEC;
8536 impl crate::RegisterSpec for GTCCR_SPEC {
8537 type Ux = u8;
8538 }
8539 ///`read()` method returns [`gtccr::R`](R) reader structure
8540 impl crate::Readable for GTCCR_SPEC {}
8541 ///`write(|w| ..)` method takes [`gtccr::W`](W) writer structure
8542 impl crate::Writable for GTCCR_SPEC {
8543 type Safety = crate::Unsafe;
8544 }
8545 ///`reset()` method sets GTCCR to value 0
8546 impl crate::Resettable for GTCCR_SPEC {}
8547 }
8548 /**OCR2A (rw) register accessor: Timer/Counter2 Output Compare Register A
8549
8550You can [`read`](crate::Reg::read) this register and get [`ocr2a::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ocr2a::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
8551
8552For information about available fields see [`mod@ocr2a`] module*/
8553 pub type OCR2A = crate::Reg<ocr2a::OCR2A_SPEC>;
8554 ///Timer/Counter2 Output Compare Register A
8555 pub mod ocr2a {
8556 ///Register `OCR2A` reader
8557 pub type R = crate::R<OCR2A_SPEC>;
8558 ///Register `OCR2A` writer
8559 pub type W = crate::W<OCR2A_SPEC>;
8560 impl core::fmt::Debug for R {
8561 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
8562 write!(f, "{}", self.bits())
8563 }
8564 }
8565 impl W {}
8566 /**Timer/Counter2 Output Compare Register A
8567
8568You can [`read`](crate::Reg::read) this register and get [`ocr2a::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ocr2a::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
8569 pub struct OCR2A_SPEC;
8570 impl crate::RegisterSpec for OCR2A_SPEC {
8571 type Ux = u8;
8572 }
8573 ///`read()` method returns [`ocr2a::R`](R) reader structure
8574 impl crate::Readable for OCR2A_SPEC {}
8575 ///`write(|w| ..)` method takes [`ocr2a::W`](W) writer structure
8576 impl crate::Writable for OCR2A_SPEC {
8577 type Safety = crate::Safe;
8578 }
8579 ///`reset()` method sets OCR2A to value 0
8580 impl crate::Resettable for OCR2A_SPEC {}
8581 }
8582 /**OCR2B (rw) register accessor: Timer/Counter2 Output Compare Register B
8583
8584You can [`read`](crate::Reg::read) this register and get [`ocr2b::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ocr2b::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
8585
8586For information about available fields see [`mod@ocr2b`] module*/
8587 pub type OCR2B = crate::Reg<ocr2b::OCR2B_SPEC>;
8588 ///Timer/Counter2 Output Compare Register B
8589 pub mod ocr2b {
8590 ///Register `OCR2B` reader
8591 pub type R = crate::R<OCR2B_SPEC>;
8592 ///Register `OCR2B` writer
8593 pub type W = crate::W<OCR2B_SPEC>;
8594 impl core::fmt::Debug for R {
8595 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
8596 write!(f, "{}", self.bits())
8597 }
8598 }
8599 impl W {}
8600 /**Timer/Counter2 Output Compare Register B
8601
8602You can [`read`](crate::Reg::read) this register and get [`ocr2b::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ocr2b::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
8603 pub struct OCR2B_SPEC;
8604 impl crate::RegisterSpec for OCR2B_SPEC {
8605 type Ux = u8;
8606 }
8607 ///`read()` method returns [`ocr2b::R`](R) reader structure
8608 impl crate::Readable for OCR2B_SPEC {}
8609 ///`write(|w| ..)` method takes [`ocr2b::W`](W) writer structure
8610 impl crate::Writable for OCR2B_SPEC {
8611 type Safety = crate::Safe;
8612 }
8613 ///`reset()` method sets OCR2B to value 0
8614 impl crate::Resettable for OCR2B_SPEC {}
8615 }
8616 /**TCCR2A (rw) register accessor: Timer/Counter2 Control Register A
8617
8618You can [`read`](crate::Reg::read) this register and get [`tccr2a::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tccr2a::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
8619
8620For information about available fields see [`mod@tccr2a`] module*/
8621 pub type TCCR2A = crate::Reg<tccr2a::TCCR2A_SPEC>;
8622 ///Timer/Counter2 Control Register A
8623 pub mod tccr2a {
8624 ///Register `TCCR2A` reader
8625 pub type R = crate::R<TCCR2A_SPEC>;
8626 ///Register `TCCR2A` writer
8627 pub type W = crate::W<TCCR2A_SPEC>;
8628 /**Waveform Genration Mode
8629
8630Value on reset: 0*/
8631 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
8632 #[repr(u8)]
8633 pub enum WGM2_A {
8634 ///0: Normal, Top: `0xff`, Update: *Immediate*, Flag: *MAX*
8635 NORMAL_TOP = 0,
8636 ///1: Phase Correct PWM, Top: `0xff`, Update: *TOP*, Flag: *BOTTOM*
8637 PWM_PHASE = 1,
8638 ///2: CTC, Top: *OCRA*, Update: *Immediate*, Flag: *MAX*
8639 CTC = 2,
8640 ///3: Fast PWM, Top: `0xff`, Update: *TOP*, Flag: *MAX*
8641 PWM_FAST = 3,
8642 }
8643 impl From<WGM2_A> for u8 {
8644 #[inline(always)]
8645 fn from(variant: WGM2_A) -> Self {
8646 variant as _
8647 }
8648 }
8649 impl crate::FieldSpec for WGM2_A {
8650 type Ux = u8;
8651 }
8652 impl crate::IsEnum for WGM2_A {}
8653 ///Field `WGM2` reader - Waveform Genration Mode
8654 pub type WGM2_R = crate::FieldReader<WGM2_A>;
8655 impl WGM2_R {
8656 ///Get enumerated values variant
8657 #[inline(always)]
8658 pub const fn variant(&self) -> WGM2_A {
8659 match self.bits {
8660 0 => WGM2_A::NORMAL_TOP,
8661 1 => WGM2_A::PWM_PHASE,
8662 2 => WGM2_A::CTC,
8663 3 => WGM2_A::PWM_FAST,
8664 _ => unreachable!(),
8665 }
8666 }
8667 ///Normal, Top: `0xff`, Update: *Immediate*, Flag: *MAX*
8668 #[inline(always)]
8669 pub fn is_normal_top(&self) -> bool {
8670 *self == WGM2_A::NORMAL_TOP
8671 }
8672 ///Phase Correct PWM, Top: `0xff`, Update: *TOP*, Flag: *BOTTOM*
8673 #[inline(always)]
8674 pub fn is_pwm_phase(&self) -> bool {
8675 *self == WGM2_A::PWM_PHASE
8676 }
8677 ///CTC, Top: *OCRA*, Update: *Immediate*, Flag: *MAX*
8678 #[inline(always)]
8679 pub fn is_ctc(&self) -> bool {
8680 *self == WGM2_A::CTC
8681 }
8682 ///Fast PWM, Top: `0xff`, Update: *TOP*, Flag: *MAX*
8683 #[inline(always)]
8684 pub fn is_pwm_fast(&self) -> bool {
8685 *self == WGM2_A::PWM_FAST
8686 }
8687 }
8688 ///Field `WGM2` writer - Waveform Genration Mode
8689 pub type WGM2_W<'a, REG> = crate::FieldWriter<'a, REG, 2, WGM2_A, crate::Safe>;
8690 impl<'a, REG> WGM2_W<'a, REG>
8691 where
8692 REG: crate::Writable + crate::RegisterSpec,
8693 REG::Ux: From<u8>,
8694 {
8695 ///Normal, Top: `0xff`, Update: *Immediate*, Flag: *MAX*
8696 #[inline(always)]
8697 pub fn normal_top(self) -> &'a mut crate::W<REG> {
8698 self.variant(WGM2_A::NORMAL_TOP)
8699 }
8700 ///Phase Correct PWM, Top: `0xff`, Update: *TOP*, Flag: *BOTTOM*
8701 #[inline(always)]
8702 pub fn pwm_phase(self) -> &'a mut crate::W<REG> {
8703 self.variant(WGM2_A::PWM_PHASE)
8704 }
8705 ///CTC, Top: *OCRA*, Update: *Immediate*, Flag: *MAX*
8706 #[inline(always)]
8707 pub fn ctc(self) -> &'a mut crate::W<REG> {
8708 self.variant(WGM2_A::CTC)
8709 }
8710 ///Fast PWM, Top: `0xff`, Update: *TOP*, Flag: *MAX*
8711 #[inline(always)]
8712 pub fn pwm_fast(self) -> &'a mut crate::W<REG> {
8713 self.variant(WGM2_A::PWM_FAST)
8714 }
8715 }
8716 /**Compare Output B Mode
8717
8718Value on reset: 0*/
8719 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
8720 #[repr(u8)]
8721 pub enum COM2B_A {
8722 ///0: Normal port operation, OCix disconnected
8723 DISCONNECTED = 0,
8724 ///1: Toggle OCix on Compare Match (Might depend on WGM)
8725 MATCH_TOGGLE = 1,
8726 ///2: Clear OCix on Compare Match (If PWM is enabled, OCix is set at TOP)
8727 MATCH_CLEAR = 2,
8728 ///3: Set OCix on Compare Match (If PWM is enabled, OCix is cleared at TOP)
8729 MATCH_SET = 3,
8730 }
8731 impl From<COM2B_A> for u8 {
8732 #[inline(always)]
8733 fn from(variant: COM2B_A) -> Self {
8734 variant as _
8735 }
8736 }
8737 impl crate::FieldSpec for COM2B_A {
8738 type Ux = u8;
8739 }
8740 impl crate::IsEnum for COM2B_A {}
8741 ///Field `COM2B` reader - Compare Output B Mode
8742 pub type COM2B_R = crate::FieldReader<COM2B_A>;
8743 impl COM2B_R {
8744 ///Get enumerated values variant
8745 #[inline(always)]
8746 pub const fn variant(&self) -> COM2B_A {
8747 match self.bits {
8748 0 => COM2B_A::DISCONNECTED,
8749 1 => COM2B_A::MATCH_TOGGLE,
8750 2 => COM2B_A::MATCH_CLEAR,
8751 3 => COM2B_A::MATCH_SET,
8752 _ => unreachable!(),
8753 }
8754 }
8755 ///Normal port operation, OCix disconnected
8756 #[inline(always)]
8757 pub fn is_disconnected(&self) -> bool {
8758 *self == COM2B_A::DISCONNECTED
8759 }
8760 ///Toggle OCix on Compare Match (Might depend on WGM)
8761 #[inline(always)]
8762 pub fn is_match_toggle(&self) -> bool {
8763 *self == COM2B_A::MATCH_TOGGLE
8764 }
8765 ///Clear OCix on Compare Match (If PWM is enabled, OCix is set at TOP)
8766 #[inline(always)]
8767 pub fn is_match_clear(&self) -> bool {
8768 *self == COM2B_A::MATCH_CLEAR
8769 }
8770 ///Set OCix on Compare Match (If PWM is enabled, OCix is cleared at TOP)
8771 #[inline(always)]
8772 pub fn is_match_set(&self) -> bool {
8773 *self == COM2B_A::MATCH_SET
8774 }
8775 }
8776 ///Field `COM2B` writer - Compare Output B Mode
8777 pub type COM2B_W<'a, REG> = crate::FieldWriter<'a, REG, 2, COM2B_A, crate::Safe>;
8778 impl<'a, REG> COM2B_W<'a, REG>
8779 where
8780 REG: crate::Writable + crate::RegisterSpec,
8781 REG::Ux: From<u8>,
8782 {
8783 ///Normal port operation, OCix disconnected
8784 #[inline(always)]
8785 pub fn disconnected(self) -> &'a mut crate::W<REG> {
8786 self.variant(COM2B_A::DISCONNECTED)
8787 }
8788 ///Toggle OCix on Compare Match (Might depend on WGM)
8789 #[inline(always)]
8790 pub fn match_toggle(self) -> &'a mut crate::W<REG> {
8791 self.variant(COM2B_A::MATCH_TOGGLE)
8792 }
8793 ///Clear OCix on Compare Match (If PWM is enabled, OCix is set at TOP)
8794 #[inline(always)]
8795 pub fn match_clear(self) -> &'a mut crate::W<REG> {
8796 self.variant(COM2B_A::MATCH_CLEAR)
8797 }
8798 ///Set OCix on Compare Match (If PWM is enabled, OCix is cleared at TOP)
8799 #[inline(always)]
8800 pub fn match_set(self) -> &'a mut crate::W<REG> {
8801 self.variant(COM2B_A::MATCH_SET)
8802 }
8803 }
8804 ///Field `COM2A` reader - Compare Output A Mode
8805 pub use COM2B_R as COM2A_R;
8806 ///Field `COM2A` writer - Compare Output A Mode
8807 pub use COM2B_W as COM2A_W;
8808 impl R {
8809 ///Bits 0:1 - Waveform Genration Mode
8810 #[inline(always)]
8811 pub fn wgm2(&self) -> WGM2_R {
8812 WGM2_R::new(self.bits & 3)
8813 }
8814 ///Bits 4:5 - Compare Output B Mode
8815 #[inline(always)]
8816 pub fn com2b(&self) -> COM2B_R {
8817 COM2B_R::new((self.bits >> 4) & 3)
8818 }
8819 ///Bits 6:7 - Compare Output A Mode
8820 #[inline(always)]
8821 pub fn com2a(&self) -> COM2A_R {
8822 COM2A_R::new((self.bits >> 6) & 3)
8823 }
8824 }
8825 impl W {
8826 ///Bits 0:1 - Waveform Genration Mode
8827 #[inline(always)]
8828 pub fn wgm2(&mut self) -> WGM2_W<'_, TCCR2A_SPEC> {
8829 WGM2_W::new(self, 0)
8830 }
8831 ///Bits 4:5 - Compare Output B Mode
8832 #[inline(always)]
8833 pub fn com2b(&mut self) -> COM2B_W<'_, TCCR2A_SPEC> {
8834 COM2B_W::new(self, 4)
8835 }
8836 ///Bits 6:7 - Compare Output A Mode
8837 #[inline(always)]
8838 pub fn com2a(&mut self) -> COM2A_W<'_, TCCR2A_SPEC> {
8839 COM2A_W::new(self, 6)
8840 }
8841 }
8842 /**Timer/Counter2 Control Register A
8843
8844You can [`read`](crate::Reg::read) this register and get [`tccr2a::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tccr2a::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
8845 pub struct TCCR2A_SPEC;
8846 impl crate::RegisterSpec for TCCR2A_SPEC {
8847 type Ux = u8;
8848 }
8849 ///`read()` method returns [`tccr2a::R`](R) reader structure
8850 impl crate::Readable for TCCR2A_SPEC {}
8851 ///`write(|w| ..)` method takes [`tccr2a::W`](W) writer structure
8852 impl crate::Writable for TCCR2A_SPEC {
8853 type Safety = crate::Unsafe;
8854 }
8855 ///`reset()` method sets TCCR2A to value 0
8856 impl crate::Resettable for TCCR2A_SPEC {}
8857 }
8858 /**TCCR2B (rw) register accessor: Timer/Counter2 Control Register B
8859
8860You can [`read`](crate::Reg::read) this register and get [`tccr2b::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tccr2b::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
8861
8862For information about available fields see [`mod@tccr2b`] module*/
8863 pub type TCCR2B = crate::Reg<tccr2b::TCCR2B_SPEC>;
8864 ///Timer/Counter2 Control Register B
8865 pub mod tccr2b {
8866 ///Register `TCCR2B` reader
8867 pub type R = crate::R<TCCR2B_SPEC>;
8868 ///Register `TCCR2B` writer
8869 pub type W = crate::W<TCCR2B_SPEC>;
8870 /**Clock Select bits
8871
8872Value on reset: 0*/
8873 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
8874 #[repr(u8)]
8875 pub enum CS2_A {
8876 ///0: No clock source (Timer/Counter stopped)
8877 NO_CLOCK = 0,
8878 ///1: Running, No Prescaling
8879 DIRECT = 1,
8880 ///2: Running, CLK/8
8881 PRESCALE_8 = 2,
8882 ///3: Running, CLK/32
8883 PRESCALE_32 = 3,
8884 ///4: Running, CLK/64
8885 PRESCALE_64 = 4,
8886 ///5: Running, CLK/128
8887 PRESCALE_128 = 5,
8888 ///6: Running, CLK/256
8889 PRESCALE_256 = 6,
8890 ///7: Running, CLK/1024
8891 PRESCALE_1024 = 7,
8892 }
8893 impl From<CS2_A> for u8 {
8894 #[inline(always)]
8895 fn from(variant: CS2_A) -> Self {
8896 variant as _
8897 }
8898 }
8899 impl crate::FieldSpec for CS2_A {
8900 type Ux = u8;
8901 }
8902 impl crate::IsEnum for CS2_A {}
8903 ///Field `CS2` reader - Clock Select bits
8904 pub type CS2_R = crate::FieldReader<CS2_A>;
8905 impl CS2_R {
8906 ///Get enumerated values variant
8907 #[inline(always)]
8908 pub const fn variant(&self) -> CS2_A {
8909 match self.bits {
8910 0 => CS2_A::NO_CLOCK,
8911 1 => CS2_A::DIRECT,
8912 2 => CS2_A::PRESCALE_8,
8913 3 => CS2_A::PRESCALE_32,
8914 4 => CS2_A::PRESCALE_64,
8915 5 => CS2_A::PRESCALE_128,
8916 6 => CS2_A::PRESCALE_256,
8917 7 => CS2_A::PRESCALE_1024,
8918 _ => unreachable!(),
8919 }
8920 }
8921 ///No clock source (Timer/Counter stopped)
8922 #[inline(always)]
8923 pub fn is_no_clock(&self) -> bool {
8924 *self == CS2_A::NO_CLOCK
8925 }
8926 ///Running, No Prescaling
8927 #[inline(always)]
8928 pub fn is_direct(&self) -> bool {
8929 *self == CS2_A::DIRECT
8930 }
8931 ///Running, CLK/8
8932 #[inline(always)]
8933 pub fn is_prescale_8(&self) -> bool {
8934 *self == CS2_A::PRESCALE_8
8935 }
8936 ///Running, CLK/32
8937 #[inline(always)]
8938 pub fn is_prescale_32(&self) -> bool {
8939 *self == CS2_A::PRESCALE_32
8940 }
8941 ///Running, CLK/64
8942 #[inline(always)]
8943 pub fn is_prescale_64(&self) -> bool {
8944 *self == CS2_A::PRESCALE_64
8945 }
8946 ///Running, CLK/128
8947 #[inline(always)]
8948 pub fn is_prescale_128(&self) -> bool {
8949 *self == CS2_A::PRESCALE_128
8950 }
8951 ///Running, CLK/256
8952 #[inline(always)]
8953 pub fn is_prescale_256(&self) -> bool {
8954 *self == CS2_A::PRESCALE_256
8955 }
8956 ///Running, CLK/1024
8957 #[inline(always)]
8958 pub fn is_prescale_1024(&self) -> bool {
8959 *self == CS2_A::PRESCALE_1024
8960 }
8961 }
8962 ///Field `CS2` writer - Clock Select bits
8963 pub type CS2_W<'a, REG> = crate::FieldWriter<'a, REG, 3, CS2_A, crate::Safe>;
8964 impl<'a, REG> CS2_W<'a, REG>
8965 where
8966 REG: crate::Writable + crate::RegisterSpec,
8967 REG::Ux: From<u8>,
8968 {
8969 ///No clock source (Timer/Counter stopped)
8970 #[inline(always)]
8971 pub fn no_clock(self) -> &'a mut crate::W<REG> {
8972 self.variant(CS2_A::NO_CLOCK)
8973 }
8974 ///Running, No Prescaling
8975 #[inline(always)]
8976 pub fn direct(self) -> &'a mut crate::W<REG> {
8977 self.variant(CS2_A::DIRECT)
8978 }
8979 ///Running, CLK/8
8980 #[inline(always)]
8981 pub fn prescale_8(self) -> &'a mut crate::W<REG> {
8982 self.variant(CS2_A::PRESCALE_8)
8983 }
8984 ///Running, CLK/32
8985 #[inline(always)]
8986 pub fn prescale_32(self) -> &'a mut crate::W<REG> {
8987 self.variant(CS2_A::PRESCALE_32)
8988 }
8989 ///Running, CLK/64
8990 #[inline(always)]
8991 pub fn prescale_64(self) -> &'a mut crate::W<REG> {
8992 self.variant(CS2_A::PRESCALE_64)
8993 }
8994 ///Running, CLK/128
8995 #[inline(always)]
8996 pub fn prescale_128(self) -> &'a mut crate::W<REG> {
8997 self.variant(CS2_A::PRESCALE_128)
8998 }
8999 ///Running, CLK/256
9000 #[inline(always)]
9001 pub fn prescale_256(self) -> &'a mut crate::W<REG> {
9002 self.variant(CS2_A::PRESCALE_256)
9003 }
9004 ///Running, CLK/1024
9005 #[inline(always)]
9006 pub fn prescale_1024(self) -> &'a mut crate::W<REG> {
9007 self.variant(CS2_A::PRESCALE_1024)
9008 }
9009 }
9010 ///Field `WGM22` reader - Waveform Generation Mode High Bit (Enable Top: *OCRA* for `PWM` modes)
9011 pub type WGM22_R = crate::BitReader;
9012 ///Field `WGM22` writer - Waveform Generation Mode High Bit (Enable Top: *OCRA* for `PWM` modes)
9013 pub type WGM22_W<'a, REG> = crate::BitWriter<'a, REG>;
9014 ///Field `FOC2B` writer - Force Output Compare B
9015 pub type FOC2B_W<'a, REG> = crate::BitWriter<'a, REG>;
9016 ///Field `FOC2A` writer - Force Output Compare A
9017 pub type FOC2A_W<'a, REG> = crate::BitWriter<'a, REG>;
9018 impl R {
9019 ///Bits 0:2 - Clock Select bits
9020 #[inline(always)]
9021 pub fn cs2(&self) -> CS2_R {
9022 CS2_R::new(self.bits & 7)
9023 }
9024 ///Bit 3 - Waveform Generation Mode High Bit (Enable Top: *OCRA* for `PWM` modes)
9025 #[inline(always)]
9026 pub fn wgm22(&self) -> WGM22_R {
9027 WGM22_R::new(((self.bits >> 3) & 1) != 0)
9028 }
9029 }
9030 impl W {
9031 ///Bits 0:2 - Clock Select bits
9032 #[inline(always)]
9033 pub fn cs2(&mut self) -> CS2_W<'_, TCCR2B_SPEC> {
9034 CS2_W::new(self, 0)
9035 }
9036 ///Bit 3 - Waveform Generation Mode High Bit (Enable Top: *OCRA* for `PWM` modes)
9037 #[inline(always)]
9038 pub fn wgm22(&mut self) -> WGM22_W<'_, TCCR2B_SPEC> {
9039 WGM22_W::new(self, 3)
9040 }
9041 ///Bit 6 - Force Output Compare B
9042 #[inline(always)]
9043 pub fn foc2b(&mut self) -> FOC2B_W<'_, TCCR2B_SPEC> {
9044 FOC2B_W::new(self, 6)
9045 }
9046 ///Bit 7 - Force Output Compare A
9047 #[inline(always)]
9048 pub fn foc2a(&mut self) -> FOC2A_W<'_, TCCR2B_SPEC> {
9049 FOC2A_W::new(self, 7)
9050 }
9051 }
9052 /**Timer/Counter2 Control Register B
9053
9054You can [`read`](crate::Reg::read) this register and get [`tccr2b::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tccr2b::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
9055 pub struct TCCR2B_SPEC;
9056 impl crate::RegisterSpec for TCCR2B_SPEC {
9057 type Ux = u8;
9058 }
9059 ///`read()` method returns [`tccr2b::R`](R) reader structure
9060 impl crate::Readable for TCCR2B_SPEC {}
9061 ///`write(|w| ..)` method takes [`tccr2b::W`](W) writer structure
9062 impl crate::Writable for TCCR2B_SPEC {
9063 type Safety = crate::Unsafe;
9064 }
9065 ///`reset()` method sets TCCR2B to value 0
9066 impl crate::Resettable for TCCR2B_SPEC {}
9067 }
9068 /**TCNT2 (rw) register accessor: Timer/Counter2
9069
9070You can [`read`](crate::Reg::read) this register and get [`tcnt2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcnt2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
9071
9072For information about available fields see [`mod@tcnt2`] module*/
9073 pub type TCNT2 = crate::Reg<tcnt2::TCNT2_SPEC>;
9074 ///Timer/Counter2
9075 pub mod tcnt2 {
9076 ///Register `TCNT2` reader
9077 pub type R = crate::R<TCNT2_SPEC>;
9078 ///Register `TCNT2` writer
9079 pub type W = crate::W<TCNT2_SPEC>;
9080 impl core::fmt::Debug for R {
9081 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
9082 write!(f, "{}", self.bits())
9083 }
9084 }
9085 impl W {}
9086 /**Timer/Counter2
9087
9088You can [`read`](crate::Reg::read) this register and get [`tcnt2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcnt2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
9089 pub struct TCNT2_SPEC;
9090 impl crate::RegisterSpec for TCNT2_SPEC {
9091 type Ux = u8;
9092 }
9093 ///`read()` method returns [`tcnt2::R`](R) reader structure
9094 impl crate::Readable for TCNT2_SPEC {}
9095 ///`write(|w| ..)` method takes [`tcnt2::W`](W) writer structure
9096 impl crate::Writable for TCNT2_SPEC {
9097 type Safety = crate::Safe;
9098 }
9099 ///`reset()` method sets TCNT2 to value 0
9100 impl crate::Resettable for TCNT2_SPEC {}
9101 }
9102 /**TIFR2 (rw) register accessor: Timer/Counter Interrupt Flag Register
9103
9104You can [`read`](crate::Reg::read) this register and get [`tifr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tifr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
9105
9106For information about available fields see [`mod@tifr2`] module*/
9107 pub type TIFR2 = crate::Reg<tifr2::TIFR2_SPEC>;
9108 ///Timer/Counter Interrupt Flag Register
9109 pub mod tifr2 {
9110 ///Register `TIFR2` reader
9111 pub type R = crate::R<TIFR2_SPEC>;
9112 ///Register `TIFR2` writer
9113 pub type W = crate::W<TIFR2_SPEC>;
9114 ///Field `TOV2` reader - Timer/Counter2 Overflow Flag
9115 pub type TOV2_R = crate::BitReader;
9116 ///Field `TOV2` writer - Timer/Counter2 Overflow Flag
9117 pub type TOV2_W<'a, REG> = crate::BitWriter<'a, REG>;
9118 ///Field `OCF2A` reader - Output Compare Flag 2A
9119 pub type OCF2A_R = crate::BitReader;
9120 ///Field `OCF2A` writer - Output Compare Flag 2A
9121 pub type OCF2A_W<'a, REG> = crate::BitWriter<'a, REG>;
9122 ///Field `OCF2B` reader - Output Compare Flag 2B
9123 pub type OCF2B_R = crate::BitReader;
9124 ///Field `OCF2B` writer - Output Compare Flag 2B
9125 pub type OCF2B_W<'a, REG> = crate::BitWriter<'a, REG>;
9126 impl R {
9127 ///Bit 0 - Timer/Counter2 Overflow Flag
9128 #[inline(always)]
9129 pub fn tov2(&self) -> TOV2_R {
9130 TOV2_R::new((self.bits & 1) != 0)
9131 }
9132 ///Bit 1 - Output Compare Flag 2A
9133 #[inline(always)]
9134 pub fn ocf2a(&self) -> OCF2A_R {
9135 OCF2A_R::new(((self.bits >> 1) & 1) != 0)
9136 }
9137 ///Bit 2 - Output Compare Flag 2B
9138 #[inline(always)]
9139 pub fn ocf2b(&self) -> OCF2B_R {
9140 OCF2B_R::new(((self.bits >> 2) & 1) != 0)
9141 }
9142 }
9143 impl W {
9144 ///Bit 0 - Timer/Counter2 Overflow Flag
9145 #[inline(always)]
9146 pub fn tov2(&mut self) -> TOV2_W<'_, TIFR2_SPEC> {
9147 TOV2_W::new(self, 0)
9148 }
9149 ///Bit 1 - Output Compare Flag 2A
9150 #[inline(always)]
9151 pub fn ocf2a(&mut self) -> OCF2A_W<'_, TIFR2_SPEC> {
9152 OCF2A_W::new(self, 1)
9153 }
9154 ///Bit 2 - Output Compare Flag 2B
9155 #[inline(always)]
9156 pub fn ocf2b(&mut self) -> OCF2B_W<'_, TIFR2_SPEC> {
9157 OCF2B_W::new(self, 2)
9158 }
9159 }
9160 /**Timer/Counter Interrupt Flag Register
9161
9162You can [`read`](crate::Reg::read) this register and get [`tifr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tifr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
9163 pub struct TIFR2_SPEC;
9164 impl crate::RegisterSpec for TIFR2_SPEC {
9165 type Ux = u8;
9166 }
9167 ///`read()` method returns [`tifr2::R`](R) reader structure
9168 impl crate::Readable for TIFR2_SPEC {}
9169 ///`write(|w| ..)` method takes [`tifr2::W`](W) writer structure
9170 impl crate::Writable for TIFR2_SPEC {
9171 type Safety = crate::Unsafe;
9172 }
9173 ///`reset()` method sets TIFR2 to value 0
9174 impl crate::Resettable for TIFR2_SPEC {}
9175 }
9176 /**TIMSK2 (rw) register accessor: Timer/Counter Interrupt Mask register
9177
9178You can [`read`](crate::Reg::read) this register and get [`timsk2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timsk2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
9179
9180For information about available fields see [`mod@timsk2`] module*/
9181 pub type TIMSK2 = crate::Reg<timsk2::TIMSK2_SPEC>;
9182 ///Timer/Counter Interrupt Mask register
9183 pub mod timsk2 {
9184 ///Register `TIMSK2` reader
9185 pub type R = crate::R<TIMSK2_SPEC>;
9186 ///Register `TIMSK2` writer
9187 pub type W = crate::W<TIMSK2_SPEC>;
9188 ///Field `TOIE2` reader - Timer/Counter2 Overflow Interrupt Enable
9189 pub type TOIE2_R = crate::BitReader;
9190 ///Field `TOIE2` writer - Timer/Counter2 Overflow Interrupt Enable
9191 pub type TOIE2_W<'a, REG> = crate::BitWriter<'a, REG>;
9192 ///Field `OCIE2A` reader - Timer/Counter2 Output Compare Match A Interrupt Enable
9193 pub type OCIE2A_R = crate::BitReader;
9194 ///Field `OCIE2A` writer - Timer/Counter2 Output Compare Match A Interrupt Enable
9195 pub type OCIE2A_W<'a, REG> = crate::BitWriter<'a, REG>;
9196 ///Field `OCIE2B` reader - Timer/Counter2 Output Compare Match B Interrupt Enable
9197 pub type OCIE2B_R = crate::BitReader;
9198 ///Field `OCIE2B` writer - Timer/Counter2 Output Compare Match B Interrupt Enable
9199 pub type OCIE2B_W<'a, REG> = crate::BitWriter<'a, REG>;
9200 impl R {
9201 ///Bit 0 - Timer/Counter2 Overflow Interrupt Enable
9202 #[inline(always)]
9203 pub fn toie2(&self) -> TOIE2_R {
9204 TOIE2_R::new((self.bits & 1) != 0)
9205 }
9206 ///Bit 1 - Timer/Counter2 Output Compare Match A Interrupt Enable
9207 #[inline(always)]
9208 pub fn ocie2a(&self) -> OCIE2A_R {
9209 OCIE2A_R::new(((self.bits >> 1) & 1) != 0)
9210 }
9211 ///Bit 2 - Timer/Counter2 Output Compare Match B Interrupt Enable
9212 #[inline(always)]
9213 pub fn ocie2b(&self) -> OCIE2B_R {
9214 OCIE2B_R::new(((self.bits >> 2) & 1) != 0)
9215 }
9216 }
9217 impl W {
9218 ///Bit 0 - Timer/Counter2 Overflow Interrupt Enable
9219 #[inline(always)]
9220 pub fn toie2(&mut self) -> TOIE2_W<'_, TIMSK2_SPEC> {
9221 TOIE2_W::new(self, 0)
9222 }
9223 ///Bit 1 - Timer/Counter2 Output Compare Match A Interrupt Enable
9224 #[inline(always)]
9225 pub fn ocie2a(&mut self) -> OCIE2A_W<'_, TIMSK2_SPEC> {
9226 OCIE2A_W::new(self, 1)
9227 }
9228 ///Bit 2 - Timer/Counter2 Output Compare Match B Interrupt Enable
9229 #[inline(always)]
9230 pub fn ocie2b(&mut self) -> OCIE2B_W<'_, TIMSK2_SPEC> {
9231 OCIE2B_W::new(self, 2)
9232 }
9233 }
9234 /**Timer/Counter Interrupt Mask register
9235
9236You can [`read`](crate::Reg::read) this register and get [`timsk2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timsk2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
9237 pub struct TIMSK2_SPEC;
9238 impl crate::RegisterSpec for TIMSK2_SPEC {
9239 type Ux = u8;
9240 }
9241 ///`read()` method returns [`timsk2::R`](R) reader structure
9242 impl crate::Readable for TIMSK2_SPEC {}
9243 ///`write(|w| ..)` method takes [`timsk2::W`](W) writer structure
9244 impl crate::Writable for TIMSK2_SPEC {
9245 type Safety = crate::Unsafe;
9246 }
9247 ///`reset()` method sets TIMSK2 to value 0
9248 impl crate::Resettable for TIMSK2_SPEC {}
9249 }
9250}
9251///Two Wire Serial Interface
9252pub type TWI = crate::Periph<twi::RegisterBlock, 0xb8>;
9253impl core::fmt::Debug for TWI {
9254 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
9255 f.debug_struct("TWI").finish()
9256 }
9257}
9258///Two Wire Serial Interface
9259pub mod twi {
9260 #[repr(C)]
9261 ///Register block
9262 pub struct RegisterBlock {
9263 twbr: TWBR,
9264 twsr: TWSR,
9265 twar: TWAR,
9266 twdr: TWDR,
9267 twcr: TWCR,
9268 twamr: TWAMR,
9269 }
9270 impl RegisterBlock {
9271 ///0x00 - TWI Bit Rate register
9272 #[inline(always)]
9273 pub const fn twbr(&self) -> &TWBR {
9274 &self.twbr
9275 }
9276 ///0x01 - TWI Status Register
9277 #[inline(always)]
9278 pub const fn twsr(&self) -> &TWSR {
9279 &self.twsr
9280 }
9281 ///0x02 - TWI (Slave) Address register
9282 #[inline(always)]
9283 pub const fn twar(&self) -> &TWAR {
9284 &self.twar
9285 }
9286 ///0x03 - TWI Data register
9287 #[inline(always)]
9288 pub const fn twdr(&self) -> &TWDR {
9289 &self.twdr
9290 }
9291 ///0x04 - TWI Control Register
9292 #[inline(always)]
9293 pub const fn twcr(&self) -> &TWCR {
9294 &self.twcr
9295 }
9296 ///0x05 - TWI (Slave) Address Mask Register
9297 #[inline(always)]
9298 pub const fn twamr(&self) -> &TWAMR {
9299 &self.twamr
9300 }
9301 }
9302 /**TWAMR (rw) register accessor: TWI (Slave) Address Mask Register
9303
9304You can [`read`](crate::Reg::read) this register and get [`twamr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`twamr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
9305
9306For information about available fields see [`mod@twamr`] module*/
9307 pub type TWAMR = crate::Reg<twamr::TWAMR_SPEC>;
9308 ///TWI (Slave) Address Mask Register
9309 pub mod twamr {
9310 ///Register `TWAMR` reader
9311 pub type R = crate::R<TWAMR_SPEC>;
9312 ///Register `TWAMR` writer
9313 pub type W = crate::W<TWAMR_SPEC>;
9314 ///Field `TWAM` reader - TWI (Slave) Address Mask Bits
9315 pub type TWAM_R = crate::FieldReader;
9316 ///Field `TWAM` writer - TWI (Slave) Address Mask Bits
9317 pub type TWAM_W<'a, REG> = crate::FieldWriter<'a, REG, 7, u8, crate::Safe>;
9318 impl R {
9319 ///Bits 1:7 - TWI (Slave) Address Mask Bits
9320 #[inline(always)]
9321 pub fn twam(&self) -> TWAM_R {
9322 TWAM_R::new((self.bits >> 1) & 0x7f)
9323 }
9324 }
9325 impl W {
9326 ///Bits 1:7 - TWI (Slave) Address Mask Bits
9327 #[inline(always)]
9328 pub fn twam(&mut self) -> TWAM_W<'_, TWAMR_SPEC> {
9329 TWAM_W::new(self, 1)
9330 }
9331 }
9332 /**TWI (Slave) Address Mask Register
9333
9334You can [`read`](crate::Reg::read) this register and get [`twamr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`twamr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
9335 pub struct TWAMR_SPEC;
9336 impl crate::RegisterSpec for TWAMR_SPEC {
9337 type Ux = u8;
9338 }
9339 ///`read()` method returns [`twamr::R`](R) reader structure
9340 impl crate::Readable for TWAMR_SPEC {}
9341 ///`write(|w| ..)` method takes [`twamr::W`](W) writer structure
9342 impl crate::Writable for TWAMR_SPEC {
9343 type Safety = crate::Unsafe;
9344 }
9345 ///`reset()` method sets TWAMR to value 0
9346 impl crate::Resettable for TWAMR_SPEC {}
9347 }
9348 /**TWAR (rw) register accessor: TWI (Slave) Address register
9349
9350You can [`read`](crate::Reg::read) this register and get [`twar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`twar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
9351
9352For information about available fields see [`mod@twar`] module*/
9353 pub type TWAR = crate::Reg<twar::TWAR_SPEC>;
9354 ///TWI (Slave) Address register
9355 pub mod twar {
9356 ///Register `TWAR` reader
9357 pub type R = crate::R<TWAR_SPEC>;
9358 ///Register `TWAR` writer
9359 pub type W = crate::W<TWAR_SPEC>;
9360 ///Field `TWGCE` reader - TWI General Call Recognition Enable Bit
9361 pub type TWGCE_R = crate::BitReader;
9362 ///Field `TWGCE` writer - TWI General Call Recognition Enable Bit
9363 pub type TWGCE_W<'a, REG> = crate::BitWriter<'a, REG>;
9364 ///Field `TWA` reader - TWI (Slave) Address register Bits
9365 pub type TWA_R = crate::FieldReader;
9366 ///Field `TWA` writer - TWI (Slave) Address register Bits
9367 pub type TWA_W<'a, REG> = crate::FieldWriter<'a, REG, 7, u8, crate::Safe>;
9368 impl R {
9369 ///Bit 0 - TWI General Call Recognition Enable Bit
9370 #[inline(always)]
9371 pub fn twgce(&self) -> TWGCE_R {
9372 TWGCE_R::new((self.bits & 1) != 0)
9373 }
9374 ///Bits 1:7 - TWI (Slave) Address register Bits
9375 #[inline(always)]
9376 pub fn twa(&self) -> TWA_R {
9377 TWA_R::new((self.bits >> 1) & 0x7f)
9378 }
9379 }
9380 impl W {
9381 ///Bit 0 - TWI General Call Recognition Enable Bit
9382 #[inline(always)]
9383 pub fn twgce(&mut self) -> TWGCE_W<'_, TWAR_SPEC> {
9384 TWGCE_W::new(self, 0)
9385 }
9386 ///Bits 1:7 - TWI (Slave) Address register Bits
9387 #[inline(always)]
9388 pub fn twa(&mut self) -> TWA_W<'_, TWAR_SPEC> {
9389 TWA_W::new(self, 1)
9390 }
9391 }
9392 /**TWI (Slave) Address register
9393
9394You can [`read`](crate::Reg::read) this register and get [`twar::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`twar::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
9395 pub struct TWAR_SPEC;
9396 impl crate::RegisterSpec for TWAR_SPEC {
9397 type Ux = u8;
9398 }
9399 ///`read()` method returns [`twar::R`](R) reader structure
9400 impl crate::Readable for TWAR_SPEC {}
9401 ///`write(|w| ..)` method takes [`twar::W`](W) writer structure
9402 impl crate::Writable for TWAR_SPEC {
9403 type Safety = crate::Unsafe;
9404 }
9405 ///`reset()` method sets TWAR to value 0
9406 impl crate::Resettable for TWAR_SPEC {}
9407 }
9408 /**TWBR (rw) register accessor: TWI Bit Rate register
9409
9410You can [`read`](crate::Reg::read) this register and get [`twbr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`twbr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
9411
9412For information about available fields see [`mod@twbr`] module*/
9413 pub type TWBR = crate::Reg<twbr::TWBR_SPEC>;
9414 ///TWI Bit Rate register
9415 pub mod twbr {
9416 ///Register `TWBR` reader
9417 pub type R = crate::R<TWBR_SPEC>;
9418 ///Register `TWBR` writer
9419 pub type W = crate::W<TWBR_SPEC>;
9420 impl core::fmt::Debug for R {
9421 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
9422 write!(f, "{}", self.bits())
9423 }
9424 }
9425 impl W {}
9426 /**TWI Bit Rate register
9427
9428You can [`read`](crate::Reg::read) this register and get [`twbr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`twbr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
9429 pub struct TWBR_SPEC;
9430 impl crate::RegisterSpec for TWBR_SPEC {
9431 type Ux = u8;
9432 }
9433 ///`read()` method returns [`twbr::R`](R) reader structure
9434 impl crate::Readable for TWBR_SPEC {}
9435 ///`write(|w| ..)` method takes [`twbr::W`](W) writer structure
9436 impl crate::Writable for TWBR_SPEC {
9437 type Safety = crate::Safe;
9438 }
9439 ///`reset()` method sets TWBR to value 0
9440 impl crate::Resettable for TWBR_SPEC {}
9441 }
9442 /**TWCR (rw) register accessor: TWI Control Register
9443
9444You can [`read`](crate::Reg::read) this register and get [`twcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`twcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
9445
9446For information about available fields see [`mod@twcr`] module*/
9447 pub type TWCR = crate::Reg<twcr::TWCR_SPEC>;
9448 ///TWI Control Register
9449 pub mod twcr {
9450 ///Register `TWCR` reader
9451 pub type R = crate::R<TWCR_SPEC>;
9452 ///Register `TWCR` writer
9453 pub type W = crate::W<TWCR_SPEC>;
9454 ///Field `TWIE` reader - TWI Interrupt Enable
9455 pub type TWIE_R = crate::BitReader;
9456 ///Field `TWIE` writer - TWI Interrupt Enable
9457 pub type TWIE_W<'a, REG> = crate::BitWriter<'a, REG>;
9458 ///Field `TWEN` reader - TWI Enable Bit
9459 pub type TWEN_R = crate::BitReader;
9460 ///Field `TWEN` writer - TWI Enable Bit
9461 pub type TWEN_W<'a, REG> = crate::BitWriter<'a, REG>;
9462 ///Field `TWWC` reader - TWI Write Collition Flag
9463 pub type TWWC_R = crate::BitReader;
9464 ///Field `TWSTO` reader - TWI Stop Condition Bit
9465 pub type TWSTO_R = crate::BitReader;
9466 ///Field `TWSTO` writer - TWI Stop Condition Bit
9467 pub type TWSTO_W<'a, REG> = crate::BitWriter<'a, REG>;
9468 ///Field `TWSTA` reader - TWI Start Condition Bit
9469 pub type TWSTA_R = crate::BitReader;
9470 ///Field `TWSTA` writer - TWI Start Condition Bit
9471 pub type TWSTA_W<'a, REG> = crate::BitWriter<'a, REG>;
9472 ///Field `TWEA` reader - TWI Enable Acknowledge Bit
9473 pub type TWEA_R = crate::BitReader;
9474 ///Field `TWEA` writer - TWI Enable Acknowledge Bit
9475 pub type TWEA_W<'a, REG> = crate::BitWriter<'a, REG>;
9476 ///Field `TWINT` reader - TWI Interrupt Flag
9477 pub type TWINT_R = crate::BitReader;
9478 ///Field `TWINT` writer - TWI Interrupt Flag
9479 pub type TWINT_W<'a, REG> = crate::BitWriter<'a, REG>;
9480 impl R {
9481 ///Bit 0 - TWI Interrupt Enable
9482 #[inline(always)]
9483 pub fn twie(&self) -> TWIE_R {
9484 TWIE_R::new((self.bits & 1) != 0)
9485 }
9486 ///Bit 2 - TWI Enable Bit
9487 #[inline(always)]
9488 pub fn twen(&self) -> TWEN_R {
9489 TWEN_R::new(((self.bits >> 2) & 1) != 0)
9490 }
9491 ///Bit 3 - TWI Write Collition Flag
9492 #[inline(always)]
9493 pub fn twwc(&self) -> TWWC_R {
9494 TWWC_R::new(((self.bits >> 3) & 1) != 0)
9495 }
9496 ///Bit 4 - TWI Stop Condition Bit
9497 #[inline(always)]
9498 pub fn twsto(&self) -> TWSTO_R {
9499 TWSTO_R::new(((self.bits >> 4) & 1) != 0)
9500 }
9501 ///Bit 5 - TWI Start Condition Bit
9502 #[inline(always)]
9503 pub fn twsta(&self) -> TWSTA_R {
9504 TWSTA_R::new(((self.bits >> 5) & 1) != 0)
9505 }
9506 ///Bit 6 - TWI Enable Acknowledge Bit
9507 #[inline(always)]
9508 pub fn twea(&self) -> TWEA_R {
9509 TWEA_R::new(((self.bits >> 6) & 1) != 0)
9510 }
9511 ///Bit 7 - TWI Interrupt Flag
9512 #[inline(always)]
9513 pub fn twint(&self) -> TWINT_R {
9514 TWINT_R::new(((self.bits >> 7) & 1) != 0)
9515 }
9516 }
9517 impl W {
9518 ///Bit 0 - TWI Interrupt Enable
9519 #[inline(always)]
9520 pub fn twie(&mut self) -> TWIE_W<'_, TWCR_SPEC> {
9521 TWIE_W::new(self, 0)
9522 }
9523 ///Bit 2 - TWI Enable Bit
9524 #[inline(always)]
9525 pub fn twen(&mut self) -> TWEN_W<'_, TWCR_SPEC> {
9526 TWEN_W::new(self, 2)
9527 }
9528 ///Bit 4 - TWI Stop Condition Bit
9529 #[inline(always)]
9530 pub fn twsto(&mut self) -> TWSTO_W<'_, TWCR_SPEC> {
9531 TWSTO_W::new(self, 4)
9532 }
9533 ///Bit 5 - TWI Start Condition Bit
9534 #[inline(always)]
9535 pub fn twsta(&mut self) -> TWSTA_W<'_, TWCR_SPEC> {
9536 TWSTA_W::new(self, 5)
9537 }
9538 ///Bit 6 - TWI Enable Acknowledge Bit
9539 #[inline(always)]
9540 pub fn twea(&mut self) -> TWEA_W<'_, TWCR_SPEC> {
9541 TWEA_W::new(self, 6)
9542 }
9543 ///Bit 7 - TWI Interrupt Flag
9544 #[inline(always)]
9545 pub fn twint(&mut self) -> TWINT_W<'_, TWCR_SPEC> {
9546 TWINT_W::new(self, 7)
9547 }
9548 }
9549 /**TWI Control Register
9550
9551You can [`read`](crate::Reg::read) this register and get [`twcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`twcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
9552 pub struct TWCR_SPEC;
9553 impl crate::RegisterSpec for TWCR_SPEC {
9554 type Ux = u8;
9555 }
9556 ///`read()` method returns [`twcr::R`](R) reader structure
9557 impl crate::Readable for TWCR_SPEC {}
9558 ///`write(|w| ..)` method takes [`twcr::W`](W) writer structure
9559 impl crate::Writable for TWCR_SPEC {
9560 type Safety = crate::Unsafe;
9561 }
9562 ///`reset()` method sets TWCR to value 0
9563 impl crate::Resettable for TWCR_SPEC {}
9564 }
9565 /**TWDR (rw) register accessor: TWI Data register
9566
9567You can [`read`](crate::Reg::read) this register and get [`twdr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`twdr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
9568
9569For information about available fields see [`mod@twdr`] module*/
9570 pub type TWDR = crate::Reg<twdr::TWDR_SPEC>;
9571 ///TWI Data register
9572 pub mod twdr {
9573 ///Register `TWDR` reader
9574 pub type R = crate::R<TWDR_SPEC>;
9575 ///Register `TWDR` writer
9576 pub type W = crate::W<TWDR_SPEC>;
9577 impl core::fmt::Debug for R {
9578 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
9579 write!(f, "{}", self.bits())
9580 }
9581 }
9582 impl W {}
9583 /**TWI Data register
9584
9585You can [`read`](crate::Reg::read) this register and get [`twdr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`twdr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
9586 pub struct TWDR_SPEC;
9587 impl crate::RegisterSpec for TWDR_SPEC {
9588 type Ux = u8;
9589 }
9590 ///`read()` method returns [`twdr::R`](R) reader structure
9591 impl crate::Readable for TWDR_SPEC {}
9592 ///`write(|w| ..)` method takes [`twdr::W`](W) writer structure
9593 impl crate::Writable for TWDR_SPEC {
9594 type Safety = crate::Safe;
9595 }
9596 ///`reset()` method sets TWDR to value 0
9597 impl crate::Resettable for TWDR_SPEC {}
9598 }
9599 /**TWSR (rw) register accessor: TWI Status Register
9600
9601You can [`read`](crate::Reg::read) this register and get [`twsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`twsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
9602
9603For information about available fields see [`mod@twsr`] module*/
9604 pub type TWSR = crate::Reg<twsr::TWSR_SPEC>;
9605 ///TWI Status Register
9606 pub mod twsr {
9607 ///Register `TWSR` reader
9608 pub type R = crate::R<TWSR_SPEC>;
9609 ///Register `TWSR` writer
9610 pub type W = crate::W<TWSR_SPEC>;
9611 /**TWI Prescaler
9612
9613Value on reset: 0*/
9614 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
9615 #[repr(u8)]
9616 pub enum TWPS_A {
9617 ///0: Prescaler Value 1
9618 PRESCALER_1 = 0,
9619 ///1: Prescaler Value 4
9620 PRESCALER_4 = 1,
9621 ///2: Prescaler Value 16
9622 PRESCALER_16 = 2,
9623 ///3: Prescaler Value 64
9624 PRESCALER_64 = 3,
9625 }
9626 impl From<TWPS_A> for u8 {
9627 #[inline(always)]
9628 fn from(variant: TWPS_A) -> Self {
9629 variant as _
9630 }
9631 }
9632 impl crate::FieldSpec for TWPS_A {
9633 type Ux = u8;
9634 }
9635 impl crate::IsEnum for TWPS_A {}
9636 ///Field `TWPS` reader - TWI Prescaler
9637 pub type TWPS_R = crate::FieldReader<TWPS_A>;
9638 impl TWPS_R {
9639 ///Get enumerated values variant
9640 #[inline(always)]
9641 pub const fn variant(&self) -> TWPS_A {
9642 match self.bits {
9643 0 => TWPS_A::PRESCALER_1,
9644 1 => TWPS_A::PRESCALER_4,
9645 2 => TWPS_A::PRESCALER_16,
9646 3 => TWPS_A::PRESCALER_64,
9647 _ => unreachable!(),
9648 }
9649 }
9650 ///Prescaler Value 1
9651 #[inline(always)]
9652 pub fn is_prescaler_1(&self) -> bool {
9653 *self == TWPS_A::PRESCALER_1
9654 }
9655 ///Prescaler Value 4
9656 #[inline(always)]
9657 pub fn is_prescaler_4(&self) -> bool {
9658 *self == TWPS_A::PRESCALER_4
9659 }
9660 ///Prescaler Value 16
9661 #[inline(always)]
9662 pub fn is_prescaler_16(&self) -> bool {
9663 *self == TWPS_A::PRESCALER_16
9664 }
9665 ///Prescaler Value 64
9666 #[inline(always)]
9667 pub fn is_prescaler_64(&self) -> bool {
9668 *self == TWPS_A::PRESCALER_64
9669 }
9670 }
9671 ///Field `TWPS` writer - TWI Prescaler
9672 pub type TWPS_W<'a, REG> = crate::FieldWriter<'a, REG, 2, TWPS_A, crate::Safe>;
9673 impl<'a, REG> TWPS_W<'a, REG>
9674 where
9675 REG: crate::Writable + crate::RegisterSpec,
9676 REG::Ux: From<u8>,
9677 {
9678 ///Prescaler Value 1
9679 #[inline(always)]
9680 pub fn prescaler_1(self) -> &'a mut crate::W<REG> {
9681 self.variant(TWPS_A::PRESCALER_1)
9682 }
9683 ///Prescaler Value 4
9684 #[inline(always)]
9685 pub fn prescaler_4(self) -> &'a mut crate::W<REG> {
9686 self.variant(TWPS_A::PRESCALER_4)
9687 }
9688 ///Prescaler Value 16
9689 #[inline(always)]
9690 pub fn prescaler_16(self) -> &'a mut crate::W<REG> {
9691 self.variant(TWPS_A::PRESCALER_16)
9692 }
9693 ///Prescaler Value 64
9694 #[inline(always)]
9695 pub fn prescaler_64(self) -> &'a mut crate::W<REG> {
9696 self.variant(TWPS_A::PRESCALER_64)
9697 }
9698 }
9699 ///Field `TWS` reader - TWI Status
9700 pub type TWS_R = crate::FieldReader;
9701 impl R {
9702 ///Bits 0:1 - TWI Prescaler
9703 #[inline(always)]
9704 pub fn twps(&self) -> TWPS_R {
9705 TWPS_R::new(self.bits & 3)
9706 }
9707 ///Bits 3:7 - TWI Status
9708 #[inline(always)]
9709 pub fn tws(&self) -> TWS_R {
9710 TWS_R::new((self.bits >> 3) & 0x1f)
9711 }
9712 }
9713 impl W {
9714 ///Bits 0:1 - TWI Prescaler
9715 #[inline(always)]
9716 pub fn twps(&mut self) -> TWPS_W<'_, TWSR_SPEC> {
9717 TWPS_W::new(self, 0)
9718 }
9719 }
9720 /**TWI Status Register
9721
9722You can [`read`](crate::Reg::read) this register and get [`twsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`twsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
9723 pub struct TWSR_SPEC;
9724 impl crate::RegisterSpec for TWSR_SPEC {
9725 type Ux = u8;
9726 }
9727 ///`read()` method returns [`twsr::R`](R) reader structure
9728 impl crate::Readable for TWSR_SPEC {}
9729 ///`write(|w| ..)` method takes [`twsr::W`](W) writer structure
9730 impl crate::Writable for TWSR_SPEC {
9731 type Safety = crate::Unsafe;
9732 }
9733 ///`reset()` method sets TWSR to value 0
9734 impl crate::Resettable for TWSR_SPEC {}
9735 }
9736}
9737///USART
9738pub type USART0 = crate::Periph<usart0::RegisterBlock, 0xc0>;
9739impl core::fmt::Debug for USART0 {
9740 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
9741 f.debug_struct("USART0").finish()
9742 }
9743}
9744///USART
9745pub mod usart0 {
9746 #[repr(C)]
9747 ///Register block
9748 pub struct RegisterBlock {
9749 ucsr0a: UCSR0A,
9750 ucsr0b: UCSR0B,
9751 ucsr0c: UCSR0C,
9752 _reserved3: [u8; 0x01],
9753 ubrr0: UBRR0,
9754 udr0: UDR0,
9755 }
9756 impl RegisterBlock {
9757 ///0x00 - USART Control and Status Register A
9758 #[inline(always)]
9759 pub const fn ucsr0a(&self) -> &UCSR0A {
9760 &self.ucsr0a
9761 }
9762 ///0x01 - USART Control and Status Register B
9763 #[inline(always)]
9764 pub const fn ucsr0b(&self) -> &UCSR0B {
9765 &self.ucsr0b
9766 }
9767 ///0x02 - USART Control and Status Register C
9768 #[inline(always)]
9769 pub const fn ucsr0c(&self) -> &UCSR0C {
9770 &self.ucsr0c
9771 }
9772 ///0x04 - USART Baud Rate Register Bytes
9773 #[inline(always)]
9774 pub const fn ubrr0(&self) -> &UBRR0 {
9775 &self.ubrr0
9776 }
9777 ///0x06 - USART I/O Data Register
9778 #[inline(always)]
9779 pub const fn udr0(&self) -> &UDR0 {
9780 &self.udr0
9781 }
9782 }
9783 /**UBRR0 (rw) register accessor: USART Baud Rate Register Bytes
9784
9785You can [`read`](crate::Reg::read) this register and get [`ubrr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ubrr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
9786
9787For information about available fields see [`mod@ubrr0`] module*/
9788 pub type UBRR0 = crate::Reg<ubrr0::UBRR0_SPEC>;
9789 ///USART Baud Rate Register Bytes
9790 pub mod ubrr0 {
9791 ///Register `UBRR0` reader
9792 pub type R = crate::R<UBRR0_SPEC>;
9793 ///Register `UBRR0` writer
9794 pub type W = crate::W<UBRR0_SPEC>;
9795 impl core::fmt::Debug for R {
9796 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
9797 write!(f, "{}", self.bits())
9798 }
9799 }
9800 impl W {}
9801 /**USART Baud Rate Register Bytes
9802
9803You can [`read`](crate::Reg::read) this register and get [`ubrr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ubrr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
9804 pub struct UBRR0_SPEC;
9805 impl crate::RegisterSpec for UBRR0_SPEC {
9806 type Ux = u16;
9807 }
9808 ///`read()` method returns [`ubrr0::R`](R) reader structure
9809 impl crate::Readable for UBRR0_SPEC {}
9810 ///`write(|w| ..)` method takes [`ubrr0::W`](W) writer structure
9811 impl crate::Writable for UBRR0_SPEC {
9812 type Safety = crate::Safe;
9813 }
9814 ///`reset()` method sets UBRR0 to value 0
9815 impl crate::Resettable for UBRR0_SPEC {}
9816 }
9817 /**UCSR0A (rw) register accessor: USART Control and Status Register A
9818
9819You can [`read`](crate::Reg::read) this register and get [`ucsr0a::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucsr0a::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
9820
9821For information about available fields see [`mod@ucsr0a`] module*/
9822 pub type UCSR0A = crate::Reg<ucsr0a::UCSR0A_SPEC>;
9823 ///USART Control and Status Register A
9824 pub mod ucsr0a {
9825 ///Register `UCSR0A` reader
9826 pub type R = crate::R<UCSR0A_SPEC>;
9827 ///Register `UCSR0A` writer
9828 pub type W = crate::W<UCSR0A_SPEC>;
9829 ///Field `MPCM0` reader - Multi-processor Communication Mode
9830 pub type MPCM0_R = crate::BitReader;
9831 ///Field `MPCM0` writer - Multi-processor Communication Mode
9832 pub type MPCM0_W<'a, REG> = crate::BitWriter<'a, REG>;
9833 ///Field `U2X0` reader - Double the USART transmission speed
9834 pub type U2X0_R = crate::BitReader;
9835 ///Field `U2X0` writer - Double the USART transmission speed
9836 pub type U2X0_W<'a, REG> = crate::BitWriter<'a, REG>;
9837 ///Field `UPE0` reader - Parity Error
9838 pub type UPE0_R = crate::BitReader;
9839 ///Field `DOR0` reader - Data overRun
9840 pub type DOR0_R = crate::BitReader;
9841 ///Field `FE0` reader - Framing Error
9842 pub type FE0_R = crate::BitReader;
9843 ///Field `UDRE0` reader - USART Data Register Empty
9844 pub type UDRE0_R = crate::BitReader;
9845 ///Field `TXC0` reader - USART Transmit Complete
9846 pub type TXC0_R = crate::BitReader;
9847 ///Field `TXC0` writer - USART Transmit Complete
9848 pub type TXC0_W<'a, REG> = crate::BitWriter<'a, REG>;
9849 ///Field `RXC0` reader - USART Receive Complete
9850 pub type RXC0_R = crate::BitReader;
9851 impl R {
9852 ///Bit 0 - Multi-processor Communication Mode
9853 #[inline(always)]
9854 pub fn mpcm0(&self) -> MPCM0_R {
9855 MPCM0_R::new((self.bits & 1) != 0)
9856 }
9857 ///Bit 1 - Double the USART transmission speed
9858 #[inline(always)]
9859 pub fn u2x0(&self) -> U2X0_R {
9860 U2X0_R::new(((self.bits >> 1) & 1) != 0)
9861 }
9862 ///Bit 2 - Parity Error
9863 #[inline(always)]
9864 pub fn upe0(&self) -> UPE0_R {
9865 UPE0_R::new(((self.bits >> 2) & 1) != 0)
9866 }
9867 ///Bit 3 - Data overRun
9868 #[inline(always)]
9869 pub fn dor0(&self) -> DOR0_R {
9870 DOR0_R::new(((self.bits >> 3) & 1) != 0)
9871 }
9872 ///Bit 4 - Framing Error
9873 #[inline(always)]
9874 pub fn fe0(&self) -> FE0_R {
9875 FE0_R::new(((self.bits >> 4) & 1) != 0)
9876 }
9877 ///Bit 5 - USART Data Register Empty
9878 #[inline(always)]
9879 pub fn udre0(&self) -> UDRE0_R {
9880 UDRE0_R::new(((self.bits >> 5) & 1) != 0)
9881 }
9882 ///Bit 6 - USART Transmit Complete
9883 #[inline(always)]
9884 pub fn txc0(&self) -> TXC0_R {
9885 TXC0_R::new(((self.bits >> 6) & 1) != 0)
9886 }
9887 ///Bit 7 - USART Receive Complete
9888 #[inline(always)]
9889 pub fn rxc0(&self) -> RXC0_R {
9890 RXC0_R::new(((self.bits >> 7) & 1) != 0)
9891 }
9892 }
9893 impl W {
9894 ///Bit 0 - Multi-processor Communication Mode
9895 #[inline(always)]
9896 pub fn mpcm0(&mut self) -> MPCM0_W<'_, UCSR0A_SPEC> {
9897 MPCM0_W::new(self, 0)
9898 }
9899 ///Bit 1 - Double the USART transmission speed
9900 #[inline(always)]
9901 pub fn u2x0(&mut self) -> U2X0_W<'_, UCSR0A_SPEC> {
9902 U2X0_W::new(self, 1)
9903 }
9904 ///Bit 6 - USART Transmit Complete
9905 #[inline(always)]
9906 pub fn txc0(&mut self) -> TXC0_W<'_, UCSR0A_SPEC> {
9907 TXC0_W::new(self, 6)
9908 }
9909 }
9910 /**USART Control and Status Register A
9911
9912You can [`read`](crate::Reg::read) this register and get [`ucsr0a::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucsr0a::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
9913 pub struct UCSR0A_SPEC;
9914 impl crate::RegisterSpec for UCSR0A_SPEC {
9915 type Ux = u8;
9916 }
9917 ///`read()` method returns [`ucsr0a::R`](R) reader structure
9918 impl crate::Readable for UCSR0A_SPEC {}
9919 ///`write(|w| ..)` method takes [`ucsr0a::W`](W) writer structure
9920 impl crate::Writable for UCSR0A_SPEC {
9921 type Safety = crate::Unsafe;
9922 }
9923 ///`reset()` method sets UCSR0A to value 0
9924 impl crate::Resettable for UCSR0A_SPEC {}
9925 }
9926 /**UCSR0B (rw) register accessor: USART Control and Status Register B
9927
9928You can [`read`](crate::Reg::read) this register and get [`ucsr0b::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucsr0b::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
9929
9930For information about available fields see [`mod@ucsr0b`] module*/
9931 pub type UCSR0B = crate::Reg<ucsr0b::UCSR0B_SPEC>;
9932 ///USART Control and Status Register B
9933 pub mod ucsr0b {
9934 ///Register `UCSR0B` reader
9935 pub type R = crate::R<UCSR0B_SPEC>;
9936 ///Register `UCSR0B` writer
9937 pub type W = crate::W<UCSR0B_SPEC>;
9938 ///Field `TXB80` reader - Transmit Data Bit 8
9939 pub type TXB80_R = crate::BitReader;
9940 ///Field `TXB80` writer - Transmit Data Bit 8
9941 pub type TXB80_W<'a, REG> = crate::BitWriter<'a, REG>;
9942 ///Field `RXB80` reader - Receive Data Bit 8
9943 pub type RXB80_R = crate::BitReader;
9944 ///Field `UCSZ02` reader - Character Size
9945 pub type UCSZ02_R = crate::BitReader;
9946 ///Field `UCSZ02` writer - Character Size
9947 pub type UCSZ02_W<'a, REG> = crate::BitWriter<'a, REG>;
9948 ///Field `TXEN0` reader - Transmitter Enable
9949 pub type TXEN0_R = crate::BitReader;
9950 ///Field `TXEN0` writer - Transmitter Enable
9951 pub type TXEN0_W<'a, REG> = crate::BitWriter<'a, REG>;
9952 ///Field `RXEN0` reader - Receiver Enable
9953 pub type RXEN0_R = crate::BitReader;
9954 ///Field `RXEN0` writer - Receiver Enable
9955 pub type RXEN0_W<'a, REG> = crate::BitWriter<'a, REG>;
9956 ///Field `UDRIE0` reader - USART Data register Empty Interrupt Enable
9957 pub type UDRIE0_R = crate::BitReader;
9958 ///Field `UDRIE0` writer - USART Data register Empty Interrupt Enable
9959 pub type UDRIE0_W<'a, REG> = crate::BitWriter<'a, REG>;
9960 ///Field `TXCIE0` reader - TX Complete Interrupt Enable
9961 pub type TXCIE0_R = crate::BitReader;
9962 ///Field `TXCIE0` writer - TX Complete Interrupt Enable
9963 pub type TXCIE0_W<'a, REG> = crate::BitWriter<'a, REG>;
9964 ///Field `RXCIE0` reader - RX Complete Interrupt Enable
9965 pub type RXCIE0_R = crate::BitReader;
9966 ///Field `RXCIE0` writer - RX Complete Interrupt Enable
9967 pub type RXCIE0_W<'a, REG> = crate::BitWriter<'a, REG>;
9968 impl R {
9969 ///Bit 0 - Transmit Data Bit 8
9970 #[inline(always)]
9971 pub fn txb80(&self) -> TXB80_R {
9972 TXB80_R::new((self.bits & 1) != 0)
9973 }
9974 ///Bit 1 - Receive Data Bit 8
9975 #[inline(always)]
9976 pub fn rxb80(&self) -> RXB80_R {
9977 RXB80_R::new(((self.bits >> 1) & 1) != 0)
9978 }
9979 ///Bit 2 - Character Size
9980 #[inline(always)]
9981 pub fn ucsz02(&self) -> UCSZ02_R {
9982 UCSZ02_R::new(((self.bits >> 2) & 1) != 0)
9983 }
9984 ///Bit 3 - Transmitter Enable
9985 #[inline(always)]
9986 pub fn txen0(&self) -> TXEN0_R {
9987 TXEN0_R::new(((self.bits >> 3) & 1) != 0)
9988 }
9989 ///Bit 4 - Receiver Enable
9990 #[inline(always)]
9991 pub fn rxen0(&self) -> RXEN0_R {
9992 RXEN0_R::new(((self.bits >> 4) & 1) != 0)
9993 }
9994 ///Bit 5 - USART Data register Empty Interrupt Enable
9995 #[inline(always)]
9996 pub fn udrie0(&self) -> UDRIE0_R {
9997 UDRIE0_R::new(((self.bits >> 5) & 1) != 0)
9998 }
9999 ///Bit 6 - TX Complete Interrupt Enable
10000 #[inline(always)]
10001 pub fn txcie0(&self) -> TXCIE0_R {
10002 TXCIE0_R::new(((self.bits >> 6) & 1) != 0)
10003 }
10004 ///Bit 7 - RX Complete Interrupt Enable
10005 #[inline(always)]
10006 pub fn rxcie0(&self) -> RXCIE0_R {
10007 RXCIE0_R::new(((self.bits >> 7) & 1) != 0)
10008 }
10009 }
10010 impl W {
10011 ///Bit 0 - Transmit Data Bit 8
10012 #[inline(always)]
10013 pub fn txb80(&mut self) -> TXB80_W<'_, UCSR0B_SPEC> {
10014 TXB80_W::new(self, 0)
10015 }
10016 ///Bit 2 - Character Size
10017 #[inline(always)]
10018 pub fn ucsz02(&mut self) -> UCSZ02_W<'_, UCSR0B_SPEC> {
10019 UCSZ02_W::new(self, 2)
10020 }
10021 ///Bit 3 - Transmitter Enable
10022 #[inline(always)]
10023 pub fn txen0(&mut self) -> TXEN0_W<'_, UCSR0B_SPEC> {
10024 TXEN0_W::new(self, 3)
10025 }
10026 ///Bit 4 - Receiver Enable
10027 #[inline(always)]
10028 pub fn rxen0(&mut self) -> RXEN0_W<'_, UCSR0B_SPEC> {
10029 RXEN0_W::new(self, 4)
10030 }
10031 ///Bit 5 - USART Data register Empty Interrupt Enable
10032 #[inline(always)]
10033 pub fn udrie0(&mut self) -> UDRIE0_W<'_, UCSR0B_SPEC> {
10034 UDRIE0_W::new(self, 5)
10035 }
10036 ///Bit 6 - TX Complete Interrupt Enable
10037 #[inline(always)]
10038 pub fn txcie0(&mut self) -> TXCIE0_W<'_, UCSR0B_SPEC> {
10039 TXCIE0_W::new(self, 6)
10040 }
10041 ///Bit 7 - RX Complete Interrupt Enable
10042 #[inline(always)]
10043 pub fn rxcie0(&mut self) -> RXCIE0_W<'_, UCSR0B_SPEC> {
10044 RXCIE0_W::new(self, 7)
10045 }
10046 }
10047 /**USART Control and Status Register B
10048
10049You can [`read`](crate::Reg::read) this register and get [`ucsr0b::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucsr0b::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
10050 pub struct UCSR0B_SPEC;
10051 impl crate::RegisterSpec for UCSR0B_SPEC {
10052 type Ux = u8;
10053 }
10054 ///`read()` method returns [`ucsr0b::R`](R) reader structure
10055 impl crate::Readable for UCSR0B_SPEC {}
10056 ///`write(|w| ..)` method takes [`ucsr0b::W`](W) writer structure
10057 impl crate::Writable for UCSR0B_SPEC {
10058 type Safety = crate::Unsafe;
10059 }
10060 ///`reset()` method sets UCSR0B to value 0
10061 impl crate::Resettable for UCSR0B_SPEC {}
10062 }
10063 /**UCSR0C (rw) register accessor: USART Control and Status Register C
10064
10065You can [`read`](crate::Reg::read) this register and get [`ucsr0c::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucsr0c::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
10066
10067For information about available fields see [`mod@ucsr0c`] module*/
10068 pub type UCSR0C = crate::Reg<ucsr0c::UCSR0C_SPEC>;
10069 ///USART Control and Status Register C
10070 pub mod ucsr0c {
10071 ///Register `UCSR0C` reader
10072 pub type R = crate::R<UCSR0C_SPEC>;
10073 ///Register `UCSR0C` writer
10074 pub type W = crate::W<UCSR0C_SPEC>;
10075 /**Clock Polarity
10076
10077Value on reset: 0*/
10078 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
10079 pub enum UCPOL0_A {
10080 ///0: Transmit on Rising XCKn Edge, Receive on Falling XCKn Edge
10081 RISING_EDGE = 0,
10082 ///1: Transmit on Falling XCKn Edge, Receive on Rising XCKn Edge
10083 FALLING_EDGE = 1,
10084 }
10085 impl From<UCPOL0_A> for bool {
10086 #[inline(always)]
10087 fn from(variant: UCPOL0_A) -> Self {
10088 variant as u8 != 0
10089 }
10090 }
10091 ///Field `UCPOL0` reader - Clock Polarity
10092 pub type UCPOL0_R = crate::BitReader<UCPOL0_A>;
10093 impl UCPOL0_R {
10094 ///Get enumerated values variant
10095 #[inline(always)]
10096 pub const fn variant(&self) -> UCPOL0_A {
10097 match self.bits {
10098 false => UCPOL0_A::RISING_EDGE,
10099 true => UCPOL0_A::FALLING_EDGE,
10100 }
10101 }
10102 ///Transmit on Rising XCKn Edge, Receive on Falling XCKn Edge
10103 #[inline(always)]
10104 pub fn is_rising_edge(&self) -> bool {
10105 *self == UCPOL0_A::RISING_EDGE
10106 }
10107 ///Transmit on Falling XCKn Edge, Receive on Rising XCKn Edge
10108 #[inline(always)]
10109 pub fn is_falling_edge(&self) -> bool {
10110 *self == UCPOL0_A::FALLING_EDGE
10111 }
10112 }
10113 ///Field `UCPOL0` writer - Clock Polarity
10114 pub type UCPOL0_W<'a, REG> = crate::BitWriter<'a, REG, UCPOL0_A>;
10115 impl<'a, REG> UCPOL0_W<'a, REG>
10116 where
10117 REG: crate::Writable + crate::RegisterSpec,
10118 {
10119 ///Transmit on Rising XCKn Edge, Receive on Falling XCKn Edge
10120 #[inline(always)]
10121 pub fn rising_edge(self) -> &'a mut crate::W<REG> {
10122 self.variant(UCPOL0_A::RISING_EDGE)
10123 }
10124 ///Transmit on Falling XCKn Edge, Receive on Rising XCKn Edge
10125 #[inline(always)]
10126 pub fn falling_edge(self) -> &'a mut crate::W<REG> {
10127 self.variant(UCPOL0_A::FALLING_EDGE)
10128 }
10129 }
10130 /**Character Size
10131
10132Value on reset: 0*/
10133 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
10134 #[repr(u8)]
10135 pub enum UCSZ0_A {
10136 ///0: Character Size: 5 bit
10137 CHR5 = 0,
10138 ///1: Character Size: 6 bit
10139 CHR6 = 1,
10140 ///2: Character Size: 7 bit
10141 CHR7 = 2,
10142 ///3: Character Size: 8 bit
10143 CHR8 = 3,
10144 }
10145 impl From<UCSZ0_A> for u8 {
10146 #[inline(always)]
10147 fn from(variant: UCSZ0_A) -> Self {
10148 variant as _
10149 }
10150 }
10151 impl crate::FieldSpec for UCSZ0_A {
10152 type Ux = u8;
10153 }
10154 impl crate::IsEnum for UCSZ0_A {}
10155 ///Field `UCSZ0` reader - Character Size
10156 pub type UCSZ0_R = crate::FieldReader<UCSZ0_A>;
10157 impl UCSZ0_R {
10158 ///Get enumerated values variant
10159 #[inline(always)]
10160 pub const fn variant(&self) -> UCSZ0_A {
10161 match self.bits {
10162 0 => UCSZ0_A::CHR5,
10163 1 => UCSZ0_A::CHR6,
10164 2 => UCSZ0_A::CHR7,
10165 3 => UCSZ0_A::CHR8,
10166 _ => unreachable!(),
10167 }
10168 }
10169 ///Character Size: 5 bit
10170 #[inline(always)]
10171 pub fn is_chr5(&self) -> bool {
10172 *self == UCSZ0_A::CHR5
10173 }
10174 ///Character Size: 6 bit
10175 #[inline(always)]
10176 pub fn is_chr6(&self) -> bool {
10177 *self == UCSZ0_A::CHR6
10178 }
10179 ///Character Size: 7 bit
10180 #[inline(always)]
10181 pub fn is_chr7(&self) -> bool {
10182 *self == UCSZ0_A::CHR7
10183 }
10184 ///Character Size: 8 bit
10185 #[inline(always)]
10186 pub fn is_chr8(&self) -> bool {
10187 *self == UCSZ0_A::CHR8
10188 }
10189 }
10190 ///Field `UCSZ0` writer - Character Size
10191 pub type UCSZ0_W<'a, REG> = crate::FieldWriter<'a, REG, 2, UCSZ0_A, crate::Safe>;
10192 impl<'a, REG> UCSZ0_W<'a, REG>
10193 where
10194 REG: crate::Writable + crate::RegisterSpec,
10195 REG::Ux: From<u8>,
10196 {
10197 ///Character Size: 5 bit
10198 #[inline(always)]
10199 pub fn chr5(self) -> &'a mut crate::W<REG> {
10200 self.variant(UCSZ0_A::CHR5)
10201 }
10202 ///Character Size: 6 bit
10203 #[inline(always)]
10204 pub fn chr6(self) -> &'a mut crate::W<REG> {
10205 self.variant(UCSZ0_A::CHR6)
10206 }
10207 ///Character Size: 7 bit
10208 #[inline(always)]
10209 pub fn chr7(self) -> &'a mut crate::W<REG> {
10210 self.variant(UCSZ0_A::CHR7)
10211 }
10212 ///Character Size: 8 bit
10213 #[inline(always)]
10214 pub fn chr8(self) -> &'a mut crate::W<REG> {
10215 self.variant(UCSZ0_A::CHR8)
10216 }
10217 }
10218 /**Stop Bit Select
10219
10220Value on reset: 0*/
10221 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
10222 pub enum USBS0_A {
10223 ///0: 1-bit
10224 STOP1 = 0,
10225 ///1: 2-bit
10226 STOP2 = 1,
10227 }
10228 impl From<USBS0_A> for bool {
10229 #[inline(always)]
10230 fn from(variant: USBS0_A) -> Self {
10231 variant as u8 != 0
10232 }
10233 }
10234 ///Field `USBS0` reader - Stop Bit Select
10235 pub type USBS0_R = crate::BitReader<USBS0_A>;
10236 impl USBS0_R {
10237 ///Get enumerated values variant
10238 #[inline(always)]
10239 pub const fn variant(&self) -> USBS0_A {
10240 match self.bits {
10241 false => USBS0_A::STOP1,
10242 true => USBS0_A::STOP2,
10243 }
10244 }
10245 ///1-bit
10246 #[inline(always)]
10247 pub fn is_stop1(&self) -> bool {
10248 *self == USBS0_A::STOP1
10249 }
10250 ///2-bit
10251 #[inline(always)]
10252 pub fn is_stop2(&self) -> bool {
10253 *self == USBS0_A::STOP2
10254 }
10255 }
10256 ///Field `USBS0` writer - Stop Bit Select
10257 pub type USBS0_W<'a, REG> = crate::BitWriter<'a, REG, USBS0_A>;
10258 impl<'a, REG> USBS0_W<'a, REG>
10259 where
10260 REG: crate::Writable + crate::RegisterSpec,
10261 {
10262 ///1-bit
10263 #[inline(always)]
10264 pub fn stop1(self) -> &'a mut crate::W<REG> {
10265 self.variant(USBS0_A::STOP1)
10266 }
10267 ///2-bit
10268 #[inline(always)]
10269 pub fn stop2(self) -> &'a mut crate::W<REG> {
10270 self.variant(USBS0_A::STOP2)
10271 }
10272 }
10273 /**Parity Mode Bits
10274
10275Value on reset: 0*/
10276 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
10277 #[repr(u8)]
10278 pub enum UPM0_A {
10279 ///0: Disabled
10280 DISABLED = 0,
10281 ///2: Enabled, Even Parity
10282 PARITY_EVEN = 2,
10283 ///3: Enabled, Odd Parity
10284 PARITY_ODD = 3,
10285 }
10286 impl From<UPM0_A> for u8 {
10287 #[inline(always)]
10288 fn from(variant: UPM0_A) -> Self {
10289 variant as _
10290 }
10291 }
10292 impl crate::FieldSpec for UPM0_A {
10293 type Ux = u8;
10294 }
10295 impl crate::IsEnum for UPM0_A {}
10296 ///Field `UPM0` reader - Parity Mode Bits
10297 pub type UPM0_R = crate::FieldReader<UPM0_A>;
10298 impl UPM0_R {
10299 ///Get enumerated values variant
10300 #[inline(always)]
10301 pub const fn variant(&self) -> Option<UPM0_A> {
10302 match self.bits {
10303 0 => Some(UPM0_A::DISABLED),
10304 2 => Some(UPM0_A::PARITY_EVEN),
10305 3 => Some(UPM0_A::PARITY_ODD),
10306 _ => None,
10307 }
10308 }
10309 ///Disabled
10310 #[inline(always)]
10311 pub fn is_disabled(&self) -> bool {
10312 *self == UPM0_A::DISABLED
10313 }
10314 ///Enabled, Even Parity
10315 #[inline(always)]
10316 pub fn is_parity_even(&self) -> bool {
10317 *self == UPM0_A::PARITY_EVEN
10318 }
10319 ///Enabled, Odd Parity
10320 #[inline(always)]
10321 pub fn is_parity_odd(&self) -> bool {
10322 *self == UPM0_A::PARITY_ODD
10323 }
10324 }
10325 ///Field `UPM0` writer - Parity Mode Bits
10326 pub type UPM0_W<'a, REG> = crate::FieldWriter<'a, REG, 2, UPM0_A>;
10327 impl<'a, REG> UPM0_W<'a, REG>
10328 where
10329 REG: crate::Writable + crate::RegisterSpec,
10330 REG::Ux: From<u8>,
10331 {
10332 ///Disabled
10333 #[inline(always)]
10334 pub fn disabled(self) -> &'a mut crate::W<REG> {
10335 self.variant(UPM0_A::DISABLED)
10336 }
10337 ///Enabled, Even Parity
10338 #[inline(always)]
10339 pub fn parity_even(self) -> &'a mut crate::W<REG> {
10340 self.variant(UPM0_A::PARITY_EVEN)
10341 }
10342 ///Enabled, Odd Parity
10343 #[inline(always)]
10344 pub fn parity_odd(self) -> &'a mut crate::W<REG> {
10345 self.variant(UPM0_A::PARITY_ODD)
10346 }
10347 }
10348 /**USART Mode Select
10349
10350Value on reset: 0*/
10351 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
10352 #[repr(u8)]
10353 pub enum UMSEL0_A {
10354 ///0: Asynchronous USART
10355 USART_ASYNC = 0,
10356 ///1: Synchronous USART
10357 USART_SYNC = 1,
10358 ///3: Master SPI (MSPIM)
10359 SPI_MASTER = 3,
10360 }
10361 impl From<UMSEL0_A> for u8 {
10362 #[inline(always)]
10363 fn from(variant: UMSEL0_A) -> Self {
10364 variant as _
10365 }
10366 }
10367 impl crate::FieldSpec for UMSEL0_A {
10368 type Ux = u8;
10369 }
10370 impl crate::IsEnum for UMSEL0_A {}
10371 ///Field `UMSEL0` reader - USART Mode Select
10372 pub type UMSEL0_R = crate::FieldReader<UMSEL0_A>;
10373 impl UMSEL0_R {
10374 ///Get enumerated values variant
10375 #[inline(always)]
10376 pub const fn variant(&self) -> Option<UMSEL0_A> {
10377 match self.bits {
10378 0 => Some(UMSEL0_A::USART_ASYNC),
10379 1 => Some(UMSEL0_A::USART_SYNC),
10380 3 => Some(UMSEL0_A::SPI_MASTER),
10381 _ => None,
10382 }
10383 }
10384 ///Asynchronous USART
10385 #[inline(always)]
10386 pub fn is_usart_async(&self) -> bool {
10387 *self == UMSEL0_A::USART_ASYNC
10388 }
10389 ///Synchronous USART
10390 #[inline(always)]
10391 pub fn is_usart_sync(&self) -> bool {
10392 *self == UMSEL0_A::USART_SYNC
10393 }
10394 ///Master SPI (MSPIM)
10395 #[inline(always)]
10396 pub fn is_spi_master(&self) -> bool {
10397 *self == UMSEL0_A::SPI_MASTER
10398 }
10399 }
10400 ///Field `UMSEL0` writer - USART Mode Select
10401 pub type UMSEL0_W<'a, REG> = crate::FieldWriter<'a, REG, 2, UMSEL0_A>;
10402 impl<'a, REG> UMSEL0_W<'a, REG>
10403 where
10404 REG: crate::Writable + crate::RegisterSpec,
10405 REG::Ux: From<u8>,
10406 {
10407 ///Asynchronous USART
10408 #[inline(always)]
10409 pub fn usart_async(self) -> &'a mut crate::W<REG> {
10410 self.variant(UMSEL0_A::USART_ASYNC)
10411 }
10412 ///Synchronous USART
10413 #[inline(always)]
10414 pub fn usart_sync(self) -> &'a mut crate::W<REG> {
10415 self.variant(UMSEL0_A::USART_SYNC)
10416 }
10417 ///Master SPI (MSPIM)
10418 #[inline(always)]
10419 pub fn spi_master(self) -> &'a mut crate::W<REG> {
10420 self.variant(UMSEL0_A::SPI_MASTER)
10421 }
10422 }
10423 impl R {
10424 ///Bit 0 - Clock Polarity
10425 #[inline(always)]
10426 pub fn ucpol0(&self) -> UCPOL0_R {
10427 UCPOL0_R::new((self.bits & 1) != 0)
10428 }
10429 ///Bits 1:2 - Character Size
10430 #[inline(always)]
10431 pub fn ucsz0(&self) -> UCSZ0_R {
10432 UCSZ0_R::new((self.bits >> 1) & 3)
10433 }
10434 ///Bit 3 - Stop Bit Select
10435 #[inline(always)]
10436 pub fn usbs0(&self) -> USBS0_R {
10437 USBS0_R::new(((self.bits >> 3) & 1) != 0)
10438 }
10439 ///Bits 4:5 - Parity Mode Bits
10440 #[inline(always)]
10441 pub fn upm0(&self) -> UPM0_R {
10442 UPM0_R::new((self.bits >> 4) & 3)
10443 }
10444 ///Bits 6:7 - USART Mode Select
10445 #[inline(always)]
10446 pub fn umsel0(&self) -> UMSEL0_R {
10447 UMSEL0_R::new((self.bits >> 6) & 3)
10448 }
10449 }
10450 impl W {
10451 ///Bit 0 - Clock Polarity
10452 #[inline(always)]
10453 pub fn ucpol0(&mut self) -> UCPOL0_W<'_, UCSR0C_SPEC> {
10454 UCPOL0_W::new(self, 0)
10455 }
10456 ///Bits 1:2 - Character Size
10457 #[inline(always)]
10458 pub fn ucsz0(&mut self) -> UCSZ0_W<'_, UCSR0C_SPEC> {
10459 UCSZ0_W::new(self, 1)
10460 }
10461 ///Bit 3 - Stop Bit Select
10462 #[inline(always)]
10463 pub fn usbs0(&mut self) -> USBS0_W<'_, UCSR0C_SPEC> {
10464 USBS0_W::new(self, 3)
10465 }
10466 ///Bits 4:5 - Parity Mode Bits
10467 #[inline(always)]
10468 pub fn upm0(&mut self) -> UPM0_W<'_, UCSR0C_SPEC> {
10469 UPM0_W::new(self, 4)
10470 }
10471 ///Bits 6:7 - USART Mode Select
10472 #[inline(always)]
10473 pub fn umsel0(&mut self) -> UMSEL0_W<'_, UCSR0C_SPEC> {
10474 UMSEL0_W::new(self, 6)
10475 }
10476 }
10477 /**USART Control and Status Register C
10478
10479You can [`read`](crate::Reg::read) this register and get [`ucsr0c::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucsr0c::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
10480 pub struct UCSR0C_SPEC;
10481 impl crate::RegisterSpec for UCSR0C_SPEC {
10482 type Ux = u8;
10483 }
10484 ///`read()` method returns [`ucsr0c::R`](R) reader structure
10485 impl crate::Readable for UCSR0C_SPEC {}
10486 ///`write(|w| ..)` method takes [`ucsr0c::W`](W) writer structure
10487 impl crate::Writable for UCSR0C_SPEC {
10488 type Safety = crate::Unsafe;
10489 }
10490 ///`reset()` method sets UCSR0C to value 0
10491 impl crate::Resettable for UCSR0C_SPEC {}
10492 }
10493 /**UDR0 (rw) register accessor: USART I/O Data Register
10494
10495You can [`read`](crate::Reg::read) this register and get [`udr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`udr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
10496
10497For information about available fields see [`mod@udr0`] module*/
10498 pub type UDR0 = crate::Reg<udr0::UDR0_SPEC>;
10499 ///USART I/O Data Register
10500 pub mod udr0 {
10501 ///Register `UDR0` reader
10502 pub type R = crate::R<UDR0_SPEC>;
10503 ///Register `UDR0` writer
10504 pub type W = crate::W<UDR0_SPEC>;
10505 impl core::fmt::Debug for R {
10506 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
10507 write!(f, "{}", self.bits())
10508 }
10509 }
10510 impl W {}
10511 /**USART I/O Data Register
10512
10513You can [`read`](crate::Reg::read) this register and get [`udr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`udr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
10514 pub struct UDR0_SPEC;
10515 impl crate::RegisterSpec for UDR0_SPEC {
10516 type Ux = u8;
10517 }
10518 ///`read()` method returns [`udr0::R`](R) reader structure
10519 impl crate::Readable for UDR0_SPEC {}
10520 ///`write(|w| ..)` method takes [`udr0::W`](W) writer structure
10521 impl crate::Writable for UDR0_SPEC {
10522 type Safety = crate::Safe;
10523 }
10524 ///`reset()` method sets UDR0 to value 0
10525 impl crate::Resettable for UDR0_SPEC {}
10526 }
10527}
10528///Watchdog Timer
10529pub type WDT = crate::Periph<wdt::RegisterBlock, 0x60>;
10530impl core::fmt::Debug for WDT {
10531 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
10532 f.debug_struct("WDT").finish()
10533 }
10534}
10535///Watchdog Timer
10536pub mod wdt {
10537 #[repr(C)]
10538 ///Register block
10539 pub struct RegisterBlock {
10540 wdtcsr: WDTCSR,
10541 }
10542 impl RegisterBlock {
10543 ///0x00 - Watchdog Timer Control Register
10544 #[inline(always)]
10545 pub const fn wdtcsr(&self) -> &WDTCSR {
10546 &self.wdtcsr
10547 }
10548 }
10549 /**WDTCSR (rw) register accessor: Watchdog Timer Control Register
10550
10551You can [`read`](crate::Reg::read) this register and get [`wdtcsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdtcsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
10552
10553For information about available fields see [`mod@wdtcsr`] module*/
10554 pub type WDTCSR = crate::Reg<wdtcsr::WDTCSR_SPEC>;
10555 ///Watchdog Timer Control Register
10556 pub mod wdtcsr {
10557 ///Register `WDTCSR` reader
10558 pub type R = crate::R<WDTCSR_SPEC>;
10559 ///Register `WDTCSR` writer
10560 pub type W = crate::W<WDTCSR_SPEC>;
10561 /**Watchdog Timer Prescaler - Low Bits
10562
10563Value on reset: 0*/
10564 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
10565 #[repr(u8)]
10566 pub enum WDPL_A {
10567 ///0: - 2048 cycles, ~16ms/512K (524288) cycles, ~4s if WDPH is set
10568 CYCLES_2K_512K = 0,
10569 ///1: - 4096 cycles, ~32ms/1024K (1048576) cycles, ~8s if WDPH is set
10570 CYCLES_4K_1024K = 1,
10571 ///2: - 8192 cycles, ~64ms
10572 CYCLES_8K = 2,
10573 ///3: - 16K (16384) cycles, ~0.125s
10574 CYCLES_16K = 3,
10575 ///4: - 32K (32768) cycles, ~0.25s
10576 CYCLES_32K = 4,
10577 ///5: - 64K (65536) cycles, ~0.5s
10578 CYCLES_64K = 5,
10579 ///6: - 128K (131072) cycles, ~1s
10580 CYCLES_128K = 6,
10581 ///7: - 256K (262144) cycles, ~2s
10582 CYCLES_256K = 7,
10583 }
10584 impl From<WDPL_A> for u8 {
10585 #[inline(always)]
10586 fn from(variant: WDPL_A) -> Self {
10587 variant as _
10588 }
10589 }
10590 impl crate::FieldSpec for WDPL_A {
10591 type Ux = u8;
10592 }
10593 impl crate::IsEnum for WDPL_A {}
10594 ///Field `WDPL` reader - Watchdog Timer Prescaler - Low Bits
10595 pub type WDPL_R = crate::FieldReader<WDPL_A>;
10596 impl WDPL_R {
10597 ///Get enumerated values variant
10598 #[inline(always)]
10599 pub const fn variant(&self) -> WDPL_A {
10600 match self.bits {
10601 0 => WDPL_A::CYCLES_2K_512K,
10602 1 => WDPL_A::CYCLES_4K_1024K,
10603 2 => WDPL_A::CYCLES_8K,
10604 3 => WDPL_A::CYCLES_16K,
10605 4 => WDPL_A::CYCLES_32K,
10606 5 => WDPL_A::CYCLES_64K,
10607 6 => WDPL_A::CYCLES_128K,
10608 7 => WDPL_A::CYCLES_256K,
10609 _ => unreachable!(),
10610 }
10611 }
10612 ///- 2048 cycles, ~16ms/512K (524288) cycles, ~4s if WDPH is set
10613 #[inline(always)]
10614 pub fn is_cycles_2k_512k(&self) -> bool {
10615 *self == WDPL_A::CYCLES_2K_512K
10616 }
10617 ///- 4096 cycles, ~32ms/1024K (1048576) cycles, ~8s if WDPH is set
10618 #[inline(always)]
10619 pub fn is_cycles_4k_1024k(&self) -> bool {
10620 *self == WDPL_A::CYCLES_4K_1024K
10621 }
10622 ///- 8192 cycles, ~64ms
10623 #[inline(always)]
10624 pub fn is_cycles_8k(&self) -> bool {
10625 *self == WDPL_A::CYCLES_8K
10626 }
10627 ///- 16K (16384) cycles, ~0.125s
10628 #[inline(always)]
10629 pub fn is_cycles_16k(&self) -> bool {
10630 *self == WDPL_A::CYCLES_16K
10631 }
10632 ///- 32K (32768) cycles, ~0.25s
10633 #[inline(always)]
10634 pub fn is_cycles_32k(&self) -> bool {
10635 *self == WDPL_A::CYCLES_32K
10636 }
10637 ///- 64K (65536) cycles, ~0.5s
10638 #[inline(always)]
10639 pub fn is_cycles_64k(&self) -> bool {
10640 *self == WDPL_A::CYCLES_64K
10641 }
10642 ///- 128K (131072) cycles, ~1s
10643 #[inline(always)]
10644 pub fn is_cycles_128k(&self) -> bool {
10645 *self == WDPL_A::CYCLES_128K
10646 }
10647 ///- 256K (262144) cycles, ~2s
10648 #[inline(always)]
10649 pub fn is_cycles_256k(&self) -> bool {
10650 *self == WDPL_A::CYCLES_256K
10651 }
10652 }
10653 ///Field `WDPL` writer - Watchdog Timer Prescaler - Low Bits
10654 pub type WDPL_W<'a, REG> = crate::FieldWriter<'a, REG, 3, WDPL_A, crate::Safe>;
10655 impl<'a, REG> WDPL_W<'a, REG>
10656 where
10657 REG: crate::Writable + crate::RegisterSpec,
10658 REG::Ux: From<u8>,
10659 {
10660 ///- 2048 cycles, ~16ms/512K (524288) cycles, ~4s if WDPH is set
10661 #[inline(always)]
10662 pub fn cycles_2k_512k(self) -> &'a mut crate::W<REG> {
10663 self.variant(WDPL_A::CYCLES_2K_512K)
10664 }
10665 ///- 4096 cycles, ~32ms/1024K (1048576) cycles, ~8s if WDPH is set
10666 #[inline(always)]
10667 pub fn cycles_4k_1024k(self) -> &'a mut crate::W<REG> {
10668 self.variant(WDPL_A::CYCLES_4K_1024K)
10669 }
10670 ///- 8192 cycles, ~64ms
10671 #[inline(always)]
10672 pub fn cycles_8k(self) -> &'a mut crate::W<REG> {
10673 self.variant(WDPL_A::CYCLES_8K)
10674 }
10675 ///- 16K (16384) cycles, ~0.125s
10676 #[inline(always)]
10677 pub fn cycles_16k(self) -> &'a mut crate::W<REG> {
10678 self.variant(WDPL_A::CYCLES_16K)
10679 }
10680 ///- 32K (32768) cycles, ~0.25s
10681 #[inline(always)]
10682 pub fn cycles_32k(self) -> &'a mut crate::W<REG> {
10683 self.variant(WDPL_A::CYCLES_32K)
10684 }
10685 ///- 64K (65536) cycles, ~0.5s
10686 #[inline(always)]
10687 pub fn cycles_64k(self) -> &'a mut crate::W<REG> {
10688 self.variant(WDPL_A::CYCLES_64K)
10689 }
10690 ///- 128K (131072) cycles, ~1s
10691 #[inline(always)]
10692 pub fn cycles_128k(self) -> &'a mut crate::W<REG> {
10693 self.variant(WDPL_A::CYCLES_128K)
10694 }
10695 ///- 256K (262144) cycles, ~2s
10696 #[inline(always)]
10697 pub fn cycles_256k(self) -> &'a mut crate::W<REG> {
10698 self.variant(WDPL_A::CYCLES_256K)
10699 }
10700 }
10701 ///Field `WDE` reader - Watch Dog Enable
10702 pub type WDE_R = crate::BitReader;
10703 ///Field `WDE` writer - Watch Dog Enable
10704 pub type WDE_W<'a, REG> = crate::BitWriter<'a, REG>;
10705 ///Field `WDCE` reader - Watchdog Change Enable
10706 pub type WDCE_R = crate::BitReader;
10707 ///Field `WDCE` writer - Watchdog Change Enable
10708 pub type WDCE_W<'a, REG> = crate::BitWriter<'a, REG>;
10709 ///Field `WDPH` reader - Watchdog Timer Prescaler - High Bit
10710 pub type WDPH_R = crate::BitReader;
10711 ///Field `WDPH` writer - Watchdog Timer Prescaler - High Bit
10712 pub type WDPH_W<'a, REG> = crate::BitWriter<'a, REG>;
10713 ///Field `WDIE` reader - Watchdog Timeout Interrupt Enable
10714 pub type WDIE_R = crate::BitReader;
10715 ///Field `WDIE` writer - Watchdog Timeout Interrupt Enable
10716 pub type WDIE_W<'a, REG> = crate::BitWriter<'a, REG>;
10717 ///Field `WDIF` reader - Watchdog Timeout Interrupt Flag
10718 pub type WDIF_R = crate::BitReader;
10719 ///Field `WDIF` writer - Watchdog Timeout Interrupt Flag
10720 pub type WDIF_W<'a, REG> = crate::BitWriter<'a, REG>;
10721 impl R {
10722 ///Bits 0:2 - Watchdog Timer Prescaler - Low Bits
10723 #[inline(always)]
10724 pub fn wdpl(&self) -> WDPL_R {
10725 WDPL_R::new(self.bits & 7)
10726 }
10727 ///Bit 3 - Watch Dog Enable
10728 #[inline(always)]
10729 pub fn wde(&self) -> WDE_R {
10730 WDE_R::new(((self.bits >> 3) & 1) != 0)
10731 }
10732 ///Bit 4 - Watchdog Change Enable
10733 #[inline(always)]
10734 pub fn wdce(&self) -> WDCE_R {
10735 WDCE_R::new(((self.bits >> 4) & 1) != 0)
10736 }
10737 ///Bit 5 - Watchdog Timer Prescaler - High Bit
10738 #[inline(always)]
10739 pub fn wdph(&self) -> WDPH_R {
10740 WDPH_R::new(((self.bits >> 5) & 1) != 0)
10741 }
10742 ///Bit 6 - Watchdog Timeout Interrupt Enable
10743 #[inline(always)]
10744 pub fn wdie(&self) -> WDIE_R {
10745 WDIE_R::new(((self.bits >> 6) & 1) != 0)
10746 }
10747 ///Bit 7 - Watchdog Timeout Interrupt Flag
10748 #[inline(always)]
10749 pub fn wdif(&self) -> WDIF_R {
10750 WDIF_R::new(((self.bits >> 7) & 1) != 0)
10751 }
10752 }
10753 impl W {
10754 ///Bits 0:2 - Watchdog Timer Prescaler - Low Bits
10755 #[inline(always)]
10756 pub fn wdpl(&mut self) -> WDPL_W<'_, WDTCSR_SPEC> {
10757 WDPL_W::new(self, 0)
10758 }
10759 ///Bit 3 - Watch Dog Enable
10760 #[inline(always)]
10761 pub fn wde(&mut self) -> WDE_W<'_, WDTCSR_SPEC> {
10762 WDE_W::new(self, 3)
10763 }
10764 ///Bit 4 - Watchdog Change Enable
10765 #[inline(always)]
10766 pub fn wdce(&mut self) -> WDCE_W<'_, WDTCSR_SPEC> {
10767 WDCE_W::new(self, 4)
10768 }
10769 ///Bit 5 - Watchdog Timer Prescaler - High Bit
10770 #[inline(always)]
10771 pub fn wdph(&mut self) -> WDPH_W<'_, WDTCSR_SPEC> {
10772 WDPH_W::new(self, 5)
10773 }
10774 ///Bit 6 - Watchdog Timeout Interrupt Enable
10775 #[inline(always)]
10776 pub fn wdie(&mut self) -> WDIE_W<'_, WDTCSR_SPEC> {
10777 WDIE_W::new(self, 6)
10778 }
10779 ///Bit 7 - Watchdog Timeout Interrupt Flag
10780 #[inline(always)]
10781 pub fn wdif(&mut self) -> WDIF_W<'_, WDTCSR_SPEC> {
10782 WDIF_W::new(self, 7)
10783 }
10784 }
10785 /**Watchdog Timer Control Register
10786
10787You can [`read`](crate::Reg::read) this register and get [`wdtcsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdtcsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
10788 pub struct WDTCSR_SPEC;
10789 impl crate::RegisterSpec for WDTCSR_SPEC {
10790 type Ux = u8;
10791 }
10792 ///`read()` method returns [`wdtcsr::R`](R) reader structure
10793 impl crate::Readable for WDTCSR_SPEC {}
10794 ///`write(|w| ..)` method takes [`wdtcsr::W`](W) writer structure
10795 impl crate::Writable for WDTCSR_SPEC {
10796 type Safety = crate::Unsafe;
10797 }
10798 ///`reset()` method sets WDTCSR to value 0
10799 impl crate::Resettable for WDTCSR_SPEC {}
10800 }
10801}
10802use super::DEVICE_PERIPHERALS;
10803/// All the peripherals.
10804#[allow(non_snake_case)]
10805pub struct Peripherals {
10806 ///AC
10807 pub AC: AC,
10808 ///ADC
10809 pub ADC: ADC,
10810 ///CPU
10811 pub CPU: CPU,
10812 ///EEPROM
10813 pub EEPROM: EEPROM,
10814 ///EXINT
10815 pub EXINT: EXINT,
10816 ///FUSE
10817 pub FUSE: FUSE,
10818 ///LOCKBIT
10819 pub LOCKBIT: LOCKBIT,
10820 ///PORTB
10821 pub PORTB: PORTB,
10822 ///PORTC
10823 pub PORTC: PORTC,
10824 ///PORTD
10825 pub PORTD: PORTD,
10826 ///SPI
10827 pub SPI: SPI,
10828 ///TC0
10829 pub TC0: TC0,
10830 ///TC1
10831 pub TC1: TC1,
10832 ///TC2
10833 pub TC2: TC2,
10834 ///TWI
10835 pub TWI: TWI,
10836 ///USART0
10837 pub USART0: USART0,
10838 ///WDT
10839 pub WDT: WDT,
10840}
10841impl Peripherals {
10842 /// Returns all the peripherals *once*.
10843 #[cfg(feature = "critical-section")]
10844 #[inline]
10845 pub fn take() -> Option<Self> {
10846 critical_section::with(|_| {
10847 if unsafe { DEVICE_PERIPHERALS } {
10848 return None;
10849 }
10850 Some(unsafe { Peripherals::steal() })
10851 })
10852 }
10853 /// Unchecked version of `Peripherals::take`.
10854 ///
10855 /// # Safety
10856 ///
10857 /// Each of the returned peripherals must be used at most once.
10858 #[inline]
10859 pub unsafe fn steal() -> Self {
10860 DEVICE_PERIPHERALS = true;
10861 Peripherals {
10862 AC: AC::steal(),
10863 ADC: ADC::steal(),
10864 CPU: CPU::steal(),
10865 EEPROM: EEPROM::steal(),
10866 EXINT: EXINT::steal(),
10867 FUSE: FUSE::steal(),
10868 LOCKBIT: LOCKBIT::steal(),
10869 PORTB: PORTB::steal(),
10870 PORTC: PORTC::steal(),
10871 PORTD: PORTD::steal(),
10872 SPI: SPI::steal(),
10873 TC0: TC0::steal(),
10874 TC1: TC1::steal(),
10875 TC2: TC2::steal(),
10876 TWI: TWI::steal(),
10877 USART0: USART0::steal(),
10878 WDT: WDT::steal(),
10879 }
10880 }
10881}