avr_device/home/runner/work/avr-hal/avr-hal/target/debug/build/avr-device-84ef91813b9acd77/out/pac/attiny85.rs
1///Number available in the NVIC for configuring priority
2pub const NVIC_PRIO_BITS: u8 = 4;
3#[doc(hidden)]
4pub mod interrupt {
5 ///Enumeration of all the interrupts.
6 #[derive(Copy, Clone, Debug, PartialEq, Eq)]
7 #[repr(u16)]
8 pub enum Interrupt {
9 ///0 - External Pin, Power-on Reset, Brown-out Reset,Watchdog Reset
10 RESET = 0,
11 ///1 - External Interrupt 0
12 INT0 = 1,
13 ///2 - Pin change Interrupt Request 0
14 PCINT0 = 2,
15 ///3 - Timer/Counter1 Compare Match 1A
16 TIMER1_COMPA = 3,
17 ///4 - Timer/Counter1 Overflow
18 TIMER1_OVF = 4,
19 ///5 - Timer/Counter0 Overflow
20 TIMER0_OVF = 5,
21 ///6 - EEPROM Ready
22 EE_RDY = 6,
23 ///7 - Analog comparator
24 ANA_COMP = 7,
25 ///8 - ADC Conversion ready
26 ADC = 8,
27 ///9 - Timer/Counter1 Compare Match B
28 TIMER1_COMPB = 9,
29 ///10 - Timer/Counter0 Compare Match A
30 TIMER0_COMPA = 10,
31 ///11 - Timer/Counter0 Compare Match B
32 TIMER0_COMPB = 11,
33 ///12 - Watchdog Time-out
34 WDT = 12,
35 ///13 - USI START
36 USI_START = 13,
37 ///14 - USI Overflow
38 USI_OVF = 14,
39 }
40 /// TryFromInterruptError
41 #[derive(Debug, Copy, Clone)]
42 pub struct TryFromInterruptError(());
43 impl Interrupt {
44 /// Attempt to convert a given value into an `Interrupt`
45 #[inline]
46 pub fn try_from(value: u8) -> Result<Self, TryFromInterruptError> {
47 match value {
48 0 => Ok(Interrupt::RESET),
49 1 => Ok(Interrupt::INT0),
50 2 => Ok(Interrupt::PCINT0),
51 3 => Ok(Interrupt::TIMER1_COMPA),
52 4 => Ok(Interrupt::TIMER1_OVF),
53 5 => Ok(Interrupt::TIMER0_OVF),
54 6 => Ok(Interrupt::EE_RDY),
55 7 => Ok(Interrupt::ANA_COMP),
56 8 => Ok(Interrupt::ADC),
57 9 => Ok(Interrupt::TIMER1_COMPB),
58 10 => Ok(Interrupt::TIMER0_COMPA),
59 11 => Ok(Interrupt::TIMER0_COMPB),
60 12 => Ok(Interrupt::WDT),
61 13 => Ok(Interrupt::USI_START),
62 14 => Ok(Interrupt::USI_OVF),
63 _ => Err(TryFromInterruptError(())),
64 }
65 }
66 }
67}
68pub use self::interrupt::Interrupt;
69///Analog Comparator
70pub type AC = crate::Periph<ac::RegisterBlock, 0x23>;
71impl core::fmt::Debug for AC {
72 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
73 f.debug_struct("AC").finish()
74 }
75}
76///Analog Comparator
77pub mod ac {
78 #[repr(C)]
79 ///Register block
80 pub struct RegisterBlock {
81 adcsrb: ADCSRB,
82 _reserved1: [u8; 0x04],
83 acsr: ACSR,
84 _reserved2: [u8; 0x0b],
85 didr0: DIDR0,
86 }
87 impl RegisterBlock {
88 ///0x00 - ADC Control and Status Register B
89 #[inline(always)]
90 pub const fn adcsrb(&self) -> &ADCSRB {
91 &self.adcsrb
92 }
93 ///0x05 - Analog Comparator Control And Status Register
94 #[inline(always)]
95 pub const fn acsr(&self) -> &ACSR {
96 &self.acsr
97 }
98 ///0x11 - Digital Input Disable Register 0
99 #[inline(always)]
100 pub const fn didr0(&self) -> &DIDR0 {
101 &self.didr0
102 }
103 }
104 /**ACSR (rw) register accessor: Analog Comparator Control And Status Register
105
106You can [`read`](crate::Reg::read) this register and get [`acsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`acsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
107
108For information about available fields see [`mod@acsr`] module*/
109 pub type ACSR = crate::Reg<acsr::ACSR_SPEC>;
110 ///Analog Comparator Control And Status Register
111 pub mod acsr {
112 ///Register `ACSR` reader
113 pub type R = crate::R<ACSR_SPEC>;
114 ///Register `ACSR` writer
115 pub type W = crate::W<ACSR_SPEC>;
116 /**Analog Comparator Interrupt Mode Select
117
118Value on reset: 0*/
119 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
120 #[repr(u8)]
121 pub enum ACIS_A {
122 ///0: Interrupt on Toggle
123 ON_TOGGLE = 0,
124 ///2: Interrupt on Falling Edge
125 ON_FALLING_EDGE = 2,
126 ///3: Interrupt on Rising Edge
127 ON_RISING_EDGE = 3,
128 }
129 impl From<ACIS_A> for u8 {
130 #[inline(always)]
131 fn from(variant: ACIS_A) -> Self {
132 variant as _
133 }
134 }
135 impl crate::FieldSpec for ACIS_A {
136 type Ux = u8;
137 }
138 impl crate::IsEnum for ACIS_A {}
139 ///Field `ACIS` reader - Analog Comparator Interrupt Mode Select
140 pub type ACIS_R = crate::FieldReader<ACIS_A>;
141 impl ACIS_R {
142 ///Get enumerated values variant
143 #[inline(always)]
144 pub const fn variant(&self) -> Option<ACIS_A> {
145 match self.bits {
146 0 => Some(ACIS_A::ON_TOGGLE),
147 2 => Some(ACIS_A::ON_FALLING_EDGE),
148 3 => Some(ACIS_A::ON_RISING_EDGE),
149 _ => None,
150 }
151 }
152 ///Interrupt on Toggle
153 #[inline(always)]
154 pub fn is_on_toggle(&self) -> bool {
155 *self == ACIS_A::ON_TOGGLE
156 }
157 ///Interrupt on Falling Edge
158 #[inline(always)]
159 pub fn is_on_falling_edge(&self) -> bool {
160 *self == ACIS_A::ON_FALLING_EDGE
161 }
162 ///Interrupt on Rising Edge
163 #[inline(always)]
164 pub fn is_on_rising_edge(&self) -> bool {
165 *self == ACIS_A::ON_RISING_EDGE
166 }
167 }
168 ///Field `ACIS` writer - Analog Comparator Interrupt Mode Select
169 pub type ACIS_W<'a, REG> = crate::FieldWriter<'a, REG, 2, ACIS_A>;
170 impl<'a, REG> ACIS_W<'a, REG>
171 where
172 REG: crate::Writable + crate::RegisterSpec,
173 REG::Ux: From<u8>,
174 {
175 ///Interrupt on Toggle
176 #[inline(always)]
177 pub fn on_toggle(self) -> &'a mut crate::W<REG> {
178 self.variant(ACIS_A::ON_TOGGLE)
179 }
180 ///Interrupt on Falling Edge
181 #[inline(always)]
182 pub fn on_falling_edge(self) -> &'a mut crate::W<REG> {
183 self.variant(ACIS_A::ON_FALLING_EDGE)
184 }
185 ///Interrupt on Rising Edge
186 #[inline(always)]
187 pub fn on_rising_edge(self) -> &'a mut crate::W<REG> {
188 self.variant(ACIS_A::ON_RISING_EDGE)
189 }
190 }
191 ///Field `ACIE` reader - Analog Comparator Interrupt Enable
192 pub type ACIE_R = crate::BitReader;
193 ///Field `ACIE` writer - Analog Comparator Interrupt Enable
194 pub type ACIE_W<'a, REG> = crate::BitWriter<'a, REG>;
195 ///Field `ACI` reader - Analog Comparator Interrupt Flag
196 pub type ACI_R = crate::BitReader;
197 ///Field `ACI` writer - Analog Comparator Interrupt Flag
198 pub type ACI_W<'a, REG> = crate::BitWriter<'a, REG>;
199 ///Field `ACO` reader - Analog Compare Output
200 pub type ACO_R = crate::BitReader;
201 ///Field `ACBG` reader - Analog Comparator Bandgap Select
202 pub type ACBG_R = crate::BitReader;
203 ///Field `ACBG` writer - Analog Comparator Bandgap Select
204 pub type ACBG_W<'a, REG> = crate::BitWriter<'a, REG>;
205 ///Field `ACD` reader - Analog Comparator Disable
206 pub type ACD_R = crate::BitReader;
207 ///Field `ACD` writer - Analog Comparator Disable
208 pub type ACD_W<'a, REG> = crate::BitWriter<'a, REG>;
209 impl R {
210 ///Bits 0:1 - Analog Comparator Interrupt Mode Select
211 #[inline(always)]
212 pub fn acis(&self) -> ACIS_R {
213 ACIS_R::new(self.bits & 3)
214 }
215 ///Bit 3 - Analog Comparator Interrupt Enable
216 #[inline(always)]
217 pub fn acie(&self) -> ACIE_R {
218 ACIE_R::new(((self.bits >> 3) & 1) != 0)
219 }
220 ///Bit 4 - Analog Comparator Interrupt Flag
221 #[inline(always)]
222 pub fn aci(&self) -> ACI_R {
223 ACI_R::new(((self.bits >> 4) & 1) != 0)
224 }
225 ///Bit 5 - Analog Compare Output
226 #[inline(always)]
227 pub fn aco(&self) -> ACO_R {
228 ACO_R::new(((self.bits >> 5) & 1) != 0)
229 }
230 ///Bit 6 - Analog Comparator Bandgap Select
231 #[inline(always)]
232 pub fn acbg(&self) -> ACBG_R {
233 ACBG_R::new(((self.bits >> 6) & 1) != 0)
234 }
235 ///Bit 7 - Analog Comparator Disable
236 #[inline(always)]
237 pub fn acd(&self) -> ACD_R {
238 ACD_R::new(((self.bits >> 7) & 1) != 0)
239 }
240 }
241 impl W {
242 ///Bits 0:1 - Analog Comparator Interrupt Mode Select
243 #[inline(always)]
244 pub fn acis(&mut self) -> ACIS_W<'_, ACSR_SPEC> {
245 ACIS_W::new(self, 0)
246 }
247 ///Bit 3 - Analog Comparator Interrupt Enable
248 #[inline(always)]
249 pub fn acie(&mut self) -> ACIE_W<'_, ACSR_SPEC> {
250 ACIE_W::new(self, 3)
251 }
252 ///Bit 4 - Analog Comparator Interrupt Flag
253 #[inline(always)]
254 pub fn aci(&mut self) -> ACI_W<'_, ACSR_SPEC> {
255 ACI_W::new(self, 4)
256 }
257 ///Bit 6 - Analog Comparator Bandgap Select
258 #[inline(always)]
259 pub fn acbg(&mut self) -> ACBG_W<'_, ACSR_SPEC> {
260 ACBG_W::new(self, 6)
261 }
262 ///Bit 7 - Analog Comparator Disable
263 #[inline(always)]
264 pub fn acd(&mut self) -> ACD_W<'_, ACSR_SPEC> {
265 ACD_W::new(self, 7)
266 }
267 }
268 /**Analog Comparator Control And Status Register
269
270You can [`read`](crate::Reg::read) this register and get [`acsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`acsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
271 pub struct ACSR_SPEC;
272 impl crate::RegisterSpec for ACSR_SPEC {
273 type Ux = u8;
274 }
275 ///`read()` method returns [`acsr::R`](R) reader structure
276 impl crate::Readable for ACSR_SPEC {}
277 ///`write(|w| ..)` method takes [`acsr::W`](W) writer structure
278 impl crate::Writable for ACSR_SPEC {
279 type Safety = crate::Unsafe;
280 }
281 ///`reset()` method sets ACSR to value 0
282 impl crate::Resettable for ACSR_SPEC {}
283 }
284 /**ADCSRB (rw) register accessor: ADC Control and Status Register B
285
286You can [`read`](crate::Reg::read) this register and get [`adcsrb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adcsrb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
287
288For information about available fields see [`mod@adcsrb`] module*/
289 pub type ADCSRB = crate::Reg<adcsrb::ADCSRB_SPEC>;
290 ///ADC Control and Status Register B
291 pub mod adcsrb {
292 ///Register `ADCSRB` reader
293 pub type R = crate::R<ADCSRB_SPEC>;
294 ///Register `ADCSRB` writer
295 pub type W = crate::W<ADCSRB_SPEC>;
296 ///Field `ACME` reader - Analog Comparator Multiplexer Enable
297 pub type ACME_R = crate::BitReader;
298 ///Field `ACME` writer - Analog Comparator Multiplexer Enable
299 pub type ACME_W<'a, REG> = crate::BitWriter<'a, REG>;
300 impl R {
301 ///Bit 6 - Analog Comparator Multiplexer Enable
302 #[inline(always)]
303 pub fn acme(&self) -> ACME_R {
304 ACME_R::new(((self.bits >> 6) & 1) != 0)
305 }
306 }
307 impl W {
308 ///Bit 6 - Analog Comparator Multiplexer Enable
309 #[inline(always)]
310 pub fn acme(&mut self) -> ACME_W<'_, ADCSRB_SPEC> {
311 ACME_W::new(self, 6)
312 }
313 }
314 /**ADC Control and Status Register B
315
316You can [`read`](crate::Reg::read) this register and get [`adcsrb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adcsrb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
317 pub struct ADCSRB_SPEC;
318 impl crate::RegisterSpec for ADCSRB_SPEC {
319 type Ux = u8;
320 }
321 ///`read()` method returns [`adcsrb::R`](R) reader structure
322 impl crate::Readable for ADCSRB_SPEC {}
323 ///`write(|w| ..)` method takes [`adcsrb::W`](W) writer structure
324 impl crate::Writable for ADCSRB_SPEC {
325 type Safety = crate::Unsafe;
326 }
327 ///`reset()` method sets ADCSRB to value 0
328 impl crate::Resettable for ADCSRB_SPEC {}
329 }
330 /**DIDR0 (rw) register accessor: Digital Input Disable Register 0
331
332You can [`read`](crate::Reg::read) this register and get [`didr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`didr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
333
334For information about available fields see [`mod@didr0`] module*/
335 pub type DIDR0 = crate::Reg<didr0::DIDR0_SPEC>;
336 ///Digital Input Disable Register 0
337 pub mod didr0 {
338 ///Register `DIDR0` reader
339 pub type R = crate::R<DIDR0_SPEC>;
340 ///Register `DIDR0` writer
341 pub type W = crate::W<DIDR0_SPEC>;
342 ///Field `AIN0D` reader - AIN0 Digital Input Disable
343 pub type AIN0D_R = crate::BitReader;
344 ///Field `AIN0D` writer - AIN0 Digital Input Disable
345 pub type AIN0D_W<'a, REG> = crate::BitWriter<'a, REG>;
346 ///Field `AIN1D` reader - AIN1 Digital Input Disable
347 pub type AIN1D_R = crate::BitReader;
348 ///Field `AIN1D` writer - AIN1 Digital Input Disable
349 pub type AIN1D_W<'a, REG> = crate::BitWriter<'a, REG>;
350 impl R {
351 ///Bit 0 - AIN0 Digital Input Disable
352 #[inline(always)]
353 pub fn ain0d(&self) -> AIN0D_R {
354 AIN0D_R::new((self.bits & 1) != 0)
355 }
356 ///Bit 1 - AIN1 Digital Input Disable
357 #[inline(always)]
358 pub fn ain1d(&self) -> AIN1D_R {
359 AIN1D_R::new(((self.bits >> 1) & 1) != 0)
360 }
361 }
362 impl W {
363 ///Bit 0 - AIN0 Digital Input Disable
364 #[inline(always)]
365 pub fn ain0d(&mut self) -> AIN0D_W<'_, DIDR0_SPEC> {
366 AIN0D_W::new(self, 0)
367 }
368 ///Bit 1 - AIN1 Digital Input Disable
369 #[inline(always)]
370 pub fn ain1d(&mut self) -> AIN1D_W<'_, DIDR0_SPEC> {
371 AIN1D_W::new(self, 1)
372 }
373 }
374 /**Digital Input Disable Register 0
375
376You can [`read`](crate::Reg::read) this register and get [`didr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`didr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
377 pub struct DIDR0_SPEC;
378 impl crate::RegisterSpec for DIDR0_SPEC {
379 type Ux = u8;
380 }
381 ///`read()` method returns [`didr0::R`](R) reader structure
382 impl crate::Readable for DIDR0_SPEC {}
383 ///`write(|w| ..)` method takes [`didr0::W`](W) writer structure
384 impl crate::Writable for DIDR0_SPEC {
385 type Safety = crate::Unsafe;
386 }
387 ///`reset()` method sets DIDR0 to value 0
388 impl crate::Resettable for DIDR0_SPEC {}
389 }
390}
391///Analog-to-Digital Converter
392pub type ADC = crate::Periph<adc::RegisterBlock, 0x23>;
393impl core::fmt::Debug for ADC {
394 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
395 f.debug_struct("ADC").finish()
396 }
397}
398///Analog-to-Digital Converter
399pub mod adc {
400 #[repr(C)]
401 ///Register block
402 pub struct RegisterBlock {
403 adcsrb: ADCSRB,
404 adc: ADC,
405 adcsra: ADCSRA,
406 admux: ADMUX,
407 _reserved4: [u8; 0x0c],
408 didr0: DIDR0,
409 }
410 impl RegisterBlock {
411 ///0x00 - ADC Control and Status Register B
412 #[inline(always)]
413 pub const fn adcsrb(&self) -> &ADCSRB {
414 &self.adcsrb
415 }
416 ///0x01 - ADC Data Register Bytes
417 #[inline(always)]
418 pub const fn adc(&self) -> &ADC {
419 &self.adc
420 }
421 ///0x03 - ADC Control and Status Register A
422 #[inline(always)]
423 pub const fn adcsra(&self) -> &ADCSRA {
424 &self.adcsra
425 }
426 ///0x04 - The ADC multiplexer Selection Register
427 #[inline(always)]
428 pub const fn admux(&self) -> &ADMUX {
429 &self.admux
430 }
431 ///0x11 - Digital Input Disable Register 0
432 #[inline(always)]
433 pub const fn didr0(&self) -> &DIDR0 {
434 &self.didr0
435 }
436 }
437 /**ADC (rw) register accessor: ADC Data Register Bytes
438
439You can [`read`](crate::Reg::read) this register and get [`adc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
440
441For information about available fields see [`mod@adc`] module*/
442 pub type ADC = crate::Reg<adc::ADC_SPEC>;
443 ///ADC Data Register Bytes
444 pub mod adc {
445 ///Register `ADC` reader
446 pub type R = crate::R<ADC_SPEC>;
447 ///Register `ADC` writer
448 pub type W = crate::W<ADC_SPEC>;
449 impl core::fmt::Debug for R {
450 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
451 write!(f, "{}", self.bits())
452 }
453 }
454 impl W {}
455 /**ADC Data Register Bytes
456
457You can [`read`](crate::Reg::read) this register and get [`adc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
458 pub struct ADC_SPEC;
459 impl crate::RegisterSpec for ADC_SPEC {
460 type Ux = u16;
461 }
462 ///`read()` method returns [`adc::R`](R) reader structure
463 impl crate::Readable for ADC_SPEC {}
464 ///`write(|w| ..)` method takes [`adc::W`](W) writer structure
465 impl crate::Writable for ADC_SPEC {
466 type Safety = crate::Safe;
467 }
468 ///`reset()` method sets ADC to value 0
469 impl crate::Resettable for ADC_SPEC {}
470 }
471 /**ADCSRA (rw) register accessor: ADC Control and Status Register A
472
473You can [`read`](crate::Reg::read) this register and get [`adcsra::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adcsra::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
474
475For information about available fields see [`mod@adcsra`] module*/
476 pub type ADCSRA = crate::Reg<adcsra::ADCSRA_SPEC>;
477 ///ADC Control and Status Register A
478 pub mod adcsra {
479 ///Register `ADCSRA` reader
480 pub type R = crate::R<ADCSRA_SPEC>;
481 ///Register `ADCSRA` writer
482 pub type W = crate::W<ADCSRA_SPEC>;
483 /**ADC Prescaler Select Bits
484
485Value on reset: 0*/
486 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
487 #[repr(u8)]
488 pub enum ADPS_A {
489 ///1: Prescaler Value 2
490 PRESCALER_2 = 1,
491 ///2: Prescaler Value 4
492 PRESCALER_4 = 2,
493 ///3: Prescaler Value 8
494 PRESCALER_8 = 3,
495 ///4: Prescaler Value 16
496 PRESCALER_16 = 4,
497 ///5: Prescaler Value 32
498 PRESCALER_32 = 5,
499 ///6: Prescaler Value 64
500 PRESCALER_64 = 6,
501 ///7: Prescaler Value 128
502 PRESCALER_128 = 7,
503 }
504 impl From<ADPS_A> for u8 {
505 #[inline(always)]
506 fn from(variant: ADPS_A) -> Self {
507 variant as _
508 }
509 }
510 impl crate::FieldSpec for ADPS_A {
511 type Ux = u8;
512 }
513 impl crate::IsEnum for ADPS_A {}
514 ///Field `ADPS` reader - ADC Prescaler Select Bits
515 pub type ADPS_R = crate::FieldReader<ADPS_A>;
516 impl ADPS_R {
517 ///Get enumerated values variant
518 #[inline(always)]
519 pub const fn variant(&self) -> Option<ADPS_A> {
520 match self.bits {
521 1 => Some(ADPS_A::PRESCALER_2),
522 2 => Some(ADPS_A::PRESCALER_4),
523 3 => Some(ADPS_A::PRESCALER_8),
524 4 => Some(ADPS_A::PRESCALER_16),
525 5 => Some(ADPS_A::PRESCALER_32),
526 6 => Some(ADPS_A::PRESCALER_64),
527 7 => Some(ADPS_A::PRESCALER_128),
528 _ => None,
529 }
530 }
531 ///Prescaler Value 2
532 #[inline(always)]
533 pub fn is_prescaler_2(&self) -> bool {
534 *self == ADPS_A::PRESCALER_2
535 }
536 ///Prescaler Value 4
537 #[inline(always)]
538 pub fn is_prescaler_4(&self) -> bool {
539 *self == ADPS_A::PRESCALER_4
540 }
541 ///Prescaler Value 8
542 #[inline(always)]
543 pub fn is_prescaler_8(&self) -> bool {
544 *self == ADPS_A::PRESCALER_8
545 }
546 ///Prescaler Value 16
547 #[inline(always)]
548 pub fn is_prescaler_16(&self) -> bool {
549 *self == ADPS_A::PRESCALER_16
550 }
551 ///Prescaler Value 32
552 #[inline(always)]
553 pub fn is_prescaler_32(&self) -> bool {
554 *self == ADPS_A::PRESCALER_32
555 }
556 ///Prescaler Value 64
557 #[inline(always)]
558 pub fn is_prescaler_64(&self) -> bool {
559 *self == ADPS_A::PRESCALER_64
560 }
561 ///Prescaler Value 128
562 #[inline(always)]
563 pub fn is_prescaler_128(&self) -> bool {
564 *self == ADPS_A::PRESCALER_128
565 }
566 }
567 ///Field `ADPS` writer - ADC Prescaler Select Bits
568 pub type ADPS_W<'a, REG> = crate::FieldWriter<'a, REG, 3, ADPS_A>;
569 impl<'a, REG> ADPS_W<'a, REG>
570 where
571 REG: crate::Writable + crate::RegisterSpec,
572 REG::Ux: From<u8>,
573 {
574 ///Prescaler Value 2
575 #[inline(always)]
576 pub fn prescaler_2(self) -> &'a mut crate::W<REG> {
577 self.variant(ADPS_A::PRESCALER_2)
578 }
579 ///Prescaler Value 4
580 #[inline(always)]
581 pub fn prescaler_4(self) -> &'a mut crate::W<REG> {
582 self.variant(ADPS_A::PRESCALER_4)
583 }
584 ///Prescaler Value 8
585 #[inline(always)]
586 pub fn prescaler_8(self) -> &'a mut crate::W<REG> {
587 self.variant(ADPS_A::PRESCALER_8)
588 }
589 ///Prescaler Value 16
590 #[inline(always)]
591 pub fn prescaler_16(self) -> &'a mut crate::W<REG> {
592 self.variant(ADPS_A::PRESCALER_16)
593 }
594 ///Prescaler Value 32
595 #[inline(always)]
596 pub fn prescaler_32(self) -> &'a mut crate::W<REG> {
597 self.variant(ADPS_A::PRESCALER_32)
598 }
599 ///Prescaler Value 64
600 #[inline(always)]
601 pub fn prescaler_64(self) -> &'a mut crate::W<REG> {
602 self.variant(ADPS_A::PRESCALER_64)
603 }
604 ///Prescaler Value 128
605 #[inline(always)]
606 pub fn prescaler_128(self) -> &'a mut crate::W<REG> {
607 self.variant(ADPS_A::PRESCALER_128)
608 }
609 }
610 ///Field `ADIE` reader - ADC Interrupt Enable
611 pub type ADIE_R = crate::BitReader;
612 ///Field `ADIE` writer - ADC Interrupt Enable
613 pub type ADIE_W<'a, REG> = crate::BitWriter<'a, REG>;
614 ///Field `ADIF` reader - ADC Interrupt Flag
615 pub type ADIF_R = crate::BitReader;
616 ///Field `ADIF` writer - ADC Interrupt Flag
617 pub type ADIF_W<'a, REG> = crate::BitWriter<'a, REG>;
618 ///Field `ADATE` reader - ADC Auto Trigger Enable
619 pub type ADATE_R = crate::BitReader;
620 ///Field `ADATE` writer - ADC Auto Trigger Enable
621 pub type ADATE_W<'a, REG> = crate::BitWriter<'a, REG>;
622 ///Field `ADSC` reader - ADC Start Conversion
623 pub type ADSC_R = crate::BitReader;
624 ///Field `ADSC` writer - ADC Start Conversion
625 pub type ADSC_W<'a, REG> = crate::BitWriter<'a, REG>;
626 ///Field `ADEN` reader - ADC Enable
627 pub type ADEN_R = crate::BitReader;
628 ///Field `ADEN` writer - ADC Enable
629 pub type ADEN_W<'a, REG> = crate::BitWriter<'a, REG>;
630 impl R {
631 ///Bits 0:2 - ADC Prescaler Select Bits
632 #[inline(always)]
633 pub fn adps(&self) -> ADPS_R {
634 ADPS_R::new(self.bits & 7)
635 }
636 ///Bit 3 - ADC Interrupt Enable
637 #[inline(always)]
638 pub fn adie(&self) -> ADIE_R {
639 ADIE_R::new(((self.bits >> 3) & 1) != 0)
640 }
641 ///Bit 4 - ADC Interrupt Flag
642 #[inline(always)]
643 pub fn adif(&self) -> ADIF_R {
644 ADIF_R::new(((self.bits >> 4) & 1) != 0)
645 }
646 ///Bit 5 - ADC Auto Trigger Enable
647 #[inline(always)]
648 pub fn adate(&self) -> ADATE_R {
649 ADATE_R::new(((self.bits >> 5) & 1) != 0)
650 }
651 ///Bit 6 - ADC Start Conversion
652 #[inline(always)]
653 pub fn adsc(&self) -> ADSC_R {
654 ADSC_R::new(((self.bits >> 6) & 1) != 0)
655 }
656 ///Bit 7 - ADC Enable
657 #[inline(always)]
658 pub fn aden(&self) -> ADEN_R {
659 ADEN_R::new(((self.bits >> 7) & 1) != 0)
660 }
661 }
662 impl W {
663 ///Bits 0:2 - ADC Prescaler Select Bits
664 #[inline(always)]
665 pub fn adps(&mut self) -> ADPS_W<'_, ADCSRA_SPEC> {
666 ADPS_W::new(self, 0)
667 }
668 ///Bit 3 - ADC Interrupt Enable
669 #[inline(always)]
670 pub fn adie(&mut self) -> ADIE_W<'_, ADCSRA_SPEC> {
671 ADIE_W::new(self, 3)
672 }
673 ///Bit 4 - ADC Interrupt Flag
674 #[inline(always)]
675 pub fn adif(&mut self) -> ADIF_W<'_, ADCSRA_SPEC> {
676 ADIF_W::new(self, 4)
677 }
678 ///Bit 5 - ADC Auto Trigger Enable
679 #[inline(always)]
680 pub fn adate(&mut self) -> ADATE_W<'_, ADCSRA_SPEC> {
681 ADATE_W::new(self, 5)
682 }
683 ///Bit 6 - ADC Start Conversion
684 #[inline(always)]
685 pub fn adsc(&mut self) -> ADSC_W<'_, ADCSRA_SPEC> {
686 ADSC_W::new(self, 6)
687 }
688 ///Bit 7 - ADC Enable
689 #[inline(always)]
690 pub fn aden(&mut self) -> ADEN_W<'_, ADCSRA_SPEC> {
691 ADEN_W::new(self, 7)
692 }
693 }
694 /**ADC Control and Status Register A
695
696You can [`read`](crate::Reg::read) this register and get [`adcsra::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adcsra::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
697 pub struct ADCSRA_SPEC;
698 impl crate::RegisterSpec for ADCSRA_SPEC {
699 type Ux = u8;
700 }
701 ///`read()` method returns [`adcsra::R`](R) reader structure
702 impl crate::Readable for ADCSRA_SPEC {}
703 ///`write(|w| ..)` method takes [`adcsra::W`](W) writer structure
704 impl crate::Writable for ADCSRA_SPEC {
705 type Safety = crate::Unsafe;
706 }
707 ///`reset()` method sets ADCSRA to value 0
708 impl crate::Resettable for ADCSRA_SPEC {}
709 }
710 /**ADCSRB (rw) register accessor: ADC Control and Status Register B
711
712You can [`read`](crate::Reg::read) this register and get [`adcsrb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adcsrb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
713
714For information about available fields see [`mod@adcsrb`] module*/
715 pub type ADCSRB = crate::Reg<adcsrb::ADCSRB_SPEC>;
716 ///ADC Control and Status Register B
717 pub mod adcsrb {
718 ///Register `ADCSRB` reader
719 pub type R = crate::R<ADCSRB_SPEC>;
720 ///Register `ADCSRB` writer
721 pub type W = crate::W<ADCSRB_SPEC>;
722 /**ADC Auto Trigger Sources
723
724Value on reset: 0*/
725 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
726 #[repr(u8)]
727 pub enum ADTS_A {
728 ///0: Free Running mode
729 FREE = 0,
730 ///1: Analog Comparator
731 AC = 1,
732 ///2: External Interrupt Request 0
733 INT0 = 2,
734 ///3: Timer/Counter0 Compare Match A
735 TC0_CMA = 3,
736 ///4: Timer/Counter0 Overflow
737 TC0_OVF = 4,
738 ///5: Timer/Counter0 Compare Match B
739 TC0_CMB = 5,
740 ///6: Pin Change Interrupt Request
741 PCIR = 6,
742 }
743 impl From<ADTS_A> for u8 {
744 #[inline(always)]
745 fn from(variant: ADTS_A) -> Self {
746 variant as _
747 }
748 }
749 impl crate::FieldSpec for ADTS_A {
750 type Ux = u8;
751 }
752 impl crate::IsEnum for ADTS_A {}
753 ///Field `ADTS` reader - ADC Auto Trigger Sources
754 pub type ADTS_R = crate::FieldReader<ADTS_A>;
755 impl ADTS_R {
756 ///Get enumerated values variant
757 #[inline(always)]
758 pub const fn variant(&self) -> Option<ADTS_A> {
759 match self.bits {
760 0 => Some(ADTS_A::FREE),
761 1 => Some(ADTS_A::AC),
762 2 => Some(ADTS_A::INT0),
763 3 => Some(ADTS_A::TC0_CMA),
764 4 => Some(ADTS_A::TC0_OVF),
765 5 => Some(ADTS_A::TC0_CMB),
766 6 => Some(ADTS_A::PCIR),
767 _ => None,
768 }
769 }
770 ///Free Running mode
771 #[inline(always)]
772 pub fn is_free(&self) -> bool {
773 *self == ADTS_A::FREE
774 }
775 ///Analog Comparator
776 #[inline(always)]
777 pub fn is_ac(&self) -> bool {
778 *self == ADTS_A::AC
779 }
780 ///External Interrupt Request 0
781 #[inline(always)]
782 pub fn is_int0(&self) -> bool {
783 *self == ADTS_A::INT0
784 }
785 ///Timer/Counter0 Compare Match A
786 #[inline(always)]
787 pub fn is_tc0_cma(&self) -> bool {
788 *self == ADTS_A::TC0_CMA
789 }
790 ///Timer/Counter0 Overflow
791 #[inline(always)]
792 pub fn is_tc0_ovf(&self) -> bool {
793 *self == ADTS_A::TC0_OVF
794 }
795 ///Timer/Counter0 Compare Match B
796 #[inline(always)]
797 pub fn is_tc0_cmb(&self) -> bool {
798 *self == ADTS_A::TC0_CMB
799 }
800 ///Pin Change Interrupt Request
801 #[inline(always)]
802 pub fn is_pcir(&self) -> bool {
803 *self == ADTS_A::PCIR
804 }
805 }
806 ///Field `ADTS` writer - ADC Auto Trigger Sources
807 pub type ADTS_W<'a, REG> = crate::FieldWriter<'a, REG, 3, ADTS_A>;
808 impl<'a, REG> ADTS_W<'a, REG>
809 where
810 REG: crate::Writable + crate::RegisterSpec,
811 REG::Ux: From<u8>,
812 {
813 ///Free Running mode
814 #[inline(always)]
815 pub fn free(self) -> &'a mut crate::W<REG> {
816 self.variant(ADTS_A::FREE)
817 }
818 ///Analog Comparator
819 #[inline(always)]
820 pub fn ac(self) -> &'a mut crate::W<REG> {
821 self.variant(ADTS_A::AC)
822 }
823 ///External Interrupt Request 0
824 #[inline(always)]
825 pub fn int0(self) -> &'a mut crate::W<REG> {
826 self.variant(ADTS_A::INT0)
827 }
828 ///Timer/Counter0 Compare Match A
829 #[inline(always)]
830 pub fn tc0_cma(self) -> &'a mut crate::W<REG> {
831 self.variant(ADTS_A::TC0_CMA)
832 }
833 ///Timer/Counter0 Overflow
834 #[inline(always)]
835 pub fn tc0_ovf(self) -> &'a mut crate::W<REG> {
836 self.variant(ADTS_A::TC0_OVF)
837 }
838 ///Timer/Counter0 Compare Match B
839 #[inline(always)]
840 pub fn tc0_cmb(self) -> &'a mut crate::W<REG> {
841 self.variant(ADTS_A::TC0_CMB)
842 }
843 ///Pin Change Interrupt Request
844 #[inline(always)]
845 pub fn pcir(self) -> &'a mut crate::W<REG> {
846 self.variant(ADTS_A::PCIR)
847 }
848 }
849 ///Field `IPR` reader - Input Polarity Mode
850 pub type IPR_R = crate::BitReader;
851 ///Field `IPR` writer - Input Polarity Mode
852 pub type IPR_W<'a, REG> = crate::BitWriter<'a, REG>;
853 ///Field `BIN` reader - Bipolar Input Mode
854 pub type BIN_R = crate::BitReader;
855 ///Field `BIN` writer - Bipolar Input Mode
856 pub type BIN_W<'a, REG> = crate::BitWriter<'a, REG>;
857 impl R {
858 ///Bits 0:2 - ADC Auto Trigger Sources
859 #[inline(always)]
860 pub fn adts(&self) -> ADTS_R {
861 ADTS_R::new(self.bits & 7)
862 }
863 ///Bit 5 - Input Polarity Mode
864 #[inline(always)]
865 pub fn ipr(&self) -> IPR_R {
866 IPR_R::new(((self.bits >> 5) & 1) != 0)
867 }
868 ///Bit 7 - Bipolar Input Mode
869 #[inline(always)]
870 pub fn bin(&self) -> BIN_R {
871 BIN_R::new(((self.bits >> 7) & 1) != 0)
872 }
873 }
874 impl W {
875 ///Bits 0:2 - ADC Auto Trigger Sources
876 #[inline(always)]
877 pub fn adts(&mut self) -> ADTS_W<'_, ADCSRB_SPEC> {
878 ADTS_W::new(self, 0)
879 }
880 ///Bit 5 - Input Polarity Mode
881 #[inline(always)]
882 pub fn ipr(&mut self) -> IPR_W<'_, ADCSRB_SPEC> {
883 IPR_W::new(self, 5)
884 }
885 ///Bit 7 - Bipolar Input Mode
886 #[inline(always)]
887 pub fn bin(&mut self) -> BIN_W<'_, ADCSRB_SPEC> {
888 BIN_W::new(self, 7)
889 }
890 }
891 /**ADC Control and Status Register B
892
893You can [`read`](crate::Reg::read) this register and get [`adcsrb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adcsrb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
894 pub struct ADCSRB_SPEC;
895 impl crate::RegisterSpec for ADCSRB_SPEC {
896 type Ux = u8;
897 }
898 ///`read()` method returns [`adcsrb::R`](R) reader structure
899 impl crate::Readable for ADCSRB_SPEC {}
900 ///`write(|w| ..)` method takes [`adcsrb::W`](W) writer structure
901 impl crate::Writable for ADCSRB_SPEC {
902 type Safety = crate::Unsafe;
903 }
904 ///`reset()` method sets ADCSRB to value 0
905 impl crate::Resettable for ADCSRB_SPEC {}
906 }
907 /**ADMUX (rw) register accessor: The ADC multiplexer Selection Register
908
909You can [`read`](crate::Reg::read) this register and get [`admux::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`admux::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
910
911For information about available fields see [`mod@admux`] module*/
912 pub type ADMUX = crate::Reg<admux::ADMUX_SPEC>;
913 ///The ADC multiplexer Selection Register
914 pub mod admux {
915 ///Register `ADMUX` reader
916 pub type R = crate::R<ADMUX_SPEC>;
917 ///Register `ADMUX` writer
918 pub type W = crate::W<ADMUX_SPEC>;
919 /**Analog Channel and Gain Selection Bits
920
921Value on reset: 0*/
922 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
923 #[repr(u8)]
924 pub enum MUX_A {
925 ///0: Single-ended Input ADC0
926 ADC0 = 0,
927 ///1: Single-ended Input ADC1
928 ADC1 = 1,
929 ///2: Single-ended Input ADC2
930 ADC2 = 2,
931 ///3: Single-ended Input ADC3
932 ADC3 = 3,
933 ///4: Differential Inputs Positive ADC2 Negative ADC2 1x Gain
934 ADC2_ADC2_1X = 4,
935 ///5: Differential Inputs Positive ADC2 Negative ADC2 20x Gain
936 ADC2_ADC2_20X = 5,
937 ///6: Differential Inputs Positive ADC2 Negative ADC3 1x Gain
938 ADC2_ADC3_1X = 6,
939 ///7: Differential Inputs Positive ADC2 Negative ADC3 20x Gain
940 ADC2_ADC3_20X = 7,
941 ///8: Differential Inputs Positive ADC0 Negative ADC0 1x Gain
942 ADC0_ADC0_1X = 8,
943 ///9: Differential Inputs Positive ADC0 Negative ADC0 20x Gain
944 ADC0_ADC0_20X = 9,
945 ///10: Differential Inputs Positive ADC0 Negative ADC1 1x Gain
946 ADC0_ADC1_1X = 10,
947 ///11: Differential Inputs Positive ADC0 Negative ADC1 20x Gain
948 ADC0_ADC1_20X = 11,
949 ///12: Internal Reference (VBG)
950 ADC_VBG = 12,
951 ///13: 0V (GND)
952 ADC_GND = 13,
953 ///15: Temperature sensor
954 TEMPSENS = 15,
955 }
956 impl From<MUX_A> for u8 {
957 #[inline(always)]
958 fn from(variant: MUX_A) -> Self {
959 variant as _
960 }
961 }
962 impl crate::FieldSpec for MUX_A {
963 type Ux = u8;
964 }
965 impl crate::IsEnum for MUX_A {}
966 ///Field `MUX` reader - Analog Channel and Gain Selection Bits
967 pub type MUX_R = crate::FieldReader<MUX_A>;
968 impl MUX_R {
969 ///Get enumerated values variant
970 #[inline(always)]
971 pub const fn variant(&self) -> Option<MUX_A> {
972 match self.bits {
973 0 => Some(MUX_A::ADC0),
974 1 => Some(MUX_A::ADC1),
975 2 => Some(MUX_A::ADC2),
976 3 => Some(MUX_A::ADC3),
977 4 => Some(MUX_A::ADC2_ADC2_1X),
978 5 => Some(MUX_A::ADC2_ADC2_20X),
979 6 => Some(MUX_A::ADC2_ADC3_1X),
980 7 => Some(MUX_A::ADC2_ADC3_20X),
981 8 => Some(MUX_A::ADC0_ADC0_1X),
982 9 => Some(MUX_A::ADC0_ADC0_20X),
983 10 => Some(MUX_A::ADC0_ADC1_1X),
984 11 => Some(MUX_A::ADC0_ADC1_20X),
985 12 => Some(MUX_A::ADC_VBG),
986 13 => Some(MUX_A::ADC_GND),
987 15 => Some(MUX_A::TEMPSENS),
988 _ => None,
989 }
990 }
991 ///Single-ended Input ADC0
992 #[inline(always)]
993 pub fn is_adc0(&self) -> bool {
994 *self == MUX_A::ADC0
995 }
996 ///Single-ended Input ADC1
997 #[inline(always)]
998 pub fn is_adc1(&self) -> bool {
999 *self == MUX_A::ADC1
1000 }
1001 ///Single-ended Input ADC2
1002 #[inline(always)]
1003 pub fn is_adc2(&self) -> bool {
1004 *self == MUX_A::ADC2
1005 }
1006 ///Single-ended Input ADC3
1007 #[inline(always)]
1008 pub fn is_adc3(&self) -> bool {
1009 *self == MUX_A::ADC3
1010 }
1011 ///Differential Inputs Positive ADC2 Negative ADC2 1x Gain
1012 #[inline(always)]
1013 pub fn is_adc2_adc2_1x(&self) -> bool {
1014 *self == MUX_A::ADC2_ADC2_1X
1015 }
1016 ///Differential Inputs Positive ADC2 Negative ADC2 20x Gain
1017 #[inline(always)]
1018 pub fn is_adc2_adc2_20x(&self) -> bool {
1019 *self == MUX_A::ADC2_ADC2_20X
1020 }
1021 ///Differential Inputs Positive ADC2 Negative ADC3 1x Gain
1022 #[inline(always)]
1023 pub fn is_adc2_adc3_1x(&self) -> bool {
1024 *self == MUX_A::ADC2_ADC3_1X
1025 }
1026 ///Differential Inputs Positive ADC2 Negative ADC3 20x Gain
1027 #[inline(always)]
1028 pub fn is_adc2_adc3_20x(&self) -> bool {
1029 *self == MUX_A::ADC2_ADC3_20X
1030 }
1031 ///Differential Inputs Positive ADC0 Negative ADC0 1x Gain
1032 #[inline(always)]
1033 pub fn is_adc0_adc0_1x(&self) -> bool {
1034 *self == MUX_A::ADC0_ADC0_1X
1035 }
1036 ///Differential Inputs Positive ADC0 Negative ADC0 20x Gain
1037 #[inline(always)]
1038 pub fn is_adc0_adc0_20x(&self) -> bool {
1039 *self == MUX_A::ADC0_ADC0_20X
1040 }
1041 ///Differential Inputs Positive ADC0 Negative ADC1 1x Gain
1042 #[inline(always)]
1043 pub fn is_adc0_adc1_1x(&self) -> bool {
1044 *self == MUX_A::ADC0_ADC1_1X
1045 }
1046 ///Differential Inputs Positive ADC0 Negative ADC1 20x Gain
1047 #[inline(always)]
1048 pub fn is_adc0_adc1_20x(&self) -> bool {
1049 *self == MUX_A::ADC0_ADC1_20X
1050 }
1051 ///Internal Reference (VBG)
1052 #[inline(always)]
1053 pub fn is_adc_vbg(&self) -> bool {
1054 *self == MUX_A::ADC_VBG
1055 }
1056 ///0V (GND)
1057 #[inline(always)]
1058 pub fn is_adc_gnd(&self) -> bool {
1059 *self == MUX_A::ADC_GND
1060 }
1061 ///Temperature sensor
1062 #[inline(always)]
1063 pub fn is_tempsens(&self) -> bool {
1064 *self == MUX_A::TEMPSENS
1065 }
1066 }
1067 ///Field `MUX` writer - Analog Channel and Gain Selection Bits
1068 pub type MUX_W<'a, REG> = crate::FieldWriter<'a, REG, 4, MUX_A>;
1069 impl<'a, REG> MUX_W<'a, REG>
1070 where
1071 REG: crate::Writable + crate::RegisterSpec,
1072 REG::Ux: From<u8>,
1073 {
1074 ///Single-ended Input ADC0
1075 #[inline(always)]
1076 pub fn adc0(self) -> &'a mut crate::W<REG> {
1077 self.variant(MUX_A::ADC0)
1078 }
1079 ///Single-ended Input ADC1
1080 #[inline(always)]
1081 pub fn adc1(self) -> &'a mut crate::W<REG> {
1082 self.variant(MUX_A::ADC1)
1083 }
1084 ///Single-ended Input ADC2
1085 #[inline(always)]
1086 pub fn adc2(self) -> &'a mut crate::W<REG> {
1087 self.variant(MUX_A::ADC2)
1088 }
1089 ///Single-ended Input ADC3
1090 #[inline(always)]
1091 pub fn adc3(self) -> &'a mut crate::W<REG> {
1092 self.variant(MUX_A::ADC3)
1093 }
1094 ///Differential Inputs Positive ADC2 Negative ADC2 1x Gain
1095 #[inline(always)]
1096 pub fn adc2_adc2_1x(self) -> &'a mut crate::W<REG> {
1097 self.variant(MUX_A::ADC2_ADC2_1X)
1098 }
1099 ///Differential Inputs Positive ADC2 Negative ADC2 20x Gain
1100 #[inline(always)]
1101 pub fn adc2_adc2_20x(self) -> &'a mut crate::W<REG> {
1102 self.variant(MUX_A::ADC2_ADC2_20X)
1103 }
1104 ///Differential Inputs Positive ADC2 Negative ADC3 1x Gain
1105 #[inline(always)]
1106 pub fn adc2_adc3_1x(self) -> &'a mut crate::W<REG> {
1107 self.variant(MUX_A::ADC2_ADC3_1X)
1108 }
1109 ///Differential Inputs Positive ADC2 Negative ADC3 20x Gain
1110 #[inline(always)]
1111 pub fn adc2_adc3_20x(self) -> &'a mut crate::W<REG> {
1112 self.variant(MUX_A::ADC2_ADC3_20X)
1113 }
1114 ///Differential Inputs Positive ADC0 Negative ADC0 1x Gain
1115 #[inline(always)]
1116 pub fn adc0_adc0_1x(self) -> &'a mut crate::W<REG> {
1117 self.variant(MUX_A::ADC0_ADC0_1X)
1118 }
1119 ///Differential Inputs Positive ADC0 Negative ADC0 20x Gain
1120 #[inline(always)]
1121 pub fn adc0_adc0_20x(self) -> &'a mut crate::W<REG> {
1122 self.variant(MUX_A::ADC0_ADC0_20X)
1123 }
1124 ///Differential Inputs Positive ADC0 Negative ADC1 1x Gain
1125 #[inline(always)]
1126 pub fn adc0_adc1_1x(self) -> &'a mut crate::W<REG> {
1127 self.variant(MUX_A::ADC0_ADC1_1X)
1128 }
1129 ///Differential Inputs Positive ADC0 Negative ADC1 20x Gain
1130 #[inline(always)]
1131 pub fn adc0_adc1_20x(self) -> &'a mut crate::W<REG> {
1132 self.variant(MUX_A::ADC0_ADC1_20X)
1133 }
1134 ///Internal Reference (VBG)
1135 #[inline(always)]
1136 pub fn adc_vbg(self) -> &'a mut crate::W<REG> {
1137 self.variant(MUX_A::ADC_VBG)
1138 }
1139 ///0V (GND)
1140 #[inline(always)]
1141 pub fn adc_gnd(self) -> &'a mut crate::W<REG> {
1142 self.variant(MUX_A::ADC_GND)
1143 }
1144 ///Temperature sensor
1145 #[inline(always)]
1146 pub fn tempsens(self) -> &'a mut crate::W<REG> {
1147 self.variant(MUX_A::TEMPSENS)
1148 }
1149 }
1150 ///Field `REFS2` reader - Reference Selection Bit 2
1151 pub type REFS2_R = crate::BitReader;
1152 ///Field `REFS2` writer - Reference Selection Bit 2
1153 pub type REFS2_W<'a, REG> = crate::BitWriter<'a, REG>;
1154 ///Field `ADLAR` reader - Left Adjust Result
1155 pub type ADLAR_R = crate::BitReader;
1156 ///Field `ADLAR` writer - Left Adjust Result
1157 pub type ADLAR_W<'a, REG> = crate::BitWriter<'a, REG>;
1158 /**Reference Selection Bits
1159
1160Value on reset: 0*/
1161 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
1162 #[repr(u8)]
1163 pub enum REFS_A {
1164 ///0: Vcc used as Voltage Reference, disconnected from Aref
1165 VCC = 0,
1166 ///1: External Voltage Reference at AREF pin, Internal Voltage Reference turned off
1167 AREF = 1,
1168 ///2: Internal Voltage Reference (1.1V when REFS2 is cleared, 2.56V when REFS2 is set) without external bypass
1169 INTERNAL = 2,
1170 ///3: Internal 2.56V Voltage Reference with external bypass capacitor at AREF pin (REFS2 must be set)
1171 INTERNAL_BYPASS = 3,
1172 }
1173 impl From<REFS_A> for u8 {
1174 #[inline(always)]
1175 fn from(variant: REFS_A) -> Self {
1176 variant as _
1177 }
1178 }
1179 impl crate::FieldSpec for REFS_A {
1180 type Ux = u8;
1181 }
1182 impl crate::IsEnum for REFS_A {}
1183 ///Field `REFS` reader - Reference Selection Bits
1184 pub type REFS_R = crate::FieldReader<REFS_A>;
1185 impl REFS_R {
1186 ///Get enumerated values variant
1187 #[inline(always)]
1188 pub const fn variant(&self) -> REFS_A {
1189 match self.bits {
1190 0 => REFS_A::VCC,
1191 1 => REFS_A::AREF,
1192 2 => REFS_A::INTERNAL,
1193 3 => REFS_A::INTERNAL_BYPASS,
1194 _ => unreachable!(),
1195 }
1196 }
1197 ///Vcc used as Voltage Reference, disconnected from Aref
1198 #[inline(always)]
1199 pub fn is_vcc(&self) -> bool {
1200 *self == REFS_A::VCC
1201 }
1202 ///External Voltage Reference at AREF pin, Internal Voltage Reference turned off
1203 #[inline(always)]
1204 pub fn is_aref(&self) -> bool {
1205 *self == REFS_A::AREF
1206 }
1207 ///Internal Voltage Reference (1.1V when REFS2 is cleared, 2.56V when REFS2 is set) without external bypass
1208 #[inline(always)]
1209 pub fn is_internal(&self) -> bool {
1210 *self == REFS_A::INTERNAL
1211 }
1212 ///Internal 2.56V Voltage Reference with external bypass capacitor at AREF pin (REFS2 must be set)
1213 #[inline(always)]
1214 pub fn is_internal_bypass(&self) -> bool {
1215 *self == REFS_A::INTERNAL_BYPASS
1216 }
1217 }
1218 ///Field `REFS` writer - Reference Selection Bits
1219 pub type REFS_W<'a, REG> = crate::FieldWriter<'a, REG, 2, REFS_A, crate::Safe>;
1220 impl<'a, REG> REFS_W<'a, REG>
1221 where
1222 REG: crate::Writable + crate::RegisterSpec,
1223 REG::Ux: From<u8>,
1224 {
1225 ///Vcc used as Voltage Reference, disconnected from Aref
1226 #[inline(always)]
1227 pub fn vcc(self) -> &'a mut crate::W<REG> {
1228 self.variant(REFS_A::VCC)
1229 }
1230 ///External Voltage Reference at AREF pin, Internal Voltage Reference turned off
1231 #[inline(always)]
1232 pub fn aref(self) -> &'a mut crate::W<REG> {
1233 self.variant(REFS_A::AREF)
1234 }
1235 ///Internal Voltage Reference (1.1V when REFS2 is cleared, 2.56V when REFS2 is set) without external bypass
1236 #[inline(always)]
1237 pub fn internal(self) -> &'a mut crate::W<REG> {
1238 self.variant(REFS_A::INTERNAL)
1239 }
1240 ///Internal 2.56V Voltage Reference with external bypass capacitor at AREF pin (REFS2 must be set)
1241 #[inline(always)]
1242 pub fn internal_bypass(self) -> &'a mut crate::W<REG> {
1243 self.variant(REFS_A::INTERNAL_BYPASS)
1244 }
1245 }
1246 impl R {
1247 ///Bits 0:3 - Analog Channel and Gain Selection Bits
1248 #[inline(always)]
1249 pub fn mux(&self) -> MUX_R {
1250 MUX_R::new(self.bits & 0x0f)
1251 }
1252 ///Bit 4 - Reference Selection Bit 2
1253 #[inline(always)]
1254 pub fn refs2(&self) -> REFS2_R {
1255 REFS2_R::new(((self.bits >> 4) & 1) != 0)
1256 }
1257 ///Bit 5 - Left Adjust Result
1258 #[inline(always)]
1259 pub fn adlar(&self) -> ADLAR_R {
1260 ADLAR_R::new(((self.bits >> 5) & 1) != 0)
1261 }
1262 ///Bits 6:7 - Reference Selection Bits
1263 #[inline(always)]
1264 pub fn refs(&self) -> REFS_R {
1265 REFS_R::new((self.bits >> 6) & 3)
1266 }
1267 }
1268 impl W {
1269 ///Bits 0:3 - Analog Channel and Gain Selection Bits
1270 #[inline(always)]
1271 pub fn mux(&mut self) -> MUX_W<'_, ADMUX_SPEC> {
1272 MUX_W::new(self, 0)
1273 }
1274 ///Bit 4 - Reference Selection Bit 2
1275 #[inline(always)]
1276 pub fn refs2(&mut self) -> REFS2_W<'_, ADMUX_SPEC> {
1277 REFS2_W::new(self, 4)
1278 }
1279 ///Bit 5 - Left Adjust Result
1280 #[inline(always)]
1281 pub fn adlar(&mut self) -> ADLAR_W<'_, ADMUX_SPEC> {
1282 ADLAR_W::new(self, 5)
1283 }
1284 ///Bits 6:7 - Reference Selection Bits
1285 #[inline(always)]
1286 pub fn refs(&mut self) -> REFS_W<'_, ADMUX_SPEC> {
1287 REFS_W::new(self, 6)
1288 }
1289 }
1290 /**The ADC multiplexer Selection Register
1291
1292You can [`read`](crate::Reg::read) this register and get [`admux::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`admux::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
1293 pub struct ADMUX_SPEC;
1294 impl crate::RegisterSpec for ADMUX_SPEC {
1295 type Ux = u8;
1296 }
1297 ///`read()` method returns [`admux::R`](R) reader structure
1298 impl crate::Readable for ADMUX_SPEC {}
1299 ///`write(|w| ..)` method takes [`admux::W`](W) writer structure
1300 impl crate::Writable for ADMUX_SPEC {
1301 type Safety = crate::Unsafe;
1302 }
1303 ///`reset()` method sets ADMUX to value 0
1304 impl crate::Resettable for ADMUX_SPEC {}
1305 }
1306 /**DIDR0 (rw) register accessor: Digital Input Disable Register 0
1307
1308You can [`read`](crate::Reg::read) this register and get [`didr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`didr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
1309
1310For information about available fields see [`mod@didr0`] module*/
1311 pub type DIDR0 = crate::Reg<didr0::DIDR0_SPEC>;
1312 ///Digital Input Disable Register 0
1313 pub mod didr0 {
1314 ///Register `DIDR0` reader
1315 pub type R = crate::R<DIDR0_SPEC>;
1316 ///Register `DIDR0` writer
1317 pub type W = crate::W<DIDR0_SPEC>;
1318 ///Field `ADC1D` reader - ADC1 Digital input Disable
1319 pub type ADC1D_R = crate::BitReader;
1320 ///Field `ADC1D` writer - ADC1 Digital input Disable
1321 pub type ADC1D_W<'a, REG> = crate::BitWriter<'a, REG>;
1322 ///Field `ADC3D` reader - ADC3 Digital input Disable
1323 pub type ADC3D_R = crate::BitReader;
1324 ///Field `ADC3D` writer - ADC3 Digital input Disable
1325 pub type ADC3D_W<'a, REG> = crate::BitWriter<'a, REG>;
1326 ///Field `ADC2D` reader - ADC2 Digital input Disable
1327 pub type ADC2D_R = crate::BitReader;
1328 ///Field `ADC2D` writer - ADC2 Digital input Disable
1329 pub type ADC2D_W<'a, REG> = crate::BitWriter<'a, REG>;
1330 ///Field `ADC0D` reader - ADC0 Digital input Disable
1331 pub type ADC0D_R = crate::BitReader;
1332 ///Field `ADC0D` writer - ADC0 Digital input Disable
1333 pub type ADC0D_W<'a, REG> = crate::BitWriter<'a, REG>;
1334 impl R {
1335 ///Bit 2 - ADC1 Digital input Disable
1336 #[inline(always)]
1337 pub fn adc1d(&self) -> ADC1D_R {
1338 ADC1D_R::new(((self.bits >> 2) & 1) != 0)
1339 }
1340 ///Bit 3 - ADC3 Digital input Disable
1341 #[inline(always)]
1342 pub fn adc3d(&self) -> ADC3D_R {
1343 ADC3D_R::new(((self.bits >> 3) & 1) != 0)
1344 }
1345 ///Bit 4 - ADC2 Digital input Disable
1346 #[inline(always)]
1347 pub fn adc2d(&self) -> ADC2D_R {
1348 ADC2D_R::new(((self.bits >> 4) & 1) != 0)
1349 }
1350 ///Bit 5 - ADC0 Digital input Disable
1351 #[inline(always)]
1352 pub fn adc0d(&self) -> ADC0D_R {
1353 ADC0D_R::new(((self.bits >> 5) & 1) != 0)
1354 }
1355 }
1356 impl W {
1357 ///Bit 2 - ADC1 Digital input Disable
1358 #[inline(always)]
1359 pub fn adc1d(&mut self) -> ADC1D_W<'_, DIDR0_SPEC> {
1360 ADC1D_W::new(self, 2)
1361 }
1362 ///Bit 3 - ADC3 Digital input Disable
1363 #[inline(always)]
1364 pub fn adc3d(&mut self) -> ADC3D_W<'_, DIDR0_SPEC> {
1365 ADC3D_W::new(self, 3)
1366 }
1367 ///Bit 4 - ADC2 Digital input Disable
1368 #[inline(always)]
1369 pub fn adc2d(&mut self) -> ADC2D_W<'_, DIDR0_SPEC> {
1370 ADC2D_W::new(self, 4)
1371 }
1372 ///Bit 5 - ADC0 Digital input Disable
1373 #[inline(always)]
1374 pub fn adc0d(&mut self) -> ADC0D_W<'_, DIDR0_SPEC> {
1375 ADC0D_W::new(self, 5)
1376 }
1377 }
1378 /**Digital Input Disable Register 0
1379
1380You can [`read`](crate::Reg::read) this register and get [`didr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`didr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
1381 pub struct DIDR0_SPEC;
1382 impl crate::RegisterSpec for DIDR0_SPEC {
1383 type Ux = u8;
1384 }
1385 ///`read()` method returns [`didr0::R`](R) reader structure
1386 impl crate::Readable for DIDR0_SPEC {}
1387 ///`write(|w| ..)` method takes [`didr0::W`](W) writer structure
1388 impl crate::Writable for DIDR0_SPEC {
1389 type Safety = crate::Unsafe;
1390 }
1391 ///`reset()` method sets DIDR0 to value 0
1392 impl crate::Resettable for DIDR0_SPEC {}
1393 }
1394}
1395///Bootloader
1396pub type BOOT_LOAD = crate::Periph<boot_load::RegisterBlock, 0x57>;
1397impl core::fmt::Debug for BOOT_LOAD {
1398 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1399 f.debug_struct("BOOT_LOAD").finish()
1400 }
1401}
1402///Bootloader
1403pub mod boot_load {
1404 #[repr(C)]
1405 ///Register block
1406 pub struct RegisterBlock {
1407 spmcsr: SPMCSR,
1408 }
1409 impl RegisterBlock {
1410 ///0x00 - Store Program Memory Control Register
1411 #[inline(always)]
1412 pub const fn spmcsr(&self) -> &SPMCSR {
1413 &self.spmcsr
1414 }
1415 }
1416 /**SPMCSR (rw) register accessor: Store Program Memory Control Register
1417
1418You can [`read`](crate::Reg::read) this register and get [`spmcsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spmcsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
1419
1420For information about available fields see [`mod@spmcsr`] module*/
1421 pub type SPMCSR = crate::Reg<spmcsr::SPMCSR_SPEC>;
1422 ///Store Program Memory Control Register
1423 pub mod spmcsr {
1424 ///Register `SPMCSR` reader
1425 pub type R = crate::R<SPMCSR_SPEC>;
1426 ///Register `SPMCSR` writer
1427 pub type W = crate::W<SPMCSR_SPEC>;
1428 ///Field `SPMEN` reader - Store Program Memory Enable
1429 pub type SPMEN_R = crate::BitReader;
1430 ///Field `SPMEN` writer - Store Program Memory Enable
1431 pub type SPMEN_W<'a, REG> = crate::BitWriter<'a, REG>;
1432 ///Field `PGERS` reader - Page Erase
1433 pub type PGERS_R = crate::BitReader;
1434 ///Field `PGERS` writer - Page Erase
1435 pub type PGERS_W<'a, REG> = crate::BitWriter<'a, REG>;
1436 ///Field `PGWRT` reader - Page Write
1437 pub type PGWRT_R = crate::BitReader;
1438 ///Field `PGWRT` writer - Page Write
1439 pub type PGWRT_W<'a, REG> = crate::BitWriter<'a, REG>;
1440 ///Field `RFLB` reader - Read fuse and lock bits
1441 pub type RFLB_R = crate::BitReader;
1442 ///Field `RFLB` writer - Read fuse and lock bits
1443 pub type RFLB_W<'a, REG> = crate::BitWriter<'a, REG>;
1444 ///Field `CTPB` reader - Clear temporary page buffer
1445 pub type CTPB_R = crate::BitReader;
1446 ///Field `CTPB` writer - Clear temporary page buffer
1447 pub type CTPB_W<'a, REG> = crate::BitWriter<'a, REG>;
1448 ///Field `RSIG` reader - Read Device Signature Imprint Table
1449 pub type RSIG_R = crate::BitReader;
1450 ///Field `RSIG` writer - Read Device Signature Imprint Table
1451 pub type RSIG_W<'a, REG> = crate::BitWriter<'a, REG>;
1452 impl R {
1453 ///Bit 0 - Store Program Memory Enable
1454 #[inline(always)]
1455 pub fn spmen(&self) -> SPMEN_R {
1456 SPMEN_R::new((self.bits & 1) != 0)
1457 }
1458 ///Bit 1 - Page Erase
1459 #[inline(always)]
1460 pub fn pgers(&self) -> PGERS_R {
1461 PGERS_R::new(((self.bits >> 1) & 1) != 0)
1462 }
1463 ///Bit 2 - Page Write
1464 #[inline(always)]
1465 pub fn pgwrt(&self) -> PGWRT_R {
1466 PGWRT_R::new(((self.bits >> 2) & 1) != 0)
1467 }
1468 ///Bit 3 - Read fuse and lock bits
1469 #[inline(always)]
1470 pub fn rflb(&self) -> RFLB_R {
1471 RFLB_R::new(((self.bits >> 3) & 1) != 0)
1472 }
1473 ///Bit 4 - Clear temporary page buffer
1474 #[inline(always)]
1475 pub fn ctpb(&self) -> CTPB_R {
1476 CTPB_R::new(((self.bits >> 4) & 1) != 0)
1477 }
1478 ///Bit 5 - Read Device Signature Imprint Table
1479 #[inline(always)]
1480 pub fn rsig(&self) -> RSIG_R {
1481 RSIG_R::new(((self.bits >> 5) & 1) != 0)
1482 }
1483 }
1484 impl W {
1485 ///Bit 0 - Store Program Memory Enable
1486 #[inline(always)]
1487 pub fn spmen(&mut self) -> SPMEN_W<'_, SPMCSR_SPEC> {
1488 SPMEN_W::new(self, 0)
1489 }
1490 ///Bit 1 - Page Erase
1491 #[inline(always)]
1492 pub fn pgers(&mut self) -> PGERS_W<'_, SPMCSR_SPEC> {
1493 PGERS_W::new(self, 1)
1494 }
1495 ///Bit 2 - Page Write
1496 #[inline(always)]
1497 pub fn pgwrt(&mut self) -> PGWRT_W<'_, SPMCSR_SPEC> {
1498 PGWRT_W::new(self, 2)
1499 }
1500 ///Bit 3 - Read fuse and lock bits
1501 #[inline(always)]
1502 pub fn rflb(&mut self) -> RFLB_W<'_, SPMCSR_SPEC> {
1503 RFLB_W::new(self, 3)
1504 }
1505 ///Bit 4 - Clear temporary page buffer
1506 #[inline(always)]
1507 pub fn ctpb(&mut self) -> CTPB_W<'_, SPMCSR_SPEC> {
1508 CTPB_W::new(self, 4)
1509 }
1510 ///Bit 5 - Read Device Signature Imprint Table
1511 #[inline(always)]
1512 pub fn rsig(&mut self) -> RSIG_W<'_, SPMCSR_SPEC> {
1513 RSIG_W::new(self, 5)
1514 }
1515 }
1516 /**Store Program Memory Control Register
1517
1518You can [`read`](crate::Reg::read) this register and get [`spmcsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spmcsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
1519 pub struct SPMCSR_SPEC;
1520 impl crate::RegisterSpec for SPMCSR_SPEC {
1521 type Ux = u8;
1522 }
1523 ///`read()` method returns [`spmcsr::R`](R) reader structure
1524 impl crate::Readable for SPMCSR_SPEC {}
1525 ///`write(|w| ..)` method takes [`spmcsr::W`](W) writer structure
1526 impl crate::Writable for SPMCSR_SPEC {
1527 type Safety = crate::Unsafe;
1528 }
1529 ///`reset()` method sets SPMCSR to value 0
1530 impl crate::Resettable for SPMCSR_SPEC {}
1531 }
1532}
1533///CPU Registers
1534pub type CPU = crate::Periph<cpu::RegisterBlock, 0x31>;
1535impl core::fmt::Debug for CPU {
1536 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1537 f.debug_struct("CPU").finish()
1538 }
1539}
1540///CPU Registers
1541pub mod cpu {
1542 #[repr(C)]
1543 ///Register block
1544 pub struct RegisterBlock {
1545 gpior0: GPIOR0,
1546 gpior1: GPIOR1,
1547 gpior2: GPIOR2,
1548 _reserved3: [u8; 0x0c],
1549 prr: PRR,
1550 _reserved4: [u8; 0x01],
1551 dwdr: DWDR,
1552 _reserved5: [u8; 0x03],
1553 clkpr: CLKPR,
1554 pllcsr: PLLCSR,
1555 _reserved7: [u8; 0x09],
1556 osccal: OSCCAL,
1557 _reserved8: [u8; 0x02],
1558 mcusr: MCUSR,
1559 mcucr: MCUCR,
1560 }
1561 impl RegisterBlock {
1562 ///0x00 - General purpose register 0
1563 #[inline(always)]
1564 pub const fn gpior0(&self) -> &GPIOR0 {
1565 &self.gpior0
1566 }
1567 ///0x01 - General Purpose register 1
1568 #[inline(always)]
1569 pub const fn gpior1(&self) -> &GPIOR1 {
1570 &self.gpior1
1571 }
1572 ///0x02 - General Purpose IO register 2
1573 #[inline(always)]
1574 pub const fn gpior2(&self) -> &GPIOR2 {
1575 &self.gpior2
1576 }
1577 ///0x0f - Power Reduction Register
1578 #[inline(always)]
1579 pub const fn prr(&self) -> &PRR {
1580 &self.prr
1581 }
1582 ///0x11 - debugWire data register
1583 #[inline(always)]
1584 pub const fn dwdr(&self) -> &DWDR {
1585 &self.dwdr
1586 }
1587 ///0x15 - Clock Prescale Register
1588 #[inline(always)]
1589 pub const fn clkpr(&self) -> &CLKPR {
1590 &self.clkpr
1591 }
1592 ///0x16 - PLL Control and status register
1593 #[inline(always)]
1594 pub const fn pllcsr(&self) -> &PLLCSR {
1595 &self.pllcsr
1596 }
1597 ///0x20 - Oscillator Calibration Register
1598 #[inline(always)]
1599 pub const fn osccal(&self) -> &OSCCAL {
1600 &self.osccal
1601 }
1602 ///0x23 - MCU Status register
1603 #[inline(always)]
1604 pub const fn mcusr(&self) -> &MCUSR {
1605 &self.mcusr
1606 }
1607 ///0x24 - MCU Control Register
1608 #[inline(always)]
1609 pub const fn mcucr(&self) -> &MCUCR {
1610 &self.mcucr
1611 }
1612 }
1613 /**CLKPR (rw) register accessor: Clock Prescale Register
1614
1615You can [`read`](crate::Reg::read) this register and get [`clkpr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkpr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
1616
1617For information about available fields see [`mod@clkpr`] module*/
1618 pub type CLKPR = crate::Reg<clkpr::CLKPR_SPEC>;
1619 ///Clock Prescale Register
1620 pub mod clkpr {
1621 ///Register `CLKPR` reader
1622 pub type R = crate::R<CLKPR_SPEC>;
1623 ///Register `CLKPR` writer
1624 pub type W = crate::W<CLKPR_SPEC>;
1625 /**Clock Prescaler Select Bits
1626
1627Value on reset: 0*/
1628 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
1629 #[repr(u8)]
1630 pub enum CLKPS_A {
1631 ///0: Prescaler Value 1
1632 PRESCALER_1 = 0,
1633 ///1: Prescaler Value 2
1634 PRESCALER_2 = 1,
1635 ///2: Prescaler Value 4
1636 PRESCALER_4 = 2,
1637 ///3: Prescaler Value 8
1638 PRESCALER_8 = 3,
1639 ///4: Prescaler Value 16
1640 PRESCALER_16 = 4,
1641 ///5: Prescaler Value 32
1642 PRESCALER_32 = 5,
1643 ///6: Prescaler Value 64
1644 PRESCALER_64 = 6,
1645 ///7: Prescaler Value 128
1646 PRESCALER_128 = 7,
1647 ///8: Prescaler Value 256
1648 PRESCALER_256 = 8,
1649 }
1650 impl From<CLKPS_A> for u8 {
1651 #[inline(always)]
1652 fn from(variant: CLKPS_A) -> Self {
1653 variant as _
1654 }
1655 }
1656 impl crate::FieldSpec for CLKPS_A {
1657 type Ux = u8;
1658 }
1659 impl crate::IsEnum for CLKPS_A {}
1660 ///Field `CLKPS` reader - Clock Prescaler Select Bits
1661 pub type CLKPS_R = crate::FieldReader<CLKPS_A>;
1662 impl CLKPS_R {
1663 ///Get enumerated values variant
1664 #[inline(always)]
1665 pub const fn variant(&self) -> Option<CLKPS_A> {
1666 match self.bits {
1667 0 => Some(CLKPS_A::PRESCALER_1),
1668 1 => Some(CLKPS_A::PRESCALER_2),
1669 2 => Some(CLKPS_A::PRESCALER_4),
1670 3 => Some(CLKPS_A::PRESCALER_8),
1671 4 => Some(CLKPS_A::PRESCALER_16),
1672 5 => Some(CLKPS_A::PRESCALER_32),
1673 6 => Some(CLKPS_A::PRESCALER_64),
1674 7 => Some(CLKPS_A::PRESCALER_128),
1675 8 => Some(CLKPS_A::PRESCALER_256),
1676 _ => None,
1677 }
1678 }
1679 ///Prescaler Value 1
1680 #[inline(always)]
1681 pub fn is_prescaler_1(&self) -> bool {
1682 *self == CLKPS_A::PRESCALER_1
1683 }
1684 ///Prescaler Value 2
1685 #[inline(always)]
1686 pub fn is_prescaler_2(&self) -> bool {
1687 *self == CLKPS_A::PRESCALER_2
1688 }
1689 ///Prescaler Value 4
1690 #[inline(always)]
1691 pub fn is_prescaler_4(&self) -> bool {
1692 *self == CLKPS_A::PRESCALER_4
1693 }
1694 ///Prescaler Value 8
1695 #[inline(always)]
1696 pub fn is_prescaler_8(&self) -> bool {
1697 *self == CLKPS_A::PRESCALER_8
1698 }
1699 ///Prescaler Value 16
1700 #[inline(always)]
1701 pub fn is_prescaler_16(&self) -> bool {
1702 *self == CLKPS_A::PRESCALER_16
1703 }
1704 ///Prescaler Value 32
1705 #[inline(always)]
1706 pub fn is_prescaler_32(&self) -> bool {
1707 *self == CLKPS_A::PRESCALER_32
1708 }
1709 ///Prescaler Value 64
1710 #[inline(always)]
1711 pub fn is_prescaler_64(&self) -> bool {
1712 *self == CLKPS_A::PRESCALER_64
1713 }
1714 ///Prescaler Value 128
1715 #[inline(always)]
1716 pub fn is_prescaler_128(&self) -> bool {
1717 *self == CLKPS_A::PRESCALER_128
1718 }
1719 ///Prescaler Value 256
1720 #[inline(always)]
1721 pub fn is_prescaler_256(&self) -> bool {
1722 *self == CLKPS_A::PRESCALER_256
1723 }
1724 }
1725 ///Field `CLKPS` writer - Clock Prescaler Select Bits
1726 pub type CLKPS_W<'a, REG> = crate::FieldWriter<'a, REG, 4, CLKPS_A>;
1727 impl<'a, REG> CLKPS_W<'a, REG>
1728 where
1729 REG: crate::Writable + crate::RegisterSpec,
1730 REG::Ux: From<u8>,
1731 {
1732 ///Prescaler Value 1
1733 #[inline(always)]
1734 pub fn prescaler_1(self) -> &'a mut crate::W<REG> {
1735 self.variant(CLKPS_A::PRESCALER_1)
1736 }
1737 ///Prescaler Value 2
1738 #[inline(always)]
1739 pub fn prescaler_2(self) -> &'a mut crate::W<REG> {
1740 self.variant(CLKPS_A::PRESCALER_2)
1741 }
1742 ///Prescaler Value 4
1743 #[inline(always)]
1744 pub fn prescaler_4(self) -> &'a mut crate::W<REG> {
1745 self.variant(CLKPS_A::PRESCALER_4)
1746 }
1747 ///Prescaler Value 8
1748 #[inline(always)]
1749 pub fn prescaler_8(self) -> &'a mut crate::W<REG> {
1750 self.variant(CLKPS_A::PRESCALER_8)
1751 }
1752 ///Prescaler Value 16
1753 #[inline(always)]
1754 pub fn prescaler_16(self) -> &'a mut crate::W<REG> {
1755 self.variant(CLKPS_A::PRESCALER_16)
1756 }
1757 ///Prescaler Value 32
1758 #[inline(always)]
1759 pub fn prescaler_32(self) -> &'a mut crate::W<REG> {
1760 self.variant(CLKPS_A::PRESCALER_32)
1761 }
1762 ///Prescaler Value 64
1763 #[inline(always)]
1764 pub fn prescaler_64(self) -> &'a mut crate::W<REG> {
1765 self.variant(CLKPS_A::PRESCALER_64)
1766 }
1767 ///Prescaler Value 128
1768 #[inline(always)]
1769 pub fn prescaler_128(self) -> &'a mut crate::W<REG> {
1770 self.variant(CLKPS_A::PRESCALER_128)
1771 }
1772 ///Prescaler Value 256
1773 #[inline(always)]
1774 pub fn prescaler_256(self) -> &'a mut crate::W<REG> {
1775 self.variant(CLKPS_A::PRESCALER_256)
1776 }
1777 }
1778 ///Field `CLKPCE` reader - Clock Prescaler Change Enable
1779 pub type CLKPCE_R = crate::BitReader;
1780 ///Field `CLKPCE` writer - Clock Prescaler Change Enable
1781 pub type CLKPCE_W<'a, REG> = crate::BitWriter<'a, REG>;
1782 impl R {
1783 ///Bits 0:3 - Clock Prescaler Select Bits
1784 #[inline(always)]
1785 pub fn clkps(&self) -> CLKPS_R {
1786 CLKPS_R::new(self.bits & 0x0f)
1787 }
1788 ///Bit 7 - Clock Prescaler Change Enable
1789 #[inline(always)]
1790 pub fn clkpce(&self) -> CLKPCE_R {
1791 CLKPCE_R::new(((self.bits >> 7) & 1) != 0)
1792 }
1793 }
1794 impl W {
1795 ///Bits 0:3 - Clock Prescaler Select Bits
1796 #[inline(always)]
1797 pub fn clkps(&mut self) -> CLKPS_W<'_, CLKPR_SPEC> {
1798 CLKPS_W::new(self, 0)
1799 }
1800 ///Bit 7 - Clock Prescaler Change Enable
1801 #[inline(always)]
1802 pub fn clkpce(&mut self) -> CLKPCE_W<'_, CLKPR_SPEC> {
1803 CLKPCE_W::new(self, 7)
1804 }
1805 }
1806 /**Clock Prescale Register
1807
1808You can [`read`](crate::Reg::read) this register and get [`clkpr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkpr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
1809 pub struct CLKPR_SPEC;
1810 impl crate::RegisterSpec for CLKPR_SPEC {
1811 type Ux = u8;
1812 }
1813 ///`read()` method returns [`clkpr::R`](R) reader structure
1814 impl crate::Readable for CLKPR_SPEC {}
1815 ///`write(|w| ..)` method takes [`clkpr::W`](W) writer structure
1816 impl crate::Writable for CLKPR_SPEC {
1817 type Safety = crate::Unsafe;
1818 }
1819 ///`reset()` method sets CLKPR to value 0
1820 impl crate::Resettable for CLKPR_SPEC {}
1821 }
1822 /**DWDR (rw) register accessor: debugWire data register
1823
1824You can [`read`](crate::Reg::read) this register and get [`dwdr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dwdr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
1825
1826For information about available fields see [`mod@dwdr`] module*/
1827 pub type DWDR = crate::Reg<dwdr::DWDR_SPEC>;
1828 ///debugWire data register
1829 pub mod dwdr {
1830 ///Register `DWDR` reader
1831 pub type R = crate::R<DWDR_SPEC>;
1832 ///Register `DWDR` writer
1833 pub type W = crate::W<DWDR_SPEC>;
1834 impl core::fmt::Debug for R {
1835 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1836 write!(f, "{}", self.bits())
1837 }
1838 }
1839 impl W {}
1840 /**debugWire data register
1841
1842You can [`read`](crate::Reg::read) this register and get [`dwdr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dwdr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
1843 pub struct DWDR_SPEC;
1844 impl crate::RegisterSpec for DWDR_SPEC {
1845 type Ux = u8;
1846 }
1847 ///`read()` method returns [`dwdr::R`](R) reader structure
1848 impl crate::Readable for DWDR_SPEC {}
1849 ///`write(|w| ..)` method takes [`dwdr::W`](W) writer structure
1850 impl crate::Writable for DWDR_SPEC {
1851 type Safety = crate::Safe;
1852 }
1853 ///`reset()` method sets DWDR to value 0
1854 impl crate::Resettable for DWDR_SPEC {}
1855 }
1856 /**GPIOR0 (rw) register accessor: General purpose register 0
1857
1858You can [`read`](crate::Reg::read) this register and get [`gpior0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpior0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
1859
1860For information about available fields see [`mod@gpior0`] module*/
1861 pub type GPIOR0 = crate::Reg<gpior0::GPIOR0_SPEC>;
1862 ///General purpose register 0
1863 pub mod gpior0 {
1864 ///Register `GPIOR0` reader
1865 pub type R = crate::R<GPIOR0_SPEC>;
1866 ///Register `GPIOR0` writer
1867 pub type W = crate::W<GPIOR0_SPEC>;
1868 impl core::fmt::Debug for R {
1869 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1870 write!(f, "{}", self.bits())
1871 }
1872 }
1873 impl W {}
1874 /**General purpose register 0
1875
1876You can [`read`](crate::Reg::read) this register and get [`gpior0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpior0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
1877 pub struct GPIOR0_SPEC;
1878 impl crate::RegisterSpec for GPIOR0_SPEC {
1879 type Ux = u8;
1880 }
1881 ///`read()` method returns [`gpior0::R`](R) reader structure
1882 impl crate::Readable for GPIOR0_SPEC {}
1883 ///`write(|w| ..)` method takes [`gpior0::W`](W) writer structure
1884 impl crate::Writable for GPIOR0_SPEC {
1885 type Safety = crate::Safe;
1886 }
1887 ///`reset()` method sets GPIOR0 to value 0
1888 impl crate::Resettable for GPIOR0_SPEC {}
1889 }
1890 /**GPIOR1 (rw) register accessor: General Purpose register 1
1891
1892You can [`read`](crate::Reg::read) this register and get [`gpior1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpior1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
1893
1894For information about available fields see [`mod@gpior1`] module*/
1895 pub type GPIOR1 = crate::Reg<gpior1::GPIOR1_SPEC>;
1896 ///General Purpose register 1
1897 pub mod gpior1 {
1898 ///Register `GPIOR1` reader
1899 pub type R = crate::R<GPIOR1_SPEC>;
1900 ///Register `GPIOR1` writer
1901 pub type W = crate::W<GPIOR1_SPEC>;
1902 impl core::fmt::Debug for R {
1903 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1904 write!(f, "{}", self.bits())
1905 }
1906 }
1907 impl W {}
1908 /**General Purpose register 1
1909
1910You can [`read`](crate::Reg::read) this register and get [`gpior1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpior1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
1911 pub struct GPIOR1_SPEC;
1912 impl crate::RegisterSpec for GPIOR1_SPEC {
1913 type Ux = u8;
1914 }
1915 ///`read()` method returns [`gpior1::R`](R) reader structure
1916 impl crate::Readable for GPIOR1_SPEC {}
1917 ///`write(|w| ..)` method takes [`gpior1::W`](W) writer structure
1918 impl crate::Writable for GPIOR1_SPEC {
1919 type Safety = crate::Safe;
1920 }
1921 ///`reset()` method sets GPIOR1 to value 0
1922 impl crate::Resettable for GPIOR1_SPEC {}
1923 }
1924 /**GPIOR2 (rw) register accessor: General Purpose IO register 2
1925
1926You can [`read`](crate::Reg::read) this register and get [`gpior2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpior2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
1927
1928For information about available fields see [`mod@gpior2`] module*/
1929 pub type GPIOR2 = crate::Reg<gpior2::GPIOR2_SPEC>;
1930 ///General Purpose IO register 2
1931 pub mod gpior2 {
1932 ///Register `GPIOR2` reader
1933 pub type R = crate::R<GPIOR2_SPEC>;
1934 ///Register `GPIOR2` writer
1935 pub type W = crate::W<GPIOR2_SPEC>;
1936 impl core::fmt::Debug for R {
1937 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1938 write!(f, "{}", self.bits())
1939 }
1940 }
1941 impl W {}
1942 /**General Purpose IO register 2
1943
1944You can [`read`](crate::Reg::read) this register and get [`gpior2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpior2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
1945 pub struct GPIOR2_SPEC;
1946 impl crate::RegisterSpec for GPIOR2_SPEC {
1947 type Ux = u8;
1948 }
1949 ///`read()` method returns [`gpior2::R`](R) reader structure
1950 impl crate::Readable for GPIOR2_SPEC {}
1951 ///`write(|w| ..)` method takes [`gpior2::W`](W) writer structure
1952 impl crate::Writable for GPIOR2_SPEC {
1953 type Safety = crate::Safe;
1954 }
1955 ///`reset()` method sets GPIOR2 to value 0
1956 impl crate::Resettable for GPIOR2_SPEC {}
1957 }
1958 /**MCUCR (rw) register accessor: MCU Control Register
1959
1960You can [`read`](crate::Reg::read) this register and get [`mcucr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mcucr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
1961
1962For information about available fields see [`mod@mcucr`] module*/
1963 pub type MCUCR = crate::Reg<mcucr::MCUCR_SPEC>;
1964 ///MCU Control Register
1965 pub mod mcucr {
1966 ///Register `MCUCR` reader
1967 pub type R = crate::R<MCUCR_SPEC>;
1968 ///Register `MCUCR` writer
1969 pub type W = crate::W<MCUCR_SPEC>;
1970 ///Field `BODSE` reader - BOD Sleep Enable (available on some devices)
1971 pub type BODSE_R = crate::BitReader;
1972 ///Field `BODSE` writer - BOD Sleep Enable (available on some devices)
1973 pub type BODSE_W<'a, REG> = crate::BitWriter<'a, REG>;
1974 /**Sleep Mode Select Bits
1975
1976Value on reset: 0*/
1977 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
1978 #[repr(u8)]
1979 pub enum SM_A {
1980 ///0: Idle
1981 IDLE = 0,
1982 ///1: ADC Noise Reduction (If Available)
1983 ADC = 1,
1984 ///2: Power Down
1985 PDOWN = 2,
1986 ///3: Reserved
1987 VAL_0X03 = 3,
1988 }
1989 impl From<SM_A> for u8 {
1990 #[inline(always)]
1991 fn from(variant: SM_A) -> Self {
1992 variant as _
1993 }
1994 }
1995 impl crate::FieldSpec for SM_A {
1996 type Ux = u8;
1997 }
1998 impl crate::IsEnum for SM_A {}
1999 ///Field `SM` reader - Sleep Mode Select Bits
2000 pub type SM_R = crate::FieldReader<SM_A>;
2001 impl SM_R {
2002 ///Get enumerated values variant
2003 #[inline(always)]
2004 pub const fn variant(&self) -> SM_A {
2005 match self.bits {
2006 0 => SM_A::IDLE,
2007 1 => SM_A::ADC,
2008 2 => SM_A::PDOWN,
2009 3 => SM_A::VAL_0X03,
2010 _ => unreachable!(),
2011 }
2012 }
2013 ///Idle
2014 #[inline(always)]
2015 pub fn is_idle(&self) -> bool {
2016 *self == SM_A::IDLE
2017 }
2018 ///ADC Noise Reduction (If Available)
2019 #[inline(always)]
2020 pub fn is_adc(&self) -> bool {
2021 *self == SM_A::ADC
2022 }
2023 ///Power Down
2024 #[inline(always)]
2025 pub fn is_pdown(&self) -> bool {
2026 *self == SM_A::PDOWN
2027 }
2028 ///Reserved
2029 #[inline(always)]
2030 pub fn is_val_0x03(&self) -> bool {
2031 *self == SM_A::VAL_0X03
2032 }
2033 }
2034 ///Field `SM` writer - Sleep Mode Select Bits
2035 pub type SM_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SM_A, crate::Safe>;
2036 impl<'a, REG> SM_W<'a, REG>
2037 where
2038 REG: crate::Writable + crate::RegisterSpec,
2039 REG::Ux: From<u8>,
2040 {
2041 ///Idle
2042 #[inline(always)]
2043 pub fn idle(self) -> &'a mut crate::W<REG> {
2044 self.variant(SM_A::IDLE)
2045 }
2046 ///ADC Noise Reduction (If Available)
2047 #[inline(always)]
2048 pub fn adc(self) -> &'a mut crate::W<REG> {
2049 self.variant(SM_A::ADC)
2050 }
2051 ///Power Down
2052 #[inline(always)]
2053 pub fn pdown(self) -> &'a mut crate::W<REG> {
2054 self.variant(SM_A::PDOWN)
2055 }
2056 ///Reserved
2057 #[inline(always)]
2058 pub fn val_0x03(self) -> &'a mut crate::W<REG> {
2059 self.variant(SM_A::VAL_0X03)
2060 }
2061 }
2062 ///Field `SE` reader - Sleep Enable
2063 pub type SE_R = crate::BitReader;
2064 ///Field `SE` writer - Sleep Enable
2065 pub type SE_W<'a, REG> = crate::BitWriter<'a, REG>;
2066 ///Field `PUD` reader - Pull-up Disable
2067 pub type PUD_R = crate::BitReader;
2068 ///Field `PUD` writer - Pull-up Disable
2069 pub type PUD_W<'a, REG> = crate::BitWriter<'a, REG>;
2070 ///Field `BODS` reader - BOD Sleep (available on some devices)
2071 pub type BODS_R = crate::BitReader;
2072 ///Field `BODS` writer - BOD Sleep (available on some devices)
2073 pub type BODS_W<'a, REG> = crate::BitWriter<'a, REG>;
2074 impl R {
2075 ///Bit 2 - BOD Sleep Enable (available on some devices)
2076 #[inline(always)]
2077 pub fn bodse(&self) -> BODSE_R {
2078 BODSE_R::new(((self.bits >> 2) & 1) != 0)
2079 }
2080 ///Bits 3:4 - Sleep Mode Select Bits
2081 #[inline(always)]
2082 pub fn sm(&self) -> SM_R {
2083 SM_R::new((self.bits >> 3) & 3)
2084 }
2085 ///Bit 5 - Sleep Enable
2086 #[inline(always)]
2087 pub fn se(&self) -> SE_R {
2088 SE_R::new(((self.bits >> 5) & 1) != 0)
2089 }
2090 ///Bit 6 - Pull-up Disable
2091 #[inline(always)]
2092 pub fn pud(&self) -> PUD_R {
2093 PUD_R::new(((self.bits >> 6) & 1) != 0)
2094 }
2095 ///Bit 7 - BOD Sleep (available on some devices)
2096 #[inline(always)]
2097 pub fn bods(&self) -> BODS_R {
2098 BODS_R::new(((self.bits >> 7) & 1) != 0)
2099 }
2100 }
2101 impl W {
2102 ///Bit 2 - BOD Sleep Enable (available on some devices)
2103 #[inline(always)]
2104 pub fn bodse(&mut self) -> BODSE_W<'_, MCUCR_SPEC> {
2105 BODSE_W::new(self, 2)
2106 }
2107 ///Bits 3:4 - Sleep Mode Select Bits
2108 #[inline(always)]
2109 pub fn sm(&mut self) -> SM_W<'_, MCUCR_SPEC> {
2110 SM_W::new(self, 3)
2111 }
2112 ///Bit 5 - Sleep Enable
2113 #[inline(always)]
2114 pub fn se(&mut self) -> SE_W<'_, MCUCR_SPEC> {
2115 SE_W::new(self, 5)
2116 }
2117 ///Bit 6 - Pull-up Disable
2118 #[inline(always)]
2119 pub fn pud(&mut self) -> PUD_W<'_, MCUCR_SPEC> {
2120 PUD_W::new(self, 6)
2121 }
2122 ///Bit 7 - BOD Sleep (available on some devices)
2123 #[inline(always)]
2124 pub fn bods(&mut self) -> BODS_W<'_, MCUCR_SPEC> {
2125 BODS_W::new(self, 7)
2126 }
2127 }
2128 /**MCU Control Register
2129
2130You can [`read`](crate::Reg::read) this register and get [`mcucr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mcucr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
2131 pub struct MCUCR_SPEC;
2132 impl crate::RegisterSpec for MCUCR_SPEC {
2133 type Ux = u8;
2134 }
2135 ///`read()` method returns [`mcucr::R`](R) reader structure
2136 impl crate::Readable for MCUCR_SPEC {}
2137 ///`write(|w| ..)` method takes [`mcucr::W`](W) writer structure
2138 impl crate::Writable for MCUCR_SPEC {
2139 type Safety = crate::Unsafe;
2140 }
2141 ///`reset()` method sets MCUCR to value 0
2142 impl crate::Resettable for MCUCR_SPEC {}
2143 }
2144 /**MCUSR (rw) register accessor: MCU Status register
2145
2146You can [`read`](crate::Reg::read) this register and get [`mcusr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mcusr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
2147
2148For information about available fields see [`mod@mcusr`] module*/
2149 pub type MCUSR = crate::Reg<mcusr::MCUSR_SPEC>;
2150 ///MCU Status register
2151 pub mod mcusr {
2152 ///Register `MCUSR` reader
2153 pub type R = crate::R<MCUSR_SPEC>;
2154 ///Register `MCUSR` writer
2155 pub type W = crate::W<MCUSR_SPEC>;
2156 ///Field `PORF` reader - Power-On Reset Flag
2157 pub type PORF_R = crate::BitReader;
2158 ///Field `PORF` writer - Power-On Reset Flag
2159 pub type PORF_W<'a, REG> = crate::BitWriter<'a, REG>;
2160 ///Field `EXTRF` reader - External Reset Flag
2161 pub type EXTRF_R = crate::BitReader;
2162 ///Field `EXTRF` writer - External Reset Flag
2163 pub type EXTRF_W<'a, REG> = crate::BitWriter<'a, REG>;
2164 ///Field `BORF` reader - Brown-out Reset Flag
2165 pub type BORF_R = crate::BitReader;
2166 ///Field `BORF` writer - Brown-out Reset Flag
2167 pub type BORF_W<'a, REG> = crate::BitWriter<'a, REG>;
2168 ///Field `WDRF` reader - Watchdog Reset Flag
2169 pub type WDRF_R = crate::BitReader;
2170 ///Field `WDRF` writer - Watchdog Reset Flag
2171 pub type WDRF_W<'a, REG> = crate::BitWriter<'a, REG>;
2172 impl R {
2173 ///Bit 0 - Power-On Reset Flag
2174 #[inline(always)]
2175 pub fn porf(&self) -> PORF_R {
2176 PORF_R::new((self.bits & 1) != 0)
2177 }
2178 ///Bit 1 - External Reset Flag
2179 #[inline(always)]
2180 pub fn extrf(&self) -> EXTRF_R {
2181 EXTRF_R::new(((self.bits >> 1) & 1) != 0)
2182 }
2183 ///Bit 2 - Brown-out Reset Flag
2184 #[inline(always)]
2185 pub fn borf(&self) -> BORF_R {
2186 BORF_R::new(((self.bits >> 2) & 1) != 0)
2187 }
2188 ///Bit 3 - Watchdog Reset Flag
2189 #[inline(always)]
2190 pub fn wdrf(&self) -> WDRF_R {
2191 WDRF_R::new(((self.bits >> 3) & 1) != 0)
2192 }
2193 }
2194 impl W {
2195 ///Bit 0 - Power-On Reset Flag
2196 #[inline(always)]
2197 pub fn porf(&mut self) -> PORF_W<'_, MCUSR_SPEC> {
2198 PORF_W::new(self, 0)
2199 }
2200 ///Bit 1 - External Reset Flag
2201 #[inline(always)]
2202 pub fn extrf(&mut self) -> EXTRF_W<'_, MCUSR_SPEC> {
2203 EXTRF_W::new(self, 1)
2204 }
2205 ///Bit 2 - Brown-out Reset Flag
2206 #[inline(always)]
2207 pub fn borf(&mut self) -> BORF_W<'_, MCUSR_SPEC> {
2208 BORF_W::new(self, 2)
2209 }
2210 ///Bit 3 - Watchdog Reset Flag
2211 #[inline(always)]
2212 pub fn wdrf(&mut self) -> WDRF_W<'_, MCUSR_SPEC> {
2213 WDRF_W::new(self, 3)
2214 }
2215 }
2216 /**MCU Status register
2217
2218You can [`read`](crate::Reg::read) this register and get [`mcusr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mcusr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
2219 pub struct MCUSR_SPEC;
2220 impl crate::RegisterSpec for MCUSR_SPEC {
2221 type Ux = u8;
2222 }
2223 ///`read()` method returns [`mcusr::R`](R) reader structure
2224 impl crate::Readable for MCUSR_SPEC {}
2225 ///`write(|w| ..)` method takes [`mcusr::W`](W) writer structure
2226 impl crate::Writable for MCUSR_SPEC {
2227 type Safety = crate::Unsafe;
2228 }
2229 ///`reset()` method sets MCUSR to value 0
2230 impl crate::Resettable for MCUSR_SPEC {}
2231 }
2232 /**OSCCAL (rw) register accessor: Oscillator Calibration Register
2233
2234You can [`read`](crate::Reg::read) this register and get [`osccal::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`osccal::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
2235
2236For information about available fields see [`mod@osccal`] module*/
2237 pub type OSCCAL = crate::Reg<osccal::OSCCAL_SPEC>;
2238 ///Oscillator Calibration Register
2239 pub mod osccal {
2240 ///Register `OSCCAL` reader
2241 pub type R = crate::R<OSCCAL_SPEC>;
2242 ///Register `OSCCAL` writer
2243 pub type W = crate::W<OSCCAL_SPEC>;
2244 ///Field `OSCCAL` reader - Oscillator Calibration
2245 pub type OSCCAL_R = crate::FieldReader;
2246 ///Field `OSCCAL` writer - Oscillator Calibration
2247 pub type OSCCAL_W<'a, REG> = crate::FieldWriter<'a, REG, 8, u8, crate::Safe>;
2248 impl R {
2249 ///Bits 0:7 - Oscillator Calibration
2250 #[inline(always)]
2251 pub fn osccal(&self) -> OSCCAL_R {
2252 OSCCAL_R::new(self.bits)
2253 }
2254 }
2255 impl W {
2256 ///Bits 0:7 - Oscillator Calibration
2257 #[inline(always)]
2258 pub fn osccal(&mut self) -> OSCCAL_W<'_, OSCCAL_SPEC> {
2259 OSCCAL_W::new(self, 0)
2260 }
2261 }
2262 /**Oscillator Calibration Register
2263
2264You can [`read`](crate::Reg::read) this register and get [`osccal::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`osccal::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
2265 pub struct OSCCAL_SPEC;
2266 impl crate::RegisterSpec for OSCCAL_SPEC {
2267 type Ux = u8;
2268 }
2269 ///`read()` method returns [`osccal::R`](R) reader structure
2270 impl crate::Readable for OSCCAL_SPEC {}
2271 ///`write(|w| ..)` method takes [`osccal::W`](W) writer structure
2272 impl crate::Writable for OSCCAL_SPEC {
2273 type Safety = crate::Safe;
2274 }
2275 ///`reset()` method sets OSCCAL to value 0
2276 impl crate::Resettable for OSCCAL_SPEC {}
2277 }
2278 /**PLLCSR (rw) register accessor: PLL Control and status register
2279
2280You can [`read`](crate::Reg::read) this register and get [`pllcsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pllcsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
2281
2282For information about available fields see [`mod@pllcsr`] module*/
2283 pub type PLLCSR = crate::Reg<pllcsr::PLLCSR_SPEC>;
2284 ///PLL Control and status register
2285 pub mod pllcsr {
2286 ///Register `PLLCSR` reader
2287 pub type R = crate::R<PLLCSR_SPEC>;
2288 ///Register `PLLCSR` writer
2289 pub type W = crate::W<PLLCSR_SPEC>;
2290 ///Field `PLOCK` reader - PLL Lock detector
2291 pub type PLOCK_R = crate::BitReader;
2292 ///Field `PLLE` reader - PLL Enable
2293 pub type PLLE_R = crate::BitReader;
2294 ///Field `PLLE` writer - PLL Enable
2295 pub type PLLE_W<'a, REG> = crate::BitWriter<'a, REG>;
2296 ///Field `PCKE` reader - PCK Enable
2297 pub type PCKE_R = crate::BitReader;
2298 ///Field `PCKE` writer - PCK Enable
2299 pub type PCKE_W<'a, REG> = crate::BitWriter<'a, REG>;
2300 ///Field `LSM` reader - Low speed mode
2301 pub type LSM_R = crate::BitReader;
2302 ///Field `LSM` writer - Low speed mode
2303 pub type LSM_W<'a, REG> = crate::BitWriter<'a, REG>;
2304 impl R {
2305 ///Bit 0 - PLL Lock detector
2306 #[inline(always)]
2307 pub fn plock(&self) -> PLOCK_R {
2308 PLOCK_R::new((self.bits & 1) != 0)
2309 }
2310 ///Bit 1 - PLL Enable
2311 #[inline(always)]
2312 pub fn plle(&self) -> PLLE_R {
2313 PLLE_R::new(((self.bits >> 1) & 1) != 0)
2314 }
2315 ///Bit 2 - PCK Enable
2316 #[inline(always)]
2317 pub fn pcke(&self) -> PCKE_R {
2318 PCKE_R::new(((self.bits >> 2) & 1) != 0)
2319 }
2320 ///Bit 7 - Low speed mode
2321 #[inline(always)]
2322 pub fn lsm(&self) -> LSM_R {
2323 LSM_R::new(((self.bits >> 7) & 1) != 0)
2324 }
2325 }
2326 impl W {
2327 ///Bit 1 - PLL Enable
2328 #[inline(always)]
2329 pub fn plle(&mut self) -> PLLE_W<'_, PLLCSR_SPEC> {
2330 PLLE_W::new(self, 1)
2331 }
2332 ///Bit 2 - PCK Enable
2333 #[inline(always)]
2334 pub fn pcke(&mut self) -> PCKE_W<'_, PLLCSR_SPEC> {
2335 PCKE_W::new(self, 2)
2336 }
2337 ///Bit 7 - Low speed mode
2338 #[inline(always)]
2339 pub fn lsm(&mut self) -> LSM_W<'_, PLLCSR_SPEC> {
2340 LSM_W::new(self, 7)
2341 }
2342 }
2343 /**PLL Control and status register
2344
2345You can [`read`](crate::Reg::read) this register and get [`pllcsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pllcsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
2346 pub struct PLLCSR_SPEC;
2347 impl crate::RegisterSpec for PLLCSR_SPEC {
2348 type Ux = u8;
2349 }
2350 ///`read()` method returns [`pllcsr::R`](R) reader structure
2351 impl crate::Readable for PLLCSR_SPEC {}
2352 ///`write(|w| ..)` method takes [`pllcsr::W`](W) writer structure
2353 impl crate::Writable for PLLCSR_SPEC {
2354 type Safety = crate::Unsafe;
2355 }
2356 ///`reset()` method sets PLLCSR to value 0
2357 impl crate::Resettable for PLLCSR_SPEC {}
2358 }
2359 /**PRR (rw) register accessor: Power Reduction Register
2360
2361You can [`read`](crate::Reg::read) this register and get [`prr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`prr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
2362
2363For information about available fields see [`mod@prr`] module*/
2364 pub type PRR = crate::Reg<prr::PRR_SPEC>;
2365 ///Power Reduction Register
2366 pub mod prr {
2367 ///Register `PRR` reader
2368 pub type R = crate::R<PRR_SPEC>;
2369 ///Register `PRR` writer
2370 pub type W = crate::W<PRR_SPEC>;
2371 ///Field `PRADC` reader - Power Reduction ADC
2372 pub type PRADC_R = crate::BitReader;
2373 ///Field `PRADC` writer - Power Reduction ADC
2374 pub type PRADC_W<'a, REG> = crate::BitWriter<'a, REG>;
2375 ///Field `PRUSI` reader - Power Reduction USI
2376 pub type PRUSI_R = crate::BitReader;
2377 ///Field `PRUSI` writer - Power Reduction USI
2378 pub type PRUSI_W<'a, REG> = crate::BitWriter<'a, REG>;
2379 ///Field `PRTIM0` reader - Power Reduction Timer/Counter0
2380 pub type PRTIM0_R = crate::BitReader;
2381 ///Field `PRTIM0` writer - Power Reduction Timer/Counter0
2382 pub type PRTIM0_W<'a, REG> = crate::BitWriter<'a, REG>;
2383 ///Field `PRTIM1` reader - Power Reduction Timer/Counter1
2384 pub type PRTIM1_R = crate::BitReader;
2385 ///Field `PRTIM1` writer - Power Reduction Timer/Counter1
2386 pub type PRTIM1_W<'a, REG> = crate::BitWriter<'a, REG>;
2387 impl R {
2388 ///Bit 0 - Power Reduction ADC
2389 #[inline(always)]
2390 pub fn pradc(&self) -> PRADC_R {
2391 PRADC_R::new((self.bits & 1) != 0)
2392 }
2393 ///Bit 1 - Power Reduction USI
2394 #[inline(always)]
2395 pub fn prusi(&self) -> PRUSI_R {
2396 PRUSI_R::new(((self.bits >> 1) & 1) != 0)
2397 }
2398 ///Bit 2 - Power Reduction Timer/Counter0
2399 #[inline(always)]
2400 pub fn prtim0(&self) -> PRTIM0_R {
2401 PRTIM0_R::new(((self.bits >> 2) & 1) != 0)
2402 }
2403 ///Bit 3 - Power Reduction Timer/Counter1
2404 #[inline(always)]
2405 pub fn prtim1(&self) -> PRTIM1_R {
2406 PRTIM1_R::new(((self.bits >> 3) & 1) != 0)
2407 }
2408 }
2409 impl W {
2410 ///Bit 0 - Power Reduction ADC
2411 #[inline(always)]
2412 pub fn pradc(&mut self) -> PRADC_W<'_, PRR_SPEC> {
2413 PRADC_W::new(self, 0)
2414 }
2415 ///Bit 1 - Power Reduction USI
2416 #[inline(always)]
2417 pub fn prusi(&mut self) -> PRUSI_W<'_, PRR_SPEC> {
2418 PRUSI_W::new(self, 1)
2419 }
2420 ///Bit 2 - Power Reduction Timer/Counter0
2421 #[inline(always)]
2422 pub fn prtim0(&mut self) -> PRTIM0_W<'_, PRR_SPEC> {
2423 PRTIM0_W::new(self, 2)
2424 }
2425 ///Bit 3 - Power Reduction Timer/Counter1
2426 #[inline(always)]
2427 pub fn prtim1(&mut self) -> PRTIM1_W<'_, PRR_SPEC> {
2428 PRTIM1_W::new(self, 3)
2429 }
2430 }
2431 /**Power Reduction Register
2432
2433You can [`read`](crate::Reg::read) this register and get [`prr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`prr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
2434 pub struct PRR_SPEC;
2435 impl crate::RegisterSpec for PRR_SPEC {
2436 type Ux = u8;
2437 }
2438 ///`read()` method returns [`prr::R`](R) reader structure
2439 impl crate::Readable for PRR_SPEC {}
2440 ///`write(|w| ..)` method takes [`prr::W`](W) writer structure
2441 impl crate::Writable for PRR_SPEC {
2442 type Safety = crate::Unsafe;
2443 }
2444 ///`reset()` method sets PRR to value 0
2445 impl crate::Resettable for PRR_SPEC {}
2446 }
2447}
2448///EEPROM
2449pub type EEPROM = crate::Periph<eeprom::RegisterBlock, 0x3c>;
2450impl core::fmt::Debug for EEPROM {
2451 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2452 f.debug_struct("EEPROM").finish()
2453 }
2454}
2455///EEPROM
2456pub mod eeprom {
2457 #[repr(C)]
2458 ///Register block
2459 pub struct RegisterBlock {
2460 eecr: EECR,
2461 eedr: EEDR,
2462 eear: EEAR,
2463 }
2464 impl RegisterBlock {
2465 ///0x00 - EEPROM Control Register
2466 #[inline(always)]
2467 pub const fn eecr(&self) -> &EECR {
2468 &self.eecr
2469 }
2470 ///0x01 - EEPROM Data Register
2471 #[inline(always)]
2472 pub const fn eedr(&self) -> &EEDR {
2473 &self.eedr
2474 }
2475 ///0x02 - EEPROM Address Register Bytes
2476 #[inline(always)]
2477 pub const fn eear(&self) -> &EEAR {
2478 &self.eear
2479 }
2480 }
2481 /**EEAR (rw) register accessor: EEPROM Address Register Bytes
2482
2483You can [`read`](crate::Reg::read) this register and get [`eear::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eear::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
2484
2485For information about available fields see [`mod@eear`] module*/
2486 pub type EEAR = crate::Reg<eear::EEAR_SPEC>;
2487 ///EEPROM Address Register Bytes
2488 pub mod eear {
2489 ///Register `EEAR` reader
2490 pub type R = crate::R<EEAR_SPEC>;
2491 ///Register `EEAR` writer
2492 pub type W = crate::W<EEAR_SPEC>;
2493 impl core::fmt::Debug for R {
2494 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2495 write!(f, "{}", self.bits())
2496 }
2497 }
2498 impl W {}
2499 /**EEPROM Address Register Bytes
2500
2501You can [`read`](crate::Reg::read) this register and get [`eear::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eear::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
2502 pub struct EEAR_SPEC;
2503 impl crate::RegisterSpec for EEAR_SPEC {
2504 type Ux = u16;
2505 }
2506 ///`read()` method returns [`eear::R`](R) reader structure
2507 impl crate::Readable for EEAR_SPEC {}
2508 ///`write(|w| ..)` method takes [`eear::W`](W) writer structure
2509 impl crate::Writable for EEAR_SPEC {
2510 type Safety = crate::Safe;
2511 }
2512 ///`reset()` method sets EEAR to value 0
2513 impl crate::Resettable for EEAR_SPEC {}
2514 }
2515 /**EECR (rw) register accessor: EEPROM Control Register
2516
2517You can [`read`](crate::Reg::read) this register and get [`eecr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eecr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
2518
2519For information about available fields see [`mod@eecr`] module*/
2520 pub type EECR = crate::Reg<eecr::EECR_SPEC>;
2521 ///EEPROM Control Register
2522 pub mod eecr {
2523 ///Register `EECR` reader
2524 pub type R = crate::R<EECR_SPEC>;
2525 ///Register `EECR` writer
2526 pub type W = crate::W<EECR_SPEC>;
2527 ///Field `EERE` reader - EEPROM Read Enable
2528 pub type EERE_R = crate::BitReader;
2529 ///Field `EERE` writer - EEPROM Read Enable
2530 pub type EERE_W<'a, REG> = crate::BitWriter<'a, REG>;
2531 ///Field `EEPE` reader - EEPROM Write Enable
2532 pub type EEPE_R = crate::BitReader;
2533 ///Field `EEPE` writer - EEPROM Write Enable
2534 pub type EEPE_W<'a, REG> = crate::BitWriter<'a, REG>;
2535 ///Field `EEMPE` reader - EEPROM Master Write Enable
2536 pub type EEMPE_R = crate::BitReader;
2537 ///Field `EEMPE` writer - EEPROM Master Write Enable
2538 pub type EEMPE_W<'a, REG> = crate::BitWriter<'a, REG>;
2539 ///Field `EERIE` reader - EEPROM Ready Interrupt Enable
2540 pub type EERIE_R = crate::BitReader;
2541 ///Field `EERIE` writer - EEPROM Ready Interrupt Enable
2542 pub type EERIE_W<'a, REG> = crate::BitWriter<'a, REG>;
2543 /**EEPROM Programming Mode Bits
2544
2545Value on reset: 0*/
2546 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
2547 #[repr(u8)]
2548 pub enum EEPM_A {
2549 ///0: Atomic (erase and write in one operation)
2550 ATOMIC = 0,
2551 ///1: Erase only
2552 ERASE = 1,
2553 ///2: Write only
2554 WRITE = 2,
2555 }
2556 impl From<EEPM_A> for u8 {
2557 #[inline(always)]
2558 fn from(variant: EEPM_A) -> Self {
2559 variant as _
2560 }
2561 }
2562 impl crate::FieldSpec for EEPM_A {
2563 type Ux = u8;
2564 }
2565 impl crate::IsEnum for EEPM_A {}
2566 ///Field `EEPM` reader - EEPROM Programming Mode Bits
2567 pub type EEPM_R = crate::FieldReader<EEPM_A>;
2568 impl EEPM_R {
2569 ///Get enumerated values variant
2570 #[inline(always)]
2571 pub const fn variant(&self) -> Option<EEPM_A> {
2572 match self.bits {
2573 0 => Some(EEPM_A::ATOMIC),
2574 1 => Some(EEPM_A::ERASE),
2575 2 => Some(EEPM_A::WRITE),
2576 _ => None,
2577 }
2578 }
2579 ///Atomic (erase and write in one operation)
2580 #[inline(always)]
2581 pub fn is_atomic(&self) -> bool {
2582 *self == EEPM_A::ATOMIC
2583 }
2584 ///Erase only
2585 #[inline(always)]
2586 pub fn is_erase(&self) -> bool {
2587 *self == EEPM_A::ERASE
2588 }
2589 ///Write only
2590 #[inline(always)]
2591 pub fn is_write(&self) -> bool {
2592 *self == EEPM_A::WRITE
2593 }
2594 }
2595 ///Field `EEPM` writer - EEPROM Programming Mode Bits
2596 pub type EEPM_W<'a, REG> = crate::FieldWriter<'a, REG, 2, EEPM_A>;
2597 impl<'a, REG> EEPM_W<'a, REG>
2598 where
2599 REG: crate::Writable + crate::RegisterSpec,
2600 REG::Ux: From<u8>,
2601 {
2602 ///Atomic (erase and write in one operation)
2603 #[inline(always)]
2604 pub fn atomic(self) -> &'a mut crate::W<REG> {
2605 self.variant(EEPM_A::ATOMIC)
2606 }
2607 ///Erase only
2608 #[inline(always)]
2609 pub fn erase(self) -> &'a mut crate::W<REG> {
2610 self.variant(EEPM_A::ERASE)
2611 }
2612 ///Write only
2613 #[inline(always)]
2614 pub fn write(self) -> &'a mut crate::W<REG> {
2615 self.variant(EEPM_A::WRITE)
2616 }
2617 }
2618 impl R {
2619 ///Bit 0 - EEPROM Read Enable
2620 #[inline(always)]
2621 pub fn eere(&self) -> EERE_R {
2622 EERE_R::new((self.bits & 1) != 0)
2623 }
2624 ///Bit 1 - EEPROM Write Enable
2625 #[inline(always)]
2626 pub fn eepe(&self) -> EEPE_R {
2627 EEPE_R::new(((self.bits >> 1) & 1) != 0)
2628 }
2629 ///Bit 2 - EEPROM Master Write Enable
2630 #[inline(always)]
2631 pub fn eempe(&self) -> EEMPE_R {
2632 EEMPE_R::new(((self.bits >> 2) & 1) != 0)
2633 }
2634 ///Bit 3 - EEPROM Ready Interrupt Enable
2635 #[inline(always)]
2636 pub fn eerie(&self) -> EERIE_R {
2637 EERIE_R::new(((self.bits >> 3) & 1) != 0)
2638 }
2639 ///Bits 4:5 - EEPROM Programming Mode Bits
2640 #[inline(always)]
2641 pub fn eepm(&self) -> EEPM_R {
2642 EEPM_R::new((self.bits >> 4) & 3)
2643 }
2644 }
2645 impl W {
2646 ///Bit 0 - EEPROM Read Enable
2647 #[inline(always)]
2648 pub fn eere(&mut self) -> EERE_W<'_, EECR_SPEC> {
2649 EERE_W::new(self, 0)
2650 }
2651 ///Bit 1 - EEPROM Write Enable
2652 #[inline(always)]
2653 pub fn eepe(&mut self) -> EEPE_W<'_, EECR_SPEC> {
2654 EEPE_W::new(self, 1)
2655 }
2656 ///Bit 2 - EEPROM Master Write Enable
2657 #[inline(always)]
2658 pub fn eempe(&mut self) -> EEMPE_W<'_, EECR_SPEC> {
2659 EEMPE_W::new(self, 2)
2660 }
2661 ///Bit 3 - EEPROM Ready Interrupt Enable
2662 #[inline(always)]
2663 pub fn eerie(&mut self) -> EERIE_W<'_, EECR_SPEC> {
2664 EERIE_W::new(self, 3)
2665 }
2666 ///Bits 4:5 - EEPROM Programming Mode Bits
2667 #[inline(always)]
2668 pub fn eepm(&mut self) -> EEPM_W<'_, EECR_SPEC> {
2669 EEPM_W::new(self, 4)
2670 }
2671 }
2672 /**EEPROM Control Register
2673
2674You can [`read`](crate::Reg::read) this register and get [`eecr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eecr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
2675 pub struct EECR_SPEC;
2676 impl crate::RegisterSpec for EECR_SPEC {
2677 type Ux = u8;
2678 }
2679 ///`read()` method returns [`eecr::R`](R) reader structure
2680 impl crate::Readable for EECR_SPEC {}
2681 ///`write(|w| ..)` method takes [`eecr::W`](W) writer structure
2682 impl crate::Writable for EECR_SPEC {
2683 type Safety = crate::Unsafe;
2684 }
2685 ///`reset()` method sets EECR to value 0
2686 impl crate::Resettable for EECR_SPEC {}
2687 }
2688 /**EEDR (rw) register accessor: EEPROM Data Register
2689
2690You can [`read`](crate::Reg::read) this register and get [`eedr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eedr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
2691
2692For information about available fields see [`mod@eedr`] module*/
2693 pub type EEDR = crate::Reg<eedr::EEDR_SPEC>;
2694 ///EEPROM Data Register
2695 pub mod eedr {
2696 ///Register `EEDR` reader
2697 pub type R = crate::R<EEDR_SPEC>;
2698 ///Register `EEDR` writer
2699 pub type W = crate::W<EEDR_SPEC>;
2700 impl core::fmt::Debug for R {
2701 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2702 write!(f, "{}", self.bits())
2703 }
2704 }
2705 impl W {}
2706 /**EEPROM Data Register
2707
2708You can [`read`](crate::Reg::read) this register and get [`eedr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eedr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
2709 pub struct EEDR_SPEC;
2710 impl crate::RegisterSpec for EEDR_SPEC {
2711 type Ux = u8;
2712 }
2713 ///`read()` method returns [`eedr::R`](R) reader structure
2714 impl crate::Readable for EEDR_SPEC {}
2715 ///`write(|w| ..)` method takes [`eedr::W`](W) writer structure
2716 impl crate::Writable for EEDR_SPEC {
2717 type Safety = crate::Safe;
2718 }
2719 ///`reset()` method sets EEDR to value 0
2720 impl crate::Resettable for EEDR_SPEC {}
2721 }
2722}
2723///External Interrupts
2724pub type EXINT = crate::Periph<exint::RegisterBlock, 0x35>;
2725impl core::fmt::Debug for EXINT {
2726 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2727 f.debug_struct("EXINT").finish()
2728 }
2729}
2730///External Interrupts
2731pub mod exint {
2732 #[repr(C)]
2733 ///Register block
2734 pub struct RegisterBlock {
2735 pcmsk: PCMSK,
2736 _reserved1: [u8; 0x1f],
2737 mcucr: MCUCR,
2738 _reserved2: [u8; 0x04],
2739 gifr: GIFR,
2740 gimsk: GIMSK,
2741 }
2742 impl RegisterBlock {
2743 ///0x00 - Pin Change Enable Mask
2744 #[inline(always)]
2745 pub const fn pcmsk(&self) -> &PCMSK {
2746 &self.pcmsk
2747 }
2748 ///0x20 - MCU Control Register
2749 #[inline(always)]
2750 pub const fn mcucr(&self) -> &MCUCR {
2751 &self.mcucr
2752 }
2753 ///0x25 - General Interrupt Flag register
2754 #[inline(always)]
2755 pub const fn gifr(&self) -> &GIFR {
2756 &self.gifr
2757 }
2758 ///0x26 - General Interrupt Mask Register
2759 #[inline(always)]
2760 pub const fn gimsk(&self) -> &GIMSK {
2761 &self.gimsk
2762 }
2763 }
2764 /**GIFR (rw) register accessor: General Interrupt Flag register
2765
2766You can [`read`](crate::Reg::read) this register and get [`gifr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gifr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
2767
2768For information about available fields see [`mod@gifr`] module*/
2769 pub type GIFR = crate::Reg<gifr::GIFR_SPEC>;
2770 ///General Interrupt Flag register
2771 pub mod gifr {
2772 ///Register `GIFR` reader
2773 pub type R = crate::R<GIFR_SPEC>;
2774 ///Register `GIFR` writer
2775 pub type W = crate::W<GIFR_SPEC>;
2776 ///Field `PCIF` reader - Pin Change Interrupt Flag
2777 pub type PCIF_R = crate::BitReader;
2778 ///Field `PCIF` writer - Pin Change Interrupt Flag
2779 pub type PCIF_W<'a, REG> = crate::BitWriter<'a, REG>;
2780 ///Field `INTF0` reader - External Interrupt Flag 0
2781 pub type INTF0_R = crate::BitReader;
2782 ///Field `INTF0` writer - External Interrupt Flag 0
2783 pub type INTF0_W<'a, REG> = crate::BitWriter<'a, REG>;
2784 impl R {
2785 ///Bit 5 - Pin Change Interrupt Flag
2786 #[inline(always)]
2787 pub fn pcif(&self) -> PCIF_R {
2788 PCIF_R::new(((self.bits >> 5) & 1) != 0)
2789 }
2790 ///Bit 6 - External Interrupt Flag 0
2791 #[inline(always)]
2792 pub fn intf0(&self) -> INTF0_R {
2793 INTF0_R::new(((self.bits >> 6) & 1) != 0)
2794 }
2795 }
2796 impl W {
2797 ///Bit 5 - Pin Change Interrupt Flag
2798 #[inline(always)]
2799 pub fn pcif(&mut self) -> PCIF_W<'_, GIFR_SPEC> {
2800 PCIF_W::new(self, 5)
2801 }
2802 ///Bit 6 - External Interrupt Flag 0
2803 #[inline(always)]
2804 pub fn intf0(&mut self) -> INTF0_W<'_, GIFR_SPEC> {
2805 INTF0_W::new(self, 6)
2806 }
2807 }
2808 /**General Interrupt Flag register
2809
2810You can [`read`](crate::Reg::read) this register and get [`gifr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gifr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
2811 pub struct GIFR_SPEC;
2812 impl crate::RegisterSpec for GIFR_SPEC {
2813 type Ux = u8;
2814 }
2815 ///`read()` method returns [`gifr::R`](R) reader structure
2816 impl crate::Readable for GIFR_SPEC {}
2817 ///`write(|w| ..)` method takes [`gifr::W`](W) writer structure
2818 impl crate::Writable for GIFR_SPEC {
2819 type Safety = crate::Unsafe;
2820 }
2821 ///`reset()` method sets GIFR to value 0
2822 impl crate::Resettable for GIFR_SPEC {}
2823 }
2824 /**GIMSK (rw) register accessor: General Interrupt Mask Register
2825
2826You can [`read`](crate::Reg::read) this register and get [`gimsk::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gimsk::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
2827
2828For information about available fields see [`mod@gimsk`] module*/
2829 pub type GIMSK = crate::Reg<gimsk::GIMSK_SPEC>;
2830 ///General Interrupt Mask Register
2831 pub mod gimsk {
2832 ///Register `GIMSK` reader
2833 pub type R = crate::R<GIMSK_SPEC>;
2834 ///Register `GIMSK` writer
2835 pub type W = crate::W<GIMSK_SPEC>;
2836 ///Field `PCIE` reader - Pin Change Interrupt Enable
2837 pub type PCIE_R = crate::BitReader;
2838 ///Field `PCIE` writer - Pin Change Interrupt Enable
2839 pub type PCIE_W<'a, REG> = crate::BitWriter<'a, REG>;
2840 ///Field `INT0` reader - External Interrupt Request 0 Enable
2841 pub type INT0_R = crate::BitReader;
2842 ///Field `INT0` writer - External Interrupt Request 0 Enable
2843 pub type INT0_W<'a, REG> = crate::BitWriter<'a, REG>;
2844 impl R {
2845 ///Bit 5 - Pin Change Interrupt Enable
2846 #[inline(always)]
2847 pub fn pcie(&self) -> PCIE_R {
2848 PCIE_R::new(((self.bits >> 5) & 1) != 0)
2849 }
2850 ///Bit 6 - External Interrupt Request 0 Enable
2851 #[inline(always)]
2852 pub fn int0(&self) -> INT0_R {
2853 INT0_R::new(((self.bits >> 6) & 1) != 0)
2854 }
2855 }
2856 impl W {
2857 ///Bit 5 - Pin Change Interrupt Enable
2858 #[inline(always)]
2859 pub fn pcie(&mut self) -> PCIE_W<'_, GIMSK_SPEC> {
2860 PCIE_W::new(self, 5)
2861 }
2862 ///Bit 6 - External Interrupt Request 0 Enable
2863 #[inline(always)]
2864 pub fn int0(&mut self) -> INT0_W<'_, GIMSK_SPEC> {
2865 INT0_W::new(self, 6)
2866 }
2867 }
2868 /**General Interrupt Mask Register
2869
2870You can [`read`](crate::Reg::read) this register and get [`gimsk::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gimsk::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
2871 pub struct GIMSK_SPEC;
2872 impl crate::RegisterSpec for GIMSK_SPEC {
2873 type Ux = u8;
2874 }
2875 ///`read()` method returns [`gimsk::R`](R) reader structure
2876 impl crate::Readable for GIMSK_SPEC {}
2877 ///`write(|w| ..)` method takes [`gimsk::W`](W) writer structure
2878 impl crate::Writable for GIMSK_SPEC {
2879 type Safety = crate::Unsafe;
2880 }
2881 ///`reset()` method sets GIMSK to value 0
2882 impl crate::Resettable for GIMSK_SPEC {}
2883 }
2884 /**MCUCR (rw) register accessor: MCU Control Register
2885
2886You can [`read`](crate::Reg::read) this register and get [`mcucr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mcucr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
2887
2888For information about available fields see [`mod@mcucr`] module*/
2889 pub type MCUCR = crate::Reg<mcucr::MCUCR_SPEC>;
2890 ///MCU Control Register
2891 pub mod mcucr {
2892 ///Register `MCUCR` reader
2893 pub type R = crate::R<MCUCR_SPEC>;
2894 ///Register `MCUCR` writer
2895 pub type W = crate::W<MCUCR_SPEC>;
2896 /**Interrupt Sense Control 0 bits
2897
2898Value on reset: 0*/
2899 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
2900 #[repr(u8)]
2901 pub enum ISC0_A {
2902 ///0: The low level of INTx generates an interrupt request
2903 LOW = 0,
2904 ///1: Any logical change on INTx generates an interrupt request
2905 TOGGLE = 1,
2906 ///2: The falling edge of INTx generates an interrupt request
2907 FALLING = 2,
2908 ///3: The rising edge of INTx generates an interrupt request
2909 RISING = 3,
2910 }
2911 impl From<ISC0_A> for u8 {
2912 #[inline(always)]
2913 fn from(variant: ISC0_A) -> Self {
2914 variant as _
2915 }
2916 }
2917 impl crate::FieldSpec for ISC0_A {
2918 type Ux = u8;
2919 }
2920 impl crate::IsEnum for ISC0_A {}
2921 ///Field `ISC0` reader - Interrupt Sense Control 0 bits
2922 pub type ISC0_R = crate::FieldReader<ISC0_A>;
2923 impl ISC0_R {
2924 ///Get enumerated values variant
2925 #[inline(always)]
2926 pub const fn variant(&self) -> ISC0_A {
2927 match self.bits {
2928 0 => ISC0_A::LOW,
2929 1 => ISC0_A::TOGGLE,
2930 2 => ISC0_A::FALLING,
2931 3 => ISC0_A::RISING,
2932 _ => unreachable!(),
2933 }
2934 }
2935 ///The low level of INTx generates an interrupt request
2936 #[inline(always)]
2937 pub fn is_low(&self) -> bool {
2938 *self == ISC0_A::LOW
2939 }
2940 ///Any logical change on INTx generates an interrupt request
2941 #[inline(always)]
2942 pub fn is_toggle(&self) -> bool {
2943 *self == ISC0_A::TOGGLE
2944 }
2945 ///The falling edge of INTx generates an interrupt request
2946 #[inline(always)]
2947 pub fn is_falling(&self) -> bool {
2948 *self == ISC0_A::FALLING
2949 }
2950 ///The rising edge of INTx generates an interrupt request
2951 #[inline(always)]
2952 pub fn is_rising(&self) -> bool {
2953 *self == ISC0_A::RISING
2954 }
2955 }
2956 ///Field `ISC0` writer - Interrupt Sense Control 0 bits
2957 pub type ISC0_W<'a, REG> = crate::FieldWriter<'a, REG, 2, ISC0_A, crate::Safe>;
2958 impl<'a, REG> ISC0_W<'a, REG>
2959 where
2960 REG: crate::Writable + crate::RegisterSpec,
2961 REG::Ux: From<u8>,
2962 {
2963 ///The low level of INTx generates an interrupt request
2964 #[inline(always)]
2965 pub fn low(self) -> &'a mut crate::W<REG> {
2966 self.variant(ISC0_A::LOW)
2967 }
2968 ///Any logical change on INTx generates an interrupt request
2969 #[inline(always)]
2970 pub fn toggle(self) -> &'a mut crate::W<REG> {
2971 self.variant(ISC0_A::TOGGLE)
2972 }
2973 ///The falling edge of INTx generates an interrupt request
2974 #[inline(always)]
2975 pub fn falling(self) -> &'a mut crate::W<REG> {
2976 self.variant(ISC0_A::FALLING)
2977 }
2978 ///The rising edge of INTx generates an interrupt request
2979 #[inline(always)]
2980 pub fn rising(self) -> &'a mut crate::W<REG> {
2981 self.variant(ISC0_A::RISING)
2982 }
2983 }
2984 impl R {
2985 ///Bits 0:1 - Interrupt Sense Control 0 bits
2986 #[inline(always)]
2987 pub fn isc0(&self) -> ISC0_R {
2988 ISC0_R::new(self.bits & 3)
2989 }
2990 }
2991 impl W {
2992 ///Bits 0:1 - Interrupt Sense Control 0 bits
2993 #[inline(always)]
2994 pub fn isc0(&mut self) -> ISC0_W<'_, MCUCR_SPEC> {
2995 ISC0_W::new(self, 0)
2996 }
2997 }
2998 /**MCU Control Register
2999
3000You can [`read`](crate::Reg::read) this register and get [`mcucr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mcucr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
3001 pub struct MCUCR_SPEC;
3002 impl crate::RegisterSpec for MCUCR_SPEC {
3003 type Ux = u8;
3004 }
3005 ///`read()` method returns [`mcucr::R`](R) reader structure
3006 impl crate::Readable for MCUCR_SPEC {}
3007 ///`write(|w| ..)` method takes [`mcucr::W`](W) writer structure
3008 impl crate::Writable for MCUCR_SPEC {
3009 type Safety = crate::Unsafe;
3010 }
3011 ///`reset()` method sets MCUCR to value 0
3012 impl crate::Resettable for MCUCR_SPEC {}
3013 }
3014 /**PCMSK (rw) register accessor: Pin Change Enable Mask
3015
3016You can [`read`](crate::Reg::read) this register and get [`pcmsk::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcmsk::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
3017
3018For information about available fields see [`mod@pcmsk`] module*/
3019 pub type PCMSK = crate::Reg<pcmsk::PCMSK_SPEC>;
3020 ///Pin Change Enable Mask
3021 pub mod pcmsk {
3022 ///Register `PCMSK` reader
3023 pub type R = crate::R<PCMSK_SPEC>;
3024 ///Register `PCMSK` writer
3025 pub type W = crate::W<PCMSK_SPEC>;
3026 ///Field `PCINT0` reader - Enable pin change interrupt on pin 0
3027 pub type PCINT0_R = crate::BitReader;
3028 ///Field `PCINT0` writer - Enable pin change interrupt on pin 0
3029 pub type PCINT0_W<'a, REG> = crate::BitWriter<'a, REG>;
3030 ///Field `PCINT1` reader - Enable pin change interrupt on pin 1
3031 pub type PCINT1_R = crate::BitReader;
3032 ///Field `PCINT1` writer - Enable pin change interrupt on pin 1
3033 pub type PCINT1_W<'a, REG> = crate::BitWriter<'a, REG>;
3034 ///Field `PCINT2` reader - Enable pin change interrupt on pin 2
3035 pub type PCINT2_R = crate::BitReader;
3036 ///Field `PCINT2` writer - Enable pin change interrupt on pin 2
3037 pub type PCINT2_W<'a, REG> = crate::BitWriter<'a, REG>;
3038 ///Field `PCINT3` reader - Enable pin change interrupt on pin 3
3039 pub type PCINT3_R = crate::BitReader;
3040 ///Field `PCINT3` writer - Enable pin change interrupt on pin 3
3041 pub type PCINT3_W<'a, REG> = crate::BitWriter<'a, REG>;
3042 ///Field `PCINT4` reader - Enable pin change interrupt on pin 4
3043 pub type PCINT4_R = crate::BitReader;
3044 ///Field `PCINT4` writer - Enable pin change interrupt on pin 4
3045 pub type PCINT4_W<'a, REG> = crate::BitWriter<'a, REG>;
3046 ///Field `PCINT5` reader - Enable pin change interrupt on pin 5
3047 pub type PCINT5_R = crate::BitReader;
3048 ///Field `PCINT5` writer - Enable pin change interrupt on pin 5
3049 pub type PCINT5_W<'a, REG> = crate::BitWriter<'a, REG>;
3050 impl R {
3051 ///Bit 0 - Enable pin change interrupt on pin 0
3052 #[inline(always)]
3053 pub fn pcint0(&self) -> PCINT0_R {
3054 PCINT0_R::new((self.bits & 1) != 0)
3055 }
3056 ///Bit 1 - Enable pin change interrupt on pin 1
3057 #[inline(always)]
3058 pub fn pcint1(&self) -> PCINT1_R {
3059 PCINT1_R::new(((self.bits >> 1) & 1) != 0)
3060 }
3061 ///Bit 2 - Enable pin change interrupt on pin 2
3062 #[inline(always)]
3063 pub fn pcint2(&self) -> PCINT2_R {
3064 PCINT2_R::new(((self.bits >> 2) & 1) != 0)
3065 }
3066 ///Bit 3 - Enable pin change interrupt on pin 3
3067 #[inline(always)]
3068 pub fn pcint3(&self) -> PCINT3_R {
3069 PCINT3_R::new(((self.bits >> 3) & 1) != 0)
3070 }
3071 ///Bit 4 - Enable pin change interrupt on pin 4
3072 #[inline(always)]
3073 pub fn pcint4(&self) -> PCINT4_R {
3074 PCINT4_R::new(((self.bits >> 4) & 1) != 0)
3075 }
3076 ///Bit 5 - Enable pin change interrupt on pin 5
3077 #[inline(always)]
3078 pub fn pcint5(&self) -> PCINT5_R {
3079 PCINT5_R::new(((self.bits >> 5) & 1) != 0)
3080 }
3081 }
3082 impl W {
3083 ///Bit 0 - Enable pin change interrupt on pin 0
3084 #[inline(always)]
3085 pub fn pcint0(&mut self) -> PCINT0_W<'_, PCMSK_SPEC> {
3086 PCINT0_W::new(self, 0)
3087 }
3088 ///Bit 1 - Enable pin change interrupt on pin 1
3089 #[inline(always)]
3090 pub fn pcint1(&mut self) -> PCINT1_W<'_, PCMSK_SPEC> {
3091 PCINT1_W::new(self, 1)
3092 }
3093 ///Bit 2 - Enable pin change interrupt on pin 2
3094 #[inline(always)]
3095 pub fn pcint2(&mut self) -> PCINT2_W<'_, PCMSK_SPEC> {
3096 PCINT2_W::new(self, 2)
3097 }
3098 ///Bit 3 - Enable pin change interrupt on pin 3
3099 #[inline(always)]
3100 pub fn pcint3(&mut self) -> PCINT3_W<'_, PCMSK_SPEC> {
3101 PCINT3_W::new(self, 3)
3102 }
3103 ///Bit 4 - Enable pin change interrupt on pin 4
3104 #[inline(always)]
3105 pub fn pcint4(&mut self) -> PCINT4_W<'_, PCMSK_SPEC> {
3106 PCINT4_W::new(self, 4)
3107 }
3108 ///Bit 5 - Enable pin change interrupt on pin 5
3109 #[inline(always)]
3110 pub fn pcint5(&mut self) -> PCINT5_W<'_, PCMSK_SPEC> {
3111 PCINT5_W::new(self, 5)
3112 }
3113 }
3114 /**Pin Change Enable Mask
3115
3116You can [`read`](crate::Reg::read) this register and get [`pcmsk::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcmsk::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
3117 pub struct PCMSK_SPEC;
3118 impl crate::RegisterSpec for PCMSK_SPEC {
3119 type Ux = u8;
3120 }
3121 ///`read()` method returns [`pcmsk::R`](R) reader structure
3122 impl crate::Readable for PCMSK_SPEC {}
3123 ///`write(|w| ..)` method takes [`pcmsk::W`](W) writer structure
3124 impl crate::Writable for PCMSK_SPEC {
3125 type Safety = crate::Safe;
3126 }
3127 ///`reset()` method sets PCMSK to value 0
3128 impl crate::Resettable for PCMSK_SPEC {}
3129 }
3130}
3131///Fuses
3132pub type FUSE = crate::Periph<fuse::RegisterBlock, 0>;
3133impl core::fmt::Debug for FUSE {
3134 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
3135 f.debug_struct("FUSE").finish()
3136 }
3137}
3138///Fuses
3139pub mod fuse {
3140 #[repr(C)]
3141 ///Register block
3142 pub struct RegisterBlock {
3143 low: LOW,
3144 high: HIGH,
3145 extended: EXTENDED,
3146 }
3147 impl RegisterBlock {
3148 ///0x00 - No Description.
3149 #[inline(always)]
3150 pub const fn low(&self) -> &LOW {
3151 &self.low
3152 }
3153 ///0x01 - No Description.
3154 #[inline(always)]
3155 pub const fn high(&self) -> &HIGH {
3156 &self.high
3157 }
3158 ///0x02 - No Description.
3159 #[inline(always)]
3160 pub const fn extended(&self) -> &EXTENDED {
3161 &self.extended
3162 }
3163 }
3164 /**EXTENDED (rw) register accessor: No Description.
3165
3166You can [`read`](crate::Reg::read) this register and get [`extended::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`extended::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
3167
3168For information about available fields see [`mod@extended`] module*/
3169 pub type EXTENDED = crate::Reg<extended::EXTENDED_SPEC>;
3170 ///No Description.
3171 pub mod extended {
3172 ///Register `EXTENDED` reader
3173 pub type R = crate::R<EXTENDED_SPEC>;
3174 ///Register `EXTENDED` writer
3175 pub type W = crate::W<EXTENDED_SPEC>;
3176 ///Field `SELFPRGEN` reader - Self Programming enable
3177 pub type SELFPRGEN_R = crate::BitReader;
3178 ///Field `SELFPRGEN` writer - Self Programming enable
3179 pub type SELFPRGEN_W<'a, REG> = crate::BitWriter<'a, REG>;
3180 impl R {
3181 ///Bit 0 - Self Programming enable
3182 #[inline(always)]
3183 pub fn selfprgen(&self) -> SELFPRGEN_R {
3184 SELFPRGEN_R::new((self.bits & 1) != 0)
3185 }
3186 }
3187 impl W {
3188 ///Bit 0 - Self Programming enable
3189 #[inline(always)]
3190 pub fn selfprgen(&mut self) -> SELFPRGEN_W<'_, EXTENDED_SPEC> {
3191 SELFPRGEN_W::new(self, 0)
3192 }
3193 }
3194 /**No Description.
3195
3196You can [`read`](crate::Reg::read) this register and get [`extended::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`extended::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
3197 pub struct EXTENDED_SPEC;
3198 impl crate::RegisterSpec for EXTENDED_SPEC {
3199 type Ux = u8;
3200 }
3201 ///`read()` method returns [`extended::R`](R) reader structure
3202 impl crate::Readable for EXTENDED_SPEC {}
3203 ///`write(|w| ..)` method takes [`extended::W`](W) writer structure
3204 impl crate::Writable for EXTENDED_SPEC {
3205 type Safety = crate::Unsafe;
3206 }
3207 ///`reset()` method sets EXTENDED to value 0
3208 impl crate::Resettable for EXTENDED_SPEC {}
3209 }
3210 /**HIGH (rw) register accessor: No Description.
3211
3212You can [`read`](crate::Reg::read) this register and get [`high::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`high::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
3213
3214For information about available fields see [`mod@high`] module*/
3215 pub type HIGH = crate::Reg<high::HIGH_SPEC>;
3216 ///No Description.
3217 pub mod high {
3218 ///Register `HIGH` reader
3219 pub type R = crate::R<HIGH_SPEC>;
3220 ///Register `HIGH` writer
3221 pub type W = crate::W<HIGH_SPEC>;
3222 /**Brown-out Detector trigger level
3223
3224Value on reset: 0*/
3225 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
3226 #[repr(u8)]
3227 pub enum BODLEVEL_A {
3228 ///4: Brown-out detection at VCC=4.3 V
3229 _4V3 = 4,
3230 ///5: Brown-out detection at VCC=2.7 V
3231 _2V7 = 5,
3232 ///6: Brown-out detection at VCC=1.8 V
3233 _1V8 = 6,
3234 ///7: Brown-out detection disabled
3235 DISABLED = 7,
3236 }
3237 impl From<BODLEVEL_A> for u8 {
3238 #[inline(always)]
3239 fn from(variant: BODLEVEL_A) -> Self {
3240 variant as _
3241 }
3242 }
3243 impl crate::FieldSpec for BODLEVEL_A {
3244 type Ux = u8;
3245 }
3246 impl crate::IsEnum for BODLEVEL_A {}
3247 ///Field `BODLEVEL` reader - Brown-out Detector trigger level
3248 pub type BODLEVEL_R = crate::FieldReader<BODLEVEL_A>;
3249 impl BODLEVEL_R {
3250 ///Get enumerated values variant
3251 #[inline(always)]
3252 pub const fn variant(&self) -> Option<BODLEVEL_A> {
3253 match self.bits {
3254 4 => Some(BODLEVEL_A::_4V3),
3255 5 => Some(BODLEVEL_A::_2V7),
3256 6 => Some(BODLEVEL_A::_1V8),
3257 7 => Some(BODLEVEL_A::DISABLED),
3258 _ => None,
3259 }
3260 }
3261 ///Brown-out detection at VCC=4.3 V
3262 #[inline(always)]
3263 pub fn is_4v3(&self) -> bool {
3264 *self == BODLEVEL_A::_4V3
3265 }
3266 ///Brown-out detection at VCC=2.7 V
3267 #[inline(always)]
3268 pub fn is_2v7(&self) -> bool {
3269 *self == BODLEVEL_A::_2V7
3270 }
3271 ///Brown-out detection at VCC=1.8 V
3272 #[inline(always)]
3273 pub fn is_1v8(&self) -> bool {
3274 *self == BODLEVEL_A::_1V8
3275 }
3276 ///Brown-out detection disabled
3277 #[inline(always)]
3278 pub fn is_disabled(&self) -> bool {
3279 *self == BODLEVEL_A::DISABLED
3280 }
3281 }
3282 ///Field `BODLEVEL` writer - Brown-out Detector trigger level
3283 pub type BODLEVEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3, BODLEVEL_A>;
3284 impl<'a, REG> BODLEVEL_W<'a, REG>
3285 where
3286 REG: crate::Writable + crate::RegisterSpec,
3287 REG::Ux: From<u8>,
3288 {
3289 ///Brown-out detection at VCC=4.3 V
3290 #[inline(always)]
3291 pub fn _4v3(self) -> &'a mut crate::W<REG> {
3292 self.variant(BODLEVEL_A::_4V3)
3293 }
3294 ///Brown-out detection at VCC=2.7 V
3295 #[inline(always)]
3296 pub fn _2v7(self) -> &'a mut crate::W<REG> {
3297 self.variant(BODLEVEL_A::_2V7)
3298 }
3299 ///Brown-out detection at VCC=1.8 V
3300 #[inline(always)]
3301 pub fn _1v8(self) -> &'a mut crate::W<REG> {
3302 self.variant(BODLEVEL_A::_1V8)
3303 }
3304 ///Brown-out detection disabled
3305 #[inline(always)]
3306 pub fn disabled(self) -> &'a mut crate::W<REG> {
3307 self.variant(BODLEVEL_A::DISABLED)
3308 }
3309 }
3310 ///Field `EESAVE` reader - Preserve EEPROM through the Chip Erase cycle
3311 pub type EESAVE_R = crate::BitReader;
3312 ///Field `EESAVE` writer - Preserve EEPROM through the Chip Erase cycle
3313 pub type EESAVE_W<'a, REG> = crate::BitWriter<'a, REG>;
3314 ///Field `WDTON` reader - Watch-dog Timer always on
3315 pub type WDTON_R = crate::BitReader;
3316 ///Field `WDTON` writer - Watch-dog Timer always on
3317 pub type WDTON_W<'a, REG> = crate::BitWriter<'a, REG>;
3318 ///Field `SPIEN` reader - Serial program downloading (SPI) enabled
3319 pub type SPIEN_R = crate::BitReader;
3320 ///Field `SPIEN` writer - Serial program downloading (SPI) enabled
3321 pub type SPIEN_W<'a, REG> = crate::BitWriter<'a, REG>;
3322 ///Field `DWEN` reader - Debug Wire enable
3323 pub type DWEN_R = crate::BitReader;
3324 ///Field `DWEN` writer - Debug Wire enable
3325 pub type DWEN_W<'a, REG> = crate::BitWriter<'a, REG>;
3326 ///Field `RSTDISBL` reader - Reset Disabled (Enable PB5 as i/o pin)
3327 pub type RSTDISBL_R = crate::BitReader;
3328 ///Field `RSTDISBL` writer - Reset Disabled (Enable PB5 as i/o pin)
3329 pub type RSTDISBL_W<'a, REG> = crate::BitWriter<'a, REG>;
3330 impl R {
3331 ///Bits 0:2 - Brown-out Detector trigger level
3332 #[inline(always)]
3333 pub fn bodlevel(&self) -> BODLEVEL_R {
3334 BODLEVEL_R::new(self.bits & 7)
3335 }
3336 ///Bit 3 - Preserve EEPROM through the Chip Erase cycle
3337 #[inline(always)]
3338 pub fn eesave(&self) -> EESAVE_R {
3339 EESAVE_R::new(((self.bits >> 3) & 1) != 0)
3340 }
3341 ///Bit 4 - Watch-dog Timer always on
3342 #[inline(always)]
3343 pub fn wdton(&self) -> WDTON_R {
3344 WDTON_R::new(((self.bits >> 4) & 1) != 0)
3345 }
3346 ///Bit 5 - Serial program downloading (SPI) enabled
3347 #[inline(always)]
3348 pub fn spien(&self) -> SPIEN_R {
3349 SPIEN_R::new(((self.bits >> 5) & 1) != 0)
3350 }
3351 ///Bit 6 - Debug Wire enable
3352 #[inline(always)]
3353 pub fn dwen(&self) -> DWEN_R {
3354 DWEN_R::new(((self.bits >> 6) & 1) != 0)
3355 }
3356 ///Bit 7 - Reset Disabled (Enable PB5 as i/o pin)
3357 #[inline(always)]
3358 pub fn rstdisbl(&self) -> RSTDISBL_R {
3359 RSTDISBL_R::new(((self.bits >> 7) & 1) != 0)
3360 }
3361 }
3362 impl W {
3363 ///Bits 0:2 - Brown-out Detector trigger level
3364 #[inline(always)]
3365 pub fn bodlevel(&mut self) -> BODLEVEL_W<'_, HIGH_SPEC> {
3366 BODLEVEL_W::new(self, 0)
3367 }
3368 ///Bit 3 - Preserve EEPROM through the Chip Erase cycle
3369 #[inline(always)]
3370 pub fn eesave(&mut self) -> EESAVE_W<'_, HIGH_SPEC> {
3371 EESAVE_W::new(self, 3)
3372 }
3373 ///Bit 4 - Watch-dog Timer always on
3374 #[inline(always)]
3375 pub fn wdton(&mut self) -> WDTON_W<'_, HIGH_SPEC> {
3376 WDTON_W::new(self, 4)
3377 }
3378 ///Bit 5 - Serial program downloading (SPI) enabled
3379 #[inline(always)]
3380 pub fn spien(&mut self) -> SPIEN_W<'_, HIGH_SPEC> {
3381 SPIEN_W::new(self, 5)
3382 }
3383 ///Bit 6 - Debug Wire enable
3384 #[inline(always)]
3385 pub fn dwen(&mut self) -> DWEN_W<'_, HIGH_SPEC> {
3386 DWEN_W::new(self, 6)
3387 }
3388 ///Bit 7 - Reset Disabled (Enable PB5 as i/o pin)
3389 #[inline(always)]
3390 pub fn rstdisbl(&mut self) -> RSTDISBL_W<'_, HIGH_SPEC> {
3391 RSTDISBL_W::new(self, 7)
3392 }
3393 }
3394 /**No Description.
3395
3396You can [`read`](crate::Reg::read) this register and get [`high::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`high::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
3397 pub struct HIGH_SPEC;
3398 impl crate::RegisterSpec for HIGH_SPEC {
3399 type Ux = u8;
3400 }
3401 ///`read()` method returns [`high::R`](R) reader structure
3402 impl crate::Readable for HIGH_SPEC {}
3403 ///`write(|w| ..)` method takes [`high::W`](W) writer structure
3404 impl crate::Writable for HIGH_SPEC {
3405 type Safety = crate::Unsafe;
3406 }
3407 ///`reset()` method sets HIGH to value 0
3408 impl crate::Resettable for HIGH_SPEC {}
3409 }
3410 /**LOW (rw) register accessor: No Description.
3411
3412You can [`read`](crate::Reg::read) this register and get [`low::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`low::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
3413
3414For information about available fields see [`mod@low`] module*/
3415 pub type LOW = crate::Reg<low::LOW_SPEC>;
3416 ///No Description.
3417 pub mod low {
3418 ///Register `LOW` reader
3419 pub type R = crate::R<LOW_SPEC>;
3420 ///Register `LOW` writer
3421 pub type W = crate::W<LOW_SPEC>;
3422 /**Select Clock source
3423
3424Value on reset: 0*/
3425 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
3426 #[repr(u8)]
3427 pub enum SUT_CKSEL_A {
3428 ///0: Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms
3429 EXTCLK_6CK_14CK_0MS = 0,
3430 ///1: PLL Clock; Start-up time PWRDWN/RESET: 1K CK/14 CK + 4 ms
3431 PLLCLK_1KCK_14CK_4MS = 1,
3432 ///2: Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms
3433 INTRCOSC_8MHZ_6CK_14CK_0MS = 2,
3434 ///3: ATtiny15 Comp: Int. RC Osc. 6.4 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 64 ms
3435 INTRCOSC_6MHZ4_6CK_14CK_64MS = 3,
3436 ///4: WD. Osc. 128 kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms
3437 WDOSC_128KHZ_6CK_14CK_0MS = 4,
3438 ///6: Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 0 ms
3439 EXTLOFXTAL_1KCK_14CK_0MS = 6,
3440 ///8: Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms
3441 EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_4MS1 = 8,
3442 ///9: Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms
3443 EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_65MS = 9,
3444 ///10: Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms
3445 EXTXOSC_0MHZ9_3MHZ_258CK_14CK_4MS1 = 10,
3446 ///11: Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms
3447 EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_65MS = 11,
3448 ///12: Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms
3449 EXTXOSC_3MHZ_8MHZ_258CK_14CK_4MS1 = 12,
3450 ///13: Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms
3451 EXTXOSC_3MHZ_8MHZ_1KCK_14CK_65MS = 13,
3452 ///14: Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms
3453 EXTXOSC_8MHZ_XX_258CK_14CK_4MS1 = 14,
3454 ///15: Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms
3455 EXTXOSC_8MHZ_XX_1KCK_14CK_65MS = 15,
3456 ///16: Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms
3457 EXTCLK_6CK_14CK_4MS1 = 16,
3458 ///17: PLL Clock; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4 ms
3459 PLLCLK_16KCK_14CK_4MS = 17,
3460 ///18: Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4 ms
3461 INTRCOSC_8MHZ_6CK_14CK_4MS = 18,
3462 ///20: WD. Osc. 128 kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4 ms
3463 WDOSC_128KHZ_6CK_14CK_4MS = 20,
3464 ///22: Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 4 ms
3465 EXTLOFXTAL_1KCK_14CK_4MS = 22,
3466 ///24: Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms
3467 EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_65MS = 24,
3468 ///25: Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms
3469 EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_0MS = 25,
3470 ///26: Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms
3471 EXTXOSC_0MHZ9_3MHZ_258CK_14CK_65MS = 26,
3472 ///27: Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms
3473 EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_0MS = 27,
3474 ///28: Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms
3475 EXTXOSC_3MHZ_8MHZ_258CK_14CK_65MS = 28,
3476 ///29: Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms
3477 EXTXOSC_3MHZ_8MHZ_16KCK_14CK_0MS = 29,
3478 ///30: Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms
3479 EXTXOSC_8MHZ_XX_258CK_14CK_65MS = 30,
3480 ///31: Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms
3481 EXTXOSC_8MHZ_XX_16KCK_14CK_0MS = 31,
3482 ///32: Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms
3483 EXTCLK_6CK_14CK_65MS = 32,
3484 ///33: PLL Clock; Start-up time PWRDWN/RESET: 1K CK/14 CK + 64 ms
3485 PLLCLK_1KCK_14CK_64MS = 33,
3486 ///34: Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 64 ms
3487 INTRCOSC_8MHZ_6CK_14CK_64MS = 34,
3488 ///35: ATtiny15 Comp: Int. RC Osc. 6.4 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4 ms
3489 INTRCOSC_6MHZ4_6CK_14CK_4MS = 35,
3490 ///36: WD. Osc. 128 kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 64 ms
3491 WDOSC_128KHZ_6CK_14CK_64MS = 36,
3492 ///38: Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 64 ms
3493 EXTLOFXTAL_32KCK_14CK_64MS = 38,
3494 ///40: Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms
3495 EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_0MS = 40,
3496 ///41: Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms
3497 EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_4MS1 = 41,
3498 ///42: Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms
3499 EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_0MS = 42,
3500 ///43: Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms
3501 EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_4MS1 = 43,
3502 ///44: Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms
3503 EXTXOSC_3MHZ_8MHZ_1KCK_14CK_0MS = 44,
3504 ///45: Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms
3505 EXTXOSC_3MHZ_8MHZ_16KCK_14CK_4MS1 = 45,
3506 ///46: Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms
3507 EXTXOSC_8MHZ_XX_1KCK_14CK_0MS = 46,
3508 ///47: Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms
3509 EXTXOSC_8MHZ_XX_16KCK_14CK_4MS1 = 47,
3510 ///49: PLL Clock; Start-up time PWRDWN/RESET: 16K CK/14 CK + 64 ms
3511 PLLCLK_16KCK_14CK_64MS = 49,
3512 ///51: ATtiny15 Comp: Int. RC Osc. 6.4 MHz; Start-up time PWRDWN/RESET: 1 CK/14 CK + 0 ms
3513 INTRCOSC_6MHZ4_1CK_14CK_0MS = 51,
3514 ///56: Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms
3515 EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_4MS1 = 56,
3516 ///57: Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms
3517 EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_65MS = 57,
3518 ///58: Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms
3519 EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_4MS1 = 58,
3520 ///59: Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms
3521 EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_65MS = 59,
3522 ///60: Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms
3523 EXTXOSC_3MHZ_8MHZ_1KCK_14CK_4MS1 = 60,
3524 ///61: Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms
3525 EXTXOSC_3MHZ_8MHZ_16KCK_14CK_65MS = 61,
3526 ///62: Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms
3527 EXTXOSC_8MHZ_XX_1KCK_14CK_4MS1 = 62,
3528 ///63: Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms
3529 EXTXOSC_8MHZ_XX_16KCK_14CK_65MS = 63,
3530 }
3531 impl From<SUT_CKSEL_A> for u8 {
3532 #[inline(always)]
3533 fn from(variant: SUT_CKSEL_A) -> Self {
3534 variant as _
3535 }
3536 }
3537 impl crate::FieldSpec for SUT_CKSEL_A {
3538 type Ux = u8;
3539 }
3540 impl crate::IsEnum for SUT_CKSEL_A {}
3541 ///Field `SUT_CKSEL` reader - Select Clock source
3542 pub type SUT_CKSEL_R = crate::FieldReader<SUT_CKSEL_A>;
3543 impl SUT_CKSEL_R {
3544 ///Get enumerated values variant
3545 #[inline(always)]
3546 pub const fn variant(&self) -> Option<SUT_CKSEL_A> {
3547 match self.bits {
3548 0 => Some(SUT_CKSEL_A::EXTCLK_6CK_14CK_0MS),
3549 1 => Some(SUT_CKSEL_A::PLLCLK_1KCK_14CK_4MS),
3550 2 => Some(SUT_CKSEL_A::INTRCOSC_8MHZ_6CK_14CK_0MS),
3551 3 => Some(SUT_CKSEL_A::INTRCOSC_6MHZ4_6CK_14CK_64MS),
3552 4 => Some(SUT_CKSEL_A::WDOSC_128KHZ_6CK_14CK_0MS),
3553 6 => Some(SUT_CKSEL_A::EXTLOFXTAL_1KCK_14CK_0MS),
3554 8 => Some(SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_4MS1),
3555 9 => Some(SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_65MS),
3556 10 => Some(SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_258CK_14CK_4MS1),
3557 11 => Some(SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_65MS),
3558 12 => Some(SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_258CK_14CK_4MS1),
3559 13 => Some(SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_1KCK_14CK_65MS),
3560 14 => Some(SUT_CKSEL_A::EXTXOSC_8MHZ_XX_258CK_14CK_4MS1),
3561 15 => Some(SUT_CKSEL_A::EXTXOSC_8MHZ_XX_1KCK_14CK_65MS),
3562 16 => Some(SUT_CKSEL_A::EXTCLK_6CK_14CK_4MS1),
3563 17 => Some(SUT_CKSEL_A::PLLCLK_16KCK_14CK_4MS),
3564 18 => Some(SUT_CKSEL_A::INTRCOSC_8MHZ_6CK_14CK_4MS),
3565 20 => Some(SUT_CKSEL_A::WDOSC_128KHZ_6CK_14CK_4MS),
3566 22 => Some(SUT_CKSEL_A::EXTLOFXTAL_1KCK_14CK_4MS),
3567 24 => Some(SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_65MS),
3568 25 => Some(SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_0MS),
3569 26 => Some(SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_258CK_14CK_65MS),
3570 27 => Some(SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_0MS),
3571 28 => Some(SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_258CK_14CK_65MS),
3572 29 => Some(SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_16KCK_14CK_0MS),
3573 30 => Some(SUT_CKSEL_A::EXTXOSC_8MHZ_XX_258CK_14CK_65MS),
3574 31 => Some(SUT_CKSEL_A::EXTXOSC_8MHZ_XX_16KCK_14CK_0MS),
3575 32 => Some(SUT_CKSEL_A::EXTCLK_6CK_14CK_65MS),
3576 33 => Some(SUT_CKSEL_A::PLLCLK_1KCK_14CK_64MS),
3577 34 => Some(SUT_CKSEL_A::INTRCOSC_8MHZ_6CK_14CK_64MS),
3578 35 => Some(SUT_CKSEL_A::INTRCOSC_6MHZ4_6CK_14CK_4MS),
3579 36 => Some(SUT_CKSEL_A::WDOSC_128KHZ_6CK_14CK_64MS),
3580 38 => Some(SUT_CKSEL_A::EXTLOFXTAL_32KCK_14CK_64MS),
3581 40 => Some(SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_0MS),
3582 41 => Some(SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_4MS1),
3583 42 => Some(SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_0MS),
3584 43 => Some(SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_4MS1),
3585 44 => Some(SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_1KCK_14CK_0MS),
3586 45 => Some(SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_16KCK_14CK_4MS1),
3587 46 => Some(SUT_CKSEL_A::EXTXOSC_8MHZ_XX_1KCK_14CK_0MS),
3588 47 => Some(SUT_CKSEL_A::EXTXOSC_8MHZ_XX_16KCK_14CK_4MS1),
3589 49 => Some(SUT_CKSEL_A::PLLCLK_16KCK_14CK_64MS),
3590 51 => Some(SUT_CKSEL_A::INTRCOSC_6MHZ4_1CK_14CK_0MS),
3591 56 => Some(SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_4MS1),
3592 57 => Some(SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_65MS),
3593 58 => Some(SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_4MS1),
3594 59 => Some(SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_65MS),
3595 60 => Some(SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_1KCK_14CK_4MS1),
3596 61 => Some(SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_16KCK_14CK_65MS),
3597 62 => Some(SUT_CKSEL_A::EXTXOSC_8MHZ_XX_1KCK_14CK_4MS1),
3598 63 => Some(SUT_CKSEL_A::EXTXOSC_8MHZ_XX_16KCK_14CK_65MS),
3599 _ => None,
3600 }
3601 }
3602 ///Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms
3603 #[inline(always)]
3604 pub fn is_extclk_6ck_14ck_0ms(&self) -> bool {
3605 *self == SUT_CKSEL_A::EXTCLK_6CK_14CK_0MS
3606 }
3607 ///PLL Clock; Start-up time PWRDWN/RESET: 1K CK/14 CK + 4 ms
3608 #[inline(always)]
3609 pub fn is_pllclk_1kck_14ck_4ms(&self) -> bool {
3610 *self == SUT_CKSEL_A::PLLCLK_1KCK_14CK_4MS
3611 }
3612 ///Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms
3613 #[inline(always)]
3614 pub fn is_intrcosc_8mhz_6ck_14ck_0ms(&self) -> bool {
3615 *self == SUT_CKSEL_A::INTRCOSC_8MHZ_6CK_14CK_0MS
3616 }
3617 ///ATtiny15 Comp: Int. RC Osc. 6.4 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 64 ms
3618 #[inline(always)]
3619 pub fn is_intrcosc_6mhz4_6ck_14ck_64ms(&self) -> bool {
3620 *self == SUT_CKSEL_A::INTRCOSC_6MHZ4_6CK_14CK_64MS
3621 }
3622 ///WD. Osc. 128 kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms
3623 #[inline(always)]
3624 pub fn is_wdosc_128khz_6ck_14ck_0ms(&self) -> bool {
3625 *self == SUT_CKSEL_A::WDOSC_128KHZ_6CK_14CK_0MS
3626 }
3627 ///Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 0 ms
3628 #[inline(always)]
3629 pub fn is_extlofxtal_1kck_14ck_0ms(&self) -> bool {
3630 *self == SUT_CKSEL_A::EXTLOFXTAL_1KCK_14CK_0MS
3631 }
3632 ///Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms
3633 #[inline(always)]
3634 pub fn is_extxosc_0mhz4_0mhz9_258ck_14ck_4ms1(&self) -> bool {
3635 *self == SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_4MS1
3636 }
3637 ///Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms
3638 #[inline(always)]
3639 pub fn is_extxosc_0mhz4_0mhz9_1kck_14ck_65ms(&self) -> bool {
3640 *self == SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_65MS
3641 }
3642 ///Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms
3643 #[inline(always)]
3644 pub fn is_extxosc_0mhz9_3mhz_258ck_14ck_4ms1(&self) -> bool {
3645 *self == SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_258CK_14CK_4MS1
3646 }
3647 ///Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms
3648 #[inline(always)]
3649 pub fn is_extxosc_0mhz9_3mhz_1kck_14ck_65ms(&self) -> bool {
3650 *self == SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_65MS
3651 }
3652 ///Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms
3653 #[inline(always)]
3654 pub fn is_extxosc_3mhz_8mhz_258ck_14ck_4ms1(&self) -> bool {
3655 *self == SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_258CK_14CK_4MS1
3656 }
3657 ///Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms
3658 #[inline(always)]
3659 pub fn is_extxosc_3mhz_8mhz_1kck_14ck_65ms(&self) -> bool {
3660 *self == SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_1KCK_14CK_65MS
3661 }
3662 ///Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms
3663 #[inline(always)]
3664 pub fn is_extxosc_8mhz_xx_258ck_14ck_4ms1(&self) -> bool {
3665 *self == SUT_CKSEL_A::EXTXOSC_8MHZ_XX_258CK_14CK_4MS1
3666 }
3667 ///Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms
3668 #[inline(always)]
3669 pub fn is_extxosc_8mhz_xx_1kck_14ck_65ms(&self) -> bool {
3670 *self == SUT_CKSEL_A::EXTXOSC_8MHZ_XX_1KCK_14CK_65MS
3671 }
3672 ///Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms
3673 #[inline(always)]
3674 pub fn is_extclk_6ck_14ck_4ms1(&self) -> bool {
3675 *self == SUT_CKSEL_A::EXTCLK_6CK_14CK_4MS1
3676 }
3677 ///PLL Clock; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4 ms
3678 #[inline(always)]
3679 pub fn is_pllclk_16kck_14ck_4ms(&self) -> bool {
3680 *self == SUT_CKSEL_A::PLLCLK_16KCK_14CK_4MS
3681 }
3682 ///Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4 ms
3683 #[inline(always)]
3684 pub fn is_intrcosc_8mhz_6ck_14ck_4ms(&self) -> bool {
3685 *self == SUT_CKSEL_A::INTRCOSC_8MHZ_6CK_14CK_4MS
3686 }
3687 ///WD. Osc. 128 kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4 ms
3688 #[inline(always)]
3689 pub fn is_wdosc_128khz_6ck_14ck_4ms(&self) -> bool {
3690 *self == SUT_CKSEL_A::WDOSC_128KHZ_6CK_14CK_4MS
3691 }
3692 ///Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 4 ms
3693 #[inline(always)]
3694 pub fn is_extlofxtal_1kck_14ck_4ms(&self) -> bool {
3695 *self == SUT_CKSEL_A::EXTLOFXTAL_1KCK_14CK_4MS
3696 }
3697 ///Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms
3698 #[inline(always)]
3699 pub fn is_extxosc_0mhz4_0mhz9_258ck_14ck_65ms(&self) -> bool {
3700 *self == SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_65MS
3701 }
3702 ///Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms
3703 #[inline(always)]
3704 pub fn is_extxosc_0mhz4_0mhz9_16kck_14ck_0ms(&self) -> bool {
3705 *self == SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_0MS
3706 }
3707 ///Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms
3708 #[inline(always)]
3709 pub fn is_extxosc_0mhz9_3mhz_258ck_14ck_65ms(&self) -> bool {
3710 *self == SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_258CK_14CK_65MS
3711 }
3712 ///Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms
3713 #[inline(always)]
3714 pub fn is_extxosc_0mhz9_3mhz_16kck_14ck_0ms(&self) -> bool {
3715 *self == SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_0MS
3716 }
3717 ///Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms
3718 #[inline(always)]
3719 pub fn is_extxosc_3mhz_8mhz_258ck_14ck_65ms(&self) -> bool {
3720 *self == SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_258CK_14CK_65MS
3721 }
3722 ///Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms
3723 #[inline(always)]
3724 pub fn is_extxosc_3mhz_8mhz_16kck_14ck_0ms(&self) -> bool {
3725 *self == SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_16KCK_14CK_0MS
3726 }
3727 ///Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms
3728 #[inline(always)]
3729 pub fn is_extxosc_8mhz_xx_258ck_14ck_65ms(&self) -> bool {
3730 *self == SUT_CKSEL_A::EXTXOSC_8MHZ_XX_258CK_14CK_65MS
3731 }
3732 ///Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms
3733 #[inline(always)]
3734 pub fn is_extxosc_8mhz_xx_16kck_14ck_0ms(&self) -> bool {
3735 *self == SUT_CKSEL_A::EXTXOSC_8MHZ_XX_16KCK_14CK_0MS
3736 }
3737 ///Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms
3738 #[inline(always)]
3739 pub fn is_extclk_6ck_14ck_65ms(&self) -> bool {
3740 *self == SUT_CKSEL_A::EXTCLK_6CK_14CK_65MS
3741 }
3742 ///PLL Clock; Start-up time PWRDWN/RESET: 1K CK/14 CK + 64 ms
3743 #[inline(always)]
3744 pub fn is_pllclk_1kck_14ck_64ms(&self) -> bool {
3745 *self == SUT_CKSEL_A::PLLCLK_1KCK_14CK_64MS
3746 }
3747 ///Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 64 ms
3748 #[inline(always)]
3749 pub fn is_intrcosc_8mhz_6ck_14ck_64ms(&self) -> bool {
3750 *self == SUT_CKSEL_A::INTRCOSC_8MHZ_6CK_14CK_64MS
3751 }
3752 ///ATtiny15 Comp: Int. RC Osc. 6.4 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4 ms
3753 #[inline(always)]
3754 pub fn is_intrcosc_6mhz4_6ck_14ck_4ms(&self) -> bool {
3755 *self == SUT_CKSEL_A::INTRCOSC_6MHZ4_6CK_14CK_4MS
3756 }
3757 ///WD. Osc. 128 kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 64 ms
3758 #[inline(always)]
3759 pub fn is_wdosc_128khz_6ck_14ck_64ms(&self) -> bool {
3760 *self == SUT_CKSEL_A::WDOSC_128KHZ_6CK_14CK_64MS
3761 }
3762 ///Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 64 ms
3763 #[inline(always)]
3764 pub fn is_extlofxtal_32kck_14ck_64ms(&self) -> bool {
3765 *self == SUT_CKSEL_A::EXTLOFXTAL_32KCK_14CK_64MS
3766 }
3767 ///Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms
3768 #[inline(always)]
3769 pub fn is_extxosc_0mhz4_0mhz9_1kck_14ck_0ms(&self) -> bool {
3770 *self == SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_0MS
3771 }
3772 ///Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms
3773 #[inline(always)]
3774 pub fn is_extxosc_0mhz4_0mhz9_16kck_14ck_4ms1(&self) -> bool {
3775 *self == SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_4MS1
3776 }
3777 ///Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms
3778 #[inline(always)]
3779 pub fn is_extxosc_0mhz9_3mhz_1kck_14ck_0ms(&self) -> bool {
3780 *self == SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_0MS
3781 }
3782 ///Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms
3783 #[inline(always)]
3784 pub fn is_extxosc_0mhz9_3mhz_16kck_14ck_4ms1(&self) -> bool {
3785 *self == SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_4MS1
3786 }
3787 ///Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms
3788 #[inline(always)]
3789 pub fn is_extxosc_3mhz_8mhz_1kck_14ck_0ms(&self) -> bool {
3790 *self == SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_1KCK_14CK_0MS
3791 }
3792 ///Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms
3793 #[inline(always)]
3794 pub fn is_extxosc_3mhz_8mhz_16kck_14ck_4ms1(&self) -> bool {
3795 *self == SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_16KCK_14CK_4MS1
3796 }
3797 ///Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms
3798 #[inline(always)]
3799 pub fn is_extxosc_8mhz_xx_1kck_14ck_0ms(&self) -> bool {
3800 *self == SUT_CKSEL_A::EXTXOSC_8MHZ_XX_1KCK_14CK_0MS
3801 }
3802 ///Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms
3803 #[inline(always)]
3804 pub fn is_extxosc_8mhz_xx_16kck_14ck_4ms1(&self) -> bool {
3805 *self == SUT_CKSEL_A::EXTXOSC_8MHZ_XX_16KCK_14CK_4MS1
3806 }
3807 ///PLL Clock; Start-up time PWRDWN/RESET: 16K CK/14 CK + 64 ms
3808 #[inline(always)]
3809 pub fn is_pllclk_16kck_14ck_64ms(&self) -> bool {
3810 *self == SUT_CKSEL_A::PLLCLK_16KCK_14CK_64MS
3811 }
3812 ///ATtiny15 Comp: Int. RC Osc. 6.4 MHz; Start-up time PWRDWN/RESET: 1 CK/14 CK + 0 ms
3813 #[inline(always)]
3814 pub fn is_intrcosc_6mhz4_1ck_14ck_0ms(&self) -> bool {
3815 *self == SUT_CKSEL_A::INTRCOSC_6MHZ4_1CK_14CK_0MS
3816 }
3817 ///Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms
3818 #[inline(always)]
3819 pub fn is_extxosc_0mhz4_0mhz9_1kck_14ck_4ms1(&self) -> bool {
3820 *self == SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_4MS1
3821 }
3822 ///Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms
3823 #[inline(always)]
3824 pub fn is_extxosc_0mhz4_0mhz9_16kck_14ck_65ms(&self) -> bool {
3825 *self == SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_65MS
3826 }
3827 ///Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms
3828 #[inline(always)]
3829 pub fn is_extxosc_0mhz9_3mhz_1kck_14ck_4ms1(&self) -> bool {
3830 *self == SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_4MS1
3831 }
3832 ///Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms
3833 #[inline(always)]
3834 pub fn is_extxosc_0mhz9_3mhz_16kck_14ck_65ms(&self) -> bool {
3835 *self == SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_65MS
3836 }
3837 ///Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms
3838 #[inline(always)]
3839 pub fn is_extxosc_3mhz_8mhz_1kck_14ck_4ms1(&self) -> bool {
3840 *self == SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_1KCK_14CK_4MS1
3841 }
3842 ///Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms
3843 #[inline(always)]
3844 pub fn is_extxosc_3mhz_8mhz_16kck_14ck_65ms(&self) -> bool {
3845 *self == SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_16KCK_14CK_65MS
3846 }
3847 ///Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms
3848 #[inline(always)]
3849 pub fn is_extxosc_8mhz_xx_1kck_14ck_4ms1(&self) -> bool {
3850 *self == SUT_CKSEL_A::EXTXOSC_8MHZ_XX_1KCK_14CK_4MS1
3851 }
3852 ///Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms
3853 #[inline(always)]
3854 pub fn is_extxosc_8mhz_xx_16kck_14ck_65ms(&self) -> bool {
3855 *self == SUT_CKSEL_A::EXTXOSC_8MHZ_XX_16KCK_14CK_65MS
3856 }
3857 }
3858 ///Field `SUT_CKSEL` writer - Select Clock source
3859 pub type SUT_CKSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6, SUT_CKSEL_A>;
3860 impl<'a, REG> SUT_CKSEL_W<'a, REG>
3861 where
3862 REG: crate::Writable + crate::RegisterSpec,
3863 REG::Ux: From<u8>,
3864 {
3865 ///Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms
3866 #[inline(always)]
3867 pub fn extclk_6ck_14ck_0ms(self) -> &'a mut crate::W<REG> {
3868 self.variant(SUT_CKSEL_A::EXTCLK_6CK_14CK_0MS)
3869 }
3870 ///PLL Clock; Start-up time PWRDWN/RESET: 1K CK/14 CK + 4 ms
3871 #[inline(always)]
3872 pub fn pllclk_1kck_14ck_4ms(self) -> &'a mut crate::W<REG> {
3873 self.variant(SUT_CKSEL_A::PLLCLK_1KCK_14CK_4MS)
3874 }
3875 ///Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms
3876 #[inline(always)]
3877 pub fn intrcosc_8mhz_6ck_14ck_0ms(self) -> &'a mut crate::W<REG> {
3878 self.variant(SUT_CKSEL_A::INTRCOSC_8MHZ_6CK_14CK_0MS)
3879 }
3880 ///ATtiny15 Comp: Int. RC Osc. 6.4 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 64 ms
3881 #[inline(always)]
3882 pub fn intrcosc_6mhz4_6ck_14ck_64ms(self) -> &'a mut crate::W<REG> {
3883 self.variant(SUT_CKSEL_A::INTRCOSC_6MHZ4_6CK_14CK_64MS)
3884 }
3885 ///WD. Osc. 128 kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms
3886 #[inline(always)]
3887 pub fn wdosc_128khz_6ck_14ck_0ms(self) -> &'a mut crate::W<REG> {
3888 self.variant(SUT_CKSEL_A::WDOSC_128KHZ_6CK_14CK_0MS)
3889 }
3890 ///Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 0 ms
3891 #[inline(always)]
3892 pub fn extlofxtal_1kck_14ck_0ms(self) -> &'a mut crate::W<REG> {
3893 self.variant(SUT_CKSEL_A::EXTLOFXTAL_1KCK_14CK_0MS)
3894 }
3895 ///Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms
3896 #[inline(always)]
3897 pub fn extxosc_0mhz4_0mhz9_258ck_14ck_4ms1(self) -> &'a mut crate::W<REG> {
3898 self.variant(SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_4MS1)
3899 }
3900 ///Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms
3901 #[inline(always)]
3902 pub fn extxosc_0mhz4_0mhz9_1kck_14ck_65ms(self) -> &'a mut crate::W<REG> {
3903 self.variant(SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_65MS)
3904 }
3905 ///Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms
3906 #[inline(always)]
3907 pub fn extxosc_0mhz9_3mhz_258ck_14ck_4ms1(self) -> &'a mut crate::W<REG> {
3908 self.variant(SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_258CK_14CK_4MS1)
3909 }
3910 ///Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms
3911 #[inline(always)]
3912 pub fn extxosc_0mhz9_3mhz_1kck_14ck_65ms(self) -> &'a mut crate::W<REG> {
3913 self.variant(SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_65MS)
3914 }
3915 ///Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms
3916 #[inline(always)]
3917 pub fn extxosc_3mhz_8mhz_258ck_14ck_4ms1(self) -> &'a mut crate::W<REG> {
3918 self.variant(SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_258CK_14CK_4MS1)
3919 }
3920 ///Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms
3921 #[inline(always)]
3922 pub fn extxosc_3mhz_8mhz_1kck_14ck_65ms(self) -> &'a mut crate::W<REG> {
3923 self.variant(SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_1KCK_14CK_65MS)
3924 }
3925 ///Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms
3926 #[inline(always)]
3927 pub fn extxosc_8mhz_xx_258ck_14ck_4ms1(self) -> &'a mut crate::W<REG> {
3928 self.variant(SUT_CKSEL_A::EXTXOSC_8MHZ_XX_258CK_14CK_4MS1)
3929 }
3930 ///Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms
3931 #[inline(always)]
3932 pub fn extxosc_8mhz_xx_1kck_14ck_65ms(self) -> &'a mut crate::W<REG> {
3933 self.variant(SUT_CKSEL_A::EXTXOSC_8MHZ_XX_1KCK_14CK_65MS)
3934 }
3935 ///Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms
3936 #[inline(always)]
3937 pub fn extclk_6ck_14ck_4ms1(self) -> &'a mut crate::W<REG> {
3938 self.variant(SUT_CKSEL_A::EXTCLK_6CK_14CK_4MS1)
3939 }
3940 ///PLL Clock; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4 ms
3941 #[inline(always)]
3942 pub fn pllclk_16kck_14ck_4ms(self) -> &'a mut crate::W<REG> {
3943 self.variant(SUT_CKSEL_A::PLLCLK_16KCK_14CK_4MS)
3944 }
3945 ///Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4 ms
3946 #[inline(always)]
3947 pub fn intrcosc_8mhz_6ck_14ck_4ms(self) -> &'a mut crate::W<REG> {
3948 self.variant(SUT_CKSEL_A::INTRCOSC_8MHZ_6CK_14CK_4MS)
3949 }
3950 ///WD. Osc. 128 kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4 ms
3951 #[inline(always)]
3952 pub fn wdosc_128khz_6ck_14ck_4ms(self) -> &'a mut crate::W<REG> {
3953 self.variant(SUT_CKSEL_A::WDOSC_128KHZ_6CK_14CK_4MS)
3954 }
3955 ///Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 4 ms
3956 #[inline(always)]
3957 pub fn extlofxtal_1kck_14ck_4ms(self) -> &'a mut crate::W<REG> {
3958 self.variant(SUT_CKSEL_A::EXTLOFXTAL_1KCK_14CK_4MS)
3959 }
3960 ///Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms
3961 #[inline(always)]
3962 pub fn extxosc_0mhz4_0mhz9_258ck_14ck_65ms(self) -> &'a mut crate::W<REG> {
3963 self.variant(SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_65MS)
3964 }
3965 ///Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms
3966 #[inline(always)]
3967 pub fn extxosc_0mhz4_0mhz9_16kck_14ck_0ms(self) -> &'a mut crate::W<REG> {
3968 self.variant(SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_0MS)
3969 }
3970 ///Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms
3971 #[inline(always)]
3972 pub fn extxosc_0mhz9_3mhz_258ck_14ck_65ms(self) -> &'a mut crate::W<REG> {
3973 self.variant(SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_258CK_14CK_65MS)
3974 }
3975 ///Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms
3976 #[inline(always)]
3977 pub fn extxosc_0mhz9_3mhz_16kck_14ck_0ms(self) -> &'a mut crate::W<REG> {
3978 self.variant(SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_0MS)
3979 }
3980 ///Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms
3981 #[inline(always)]
3982 pub fn extxosc_3mhz_8mhz_258ck_14ck_65ms(self) -> &'a mut crate::W<REG> {
3983 self.variant(SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_258CK_14CK_65MS)
3984 }
3985 ///Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms
3986 #[inline(always)]
3987 pub fn extxosc_3mhz_8mhz_16kck_14ck_0ms(self) -> &'a mut crate::W<REG> {
3988 self.variant(SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_16KCK_14CK_0MS)
3989 }
3990 ///Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms
3991 #[inline(always)]
3992 pub fn extxosc_8mhz_xx_258ck_14ck_65ms(self) -> &'a mut crate::W<REG> {
3993 self.variant(SUT_CKSEL_A::EXTXOSC_8MHZ_XX_258CK_14CK_65MS)
3994 }
3995 ///Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms
3996 #[inline(always)]
3997 pub fn extxosc_8mhz_xx_16kck_14ck_0ms(self) -> &'a mut crate::W<REG> {
3998 self.variant(SUT_CKSEL_A::EXTXOSC_8MHZ_XX_16KCK_14CK_0MS)
3999 }
4000 ///Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms
4001 #[inline(always)]
4002 pub fn extclk_6ck_14ck_65ms(self) -> &'a mut crate::W<REG> {
4003 self.variant(SUT_CKSEL_A::EXTCLK_6CK_14CK_65MS)
4004 }
4005 ///PLL Clock; Start-up time PWRDWN/RESET: 1K CK/14 CK + 64 ms
4006 #[inline(always)]
4007 pub fn pllclk_1kck_14ck_64ms(self) -> &'a mut crate::W<REG> {
4008 self.variant(SUT_CKSEL_A::PLLCLK_1KCK_14CK_64MS)
4009 }
4010 ///Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 64 ms
4011 #[inline(always)]
4012 pub fn intrcosc_8mhz_6ck_14ck_64ms(self) -> &'a mut crate::W<REG> {
4013 self.variant(SUT_CKSEL_A::INTRCOSC_8MHZ_6CK_14CK_64MS)
4014 }
4015 ///ATtiny15 Comp: Int. RC Osc. 6.4 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4 ms
4016 #[inline(always)]
4017 pub fn intrcosc_6mhz4_6ck_14ck_4ms(self) -> &'a mut crate::W<REG> {
4018 self.variant(SUT_CKSEL_A::INTRCOSC_6MHZ4_6CK_14CK_4MS)
4019 }
4020 ///WD. Osc. 128 kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 64 ms
4021 #[inline(always)]
4022 pub fn wdosc_128khz_6ck_14ck_64ms(self) -> &'a mut crate::W<REG> {
4023 self.variant(SUT_CKSEL_A::WDOSC_128KHZ_6CK_14CK_64MS)
4024 }
4025 ///Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 64 ms
4026 #[inline(always)]
4027 pub fn extlofxtal_32kck_14ck_64ms(self) -> &'a mut crate::W<REG> {
4028 self.variant(SUT_CKSEL_A::EXTLOFXTAL_32KCK_14CK_64MS)
4029 }
4030 ///Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms
4031 #[inline(always)]
4032 pub fn extxosc_0mhz4_0mhz9_1kck_14ck_0ms(self) -> &'a mut crate::W<REG> {
4033 self.variant(SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_0MS)
4034 }
4035 ///Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms
4036 #[inline(always)]
4037 pub fn extxosc_0mhz4_0mhz9_16kck_14ck_4ms1(self) -> &'a mut crate::W<REG> {
4038 self.variant(SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_4MS1)
4039 }
4040 ///Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms
4041 #[inline(always)]
4042 pub fn extxosc_0mhz9_3mhz_1kck_14ck_0ms(self) -> &'a mut crate::W<REG> {
4043 self.variant(SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_0MS)
4044 }
4045 ///Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms
4046 #[inline(always)]
4047 pub fn extxosc_0mhz9_3mhz_16kck_14ck_4ms1(self) -> &'a mut crate::W<REG> {
4048 self.variant(SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_4MS1)
4049 }
4050 ///Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms
4051 #[inline(always)]
4052 pub fn extxosc_3mhz_8mhz_1kck_14ck_0ms(self) -> &'a mut crate::W<REG> {
4053 self.variant(SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_1KCK_14CK_0MS)
4054 }
4055 ///Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms
4056 #[inline(always)]
4057 pub fn extxosc_3mhz_8mhz_16kck_14ck_4ms1(self) -> &'a mut crate::W<REG> {
4058 self.variant(SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_16KCK_14CK_4MS1)
4059 }
4060 ///Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms
4061 #[inline(always)]
4062 pub fn extxosc_8mhz_xx_1kck_14ck_0ms(self) -> &'a mut crate::W<REG> {
4063 self.variant(SUT_CKSEL_A::EXTXOSC_8MHZ_XX_1KCK_14CK_0MS)
4064 }
4065 ///Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms
4066 #[inline(always)]
4067 pub fn extxosc_8mhz_xx_16kck_14ck_4ms1(self) -> &'a mut crate::W<REG> {
4068 self.variant(SUT_CKSEL_A::EXTXOSC_8MHZ_XX_16KCK_14CK_4MS1)
4069 }
4070 ///PLL Clock; Start-up time PWRDWN/RESET: 16K CK/14 CK + 64 ms
4071 #[inline(always)]
4072 pub fn pllclk_16kck_14ck_64ms(self) -> &'a mut crate::W<REG> {
4073 self.variant(SUT_CKSEL_A::PLLCLK_16KCK_14CK_64MS)
4074 }
4075 ///ATtiny15 Comp: Int. RC Osc. 6.4 MHz; Start-up time PWRDWN/RESET: 1 CK/14 CK + 0 ms
4076 #[inline(always)]
4077 pub fn intrcosc_6mhz4_1ck_14ck_0ms(self) -> &'a mut crate::W<REG> {
4078 self.variant(SUT_CKSEL_A::INTRCOSC_6MHZ4_1CK_14CK_0MS)
4079 }
4080 ///Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms
4081 #[inline(always)]
4082 pub fn extxosc_0mhz4_0mhz9_1kck_14ck_4ms1(self) -> &'a mut crate::W<REG> {
4083 self.variant(SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_4MS1)
4084 }
4085 ///Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms
4086 #[inline(always)]
4087 pub fn extxosc_0mhz4_0mhz9_16kck_14ck_65ms(self) -> &'a mut crate::W<REG> {
4088 self.variant(SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_65MS)
4089 }
4090 ///Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms
4091 #[inline(always)]
4092 pub fn extxosc_0mhz9_3mhz_1kck_14ck_4ms1(self) -> &'a mut crate::W<REG> {
4093 self.variant(SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_4MS1)
4094 }
4095 ///Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms
4096 #[inline(always)]
4097 pub fn extxosc_0mhz9_3mhz_16kck_14ck_65ms(self) -> &'a mut crate::W<REG> {
4098 self.variant(SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_65MS)
4099 }
4100 ///Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms
4101 #[inline(always)]
4102 pub fn extxosc_3mhz_8mhz_1kck_14ck_4ms1(self) -> &'a mut crate::W<REG> {
4103 self.variant(SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_1KCK_14CK_4MS1)
4104 }
4105 ///Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms
4106 #[inline(always)]
4107 pub fn extxosc_3mhz_8mhz_16kck_14ck_65ms(self) -> &'a mut crate::W<REG> {
4108 self.variant(SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_16KCK_14CK_65MS)
4109 }
4110 ///Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms
4111 #[inline(always)]
4112 pub fn extxosc_8mhz_xx_1kck_14ck_4ms1(self) -> &'a mut crate::W<REG> {
4113 self.variant(SUT_CKSEL_A::EXTXOSC_8MHZ_XX_1KCK_14CK_4MS1)
4114 }
4115 ///Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms
4116 #[inline(always)]
4117 pub fn extxosc_8mhz_xx_16kck_14ck_65ms(self) -> &'a mut crate::W<REG> {
4118 self.variant(SUT_CKSEL_A::EXTXOSC_8MHZ_XX_16KCK_14CK_65MS)
4119 }
4120 }
4121 ///Field `CKOUT` reader - Clock output on PORTB4
4122 pub type CKOUT_R = crate::BitReader;
4123 ///Field `CKOUT` writer - Clock output on PORTB4
4124 pub type CKOUT_W<'a, REG> = crate::BitWriter<'a, REG>;
4125 ///Field `CKDIV8` reader - Divide clock by 8 internally
4126 pub type CKDIV8_R = crate::BitReader;
4127 ///Field `CKDIV8` writer - Divide clock by 8 internally
4128 pub type CKDIV8_W<'a, REG> = crate::BitWriter<'a, REG>;
4129 impl R {
4130 ///Bits 0:5 - Select Clock source
4131 #[inline(always)]
4132 pub fn sut_cksel(&self) -> SUT_CKSEL_R {
4133 SUT_CKSEL_R::new(self.bits & 0x3f)
4134 }
4135 ///Bit 6 - Clock output on PORTB4
4136 #[inline(always)]
4137 pub fn ckout(&self) -> CKOUT_R {
4138 CKOUT_R::new(((self.bits >> 6) & 1) != 0)
4139 }
4140 ///Bit 7 - Divide clock by 8 internally
4141 #[inline(always)]
4142 pub fn ckdiv8(&self) -> CKDIV8_R {
4143 CKDIV8_R::new(((self.bits >> 7) & 1) != 0)
4144 }
4145 }
4146 impl W {
4147 ///Bits 0:5 - Select Clock source
4148 #[inline(always)]
4149 pub fn sut_cksel(&mut self) -> SUT_CKSEL_W<'_, LOW_SPEC> {
4150 SUT_CKSEL_W::new(self, 0)
4151 }
4152 ///Bit 6 - Clock output on PORTB4
4153 #[inline(always)]
4154 pub fn ckout(&mut self) -> CKOUT_W<'_, LOW_SPEC> {
4155 CKOUT_W::new(self, 6)
4156 }
4157 ///Bit 7 - Divide clock by 8 internally
4158 #[inline(always)]
4159 pub fn ckdiv8(&mut self) -> CKDIV8_W<'_, LOW_SPEC> {
4160 CKDIV8_W::new(self, 7)
4161 }
4162 }
4163 /**No Description.
4164
4165You can [`read`](crate::Reg::read) this register and get [`low::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`low::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
4166 pub struct LOW_SPEC;
4167 impl crate::RegisterSpec for LOW_SPEC {
4168 type Ux = u8;
4169 }
4170 ///`read()` method returns [`low::R`](R) reader structure
4171 impl crate::Readable for LOW_SPEC {}
4172 ///`write(|w| ..)` method takes [`low::W`](W) writer structure
4173 impl crate::Writable for LOW_SPEC {
4174 type Safety = crate::Unsafe;
4175 }
4176 ///`reset()` method sets LOW to value 0
4177 impl crate::Resettable for LOW_SPEC {}
4178 }
4179}
4180///Lockbits
4181pub type LOCKBIT = crate::Periph<lockbit::RegisterBlock, 0>;
4182impl core::fmt::Debug for LOCKBIT {
4183 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
4184 f.debug_struct("LOCKBIT").finish()
4185 }
4186}
4187///Lockbits
4188pub mod lockbit {
4189 #[repr(C)]
4190 ///Register block
4191 pub struct RegisterBlock {
4192 lockbit: LOCKBIT,
4193 }
4194 impl RegisterBlock {
4195 ///0x00 - No Description.
4196 #[inline(always)]
4197 pub const fn lockbit(&self) -> &LOCKBIT {
4198 &self.lockbit
4199 }
4200 }
4201 /**LOCKBIT (rw) register accessor: No Description.
4202
4203You can [`read`](crate::Reg::read) this register and get [`lockbit::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lockbit::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
4204
4205For information about available fields see [`mod@lockbit`] module*/
4206 pub type LOCKBIT = crate::Reg<lockbit::LOCKBIT_SPEC>;
4207 ///No Description.
4208 pub mod lockbit {
4209 ///Register `LOCKBIT` reader
4210 pub type R = crate::R<LOCKBIT_SPEC>;
4211 ///Register `LOCKBIT` writer
4212 pub type W = crate::W<LOCKBIT_SPEC>;
4213 /**Memory Lock
4214
4215Value on reset: 0*/
4216 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
4217 #[repr(u8)]
4218 pub enum LB_A {
4219 ///0: Further programming and verification disabled
4220 PROG_VER_DISABLED = 0,
4221 ///2: Further programming disabled
4222 PROG_DISABLED = 2,
4223 ///3: No memory lock features enabled
4224 NO_LOCK = 3,
4225 }
4226 impl From<LB_A> for u8 {
4227 #[inline(always)]
4228 fn from(variant: LB_A) -> Self {
4229 variant as _
4230 }
4231 }
4232 impl crate::FieldSpec for LB_A {
4233 type Ux = u8;
4234 }
4235 impl crate::IsEnum for LB_A {}
4236 ///Field `LB` reader - Memory Lock
4237 pub type LB_R = crate::FieldReader<LB_A>;
4238 impl LB_R {
4239 ///Get enumerated values variant
4240 #[inline(always)]
4241 pub const fn variant(&self) -> Option<LB_A> {
4242 match self.bits {
4243 0 => Some(LB_A::PROG_VER_DISABLED),
4244 2 => Some(LB_A::PROG_DISABLED),
4245 3 => Some(LB_A::NO_LOCK),
4246 _ => None,
4247 }
4248 }
4249 ///Further programming and verification disabled
4250 #[inline(always)]
4251 pub fn is_prog_ver_disabled(&self) -> bool {
4252 *self == LB_A::PROG_VER_DISABLED
4253 }
4254 ///Further programming disabled
4255 #[inline(always)]
4256 pub fn is_prog_disabled(&self) -> bool {
4257 *self == LB_A::PROG_DISABLED
4258 }
4259 ///No memory lock features enabled
4260 #[inline(always)]
4261 pub fn is_no_lock(&self) -> bool {
4262 *self == LB_A::NO_LOCK
4263 }
4264 }
4265 ///Field `LB` writer - Memory Lock
4266 pub type LB_W<'a, REG> = crate::FieldWriter<'a, REG, 2, LB_A>;
4267 impl<'a, REG> LB_W<'a, REG>
4268 where
4269 REG: crate::Writable + crate::RegisterSpec,
4270 REG::Ux: From<u8>,
4271 {
4272 ///Further programming and verification disabled
4273 #[inline(always)]
4274 pub fn prog_ver_disabled(self) -> &'a mut crate::W<REG> {
4275 self.variant(LB_A::PROG_VER_DISABLED)
4276 }
4277 ///Further programming disabled
4278 #[inline(always)]
4279 pub fn prog_disabled(self) -> &'a mut crate::W<REG> {
4280 self.variant(LB_A::PROG_DISABLED)
4281 }
4282 ///No memory lock features enabled
4283 #[inline(always)]
4284 pub fn no_lock(self) -> &'a mut crate::W<REG> {
4285 self.variant(LB_A::NO_LOCK)
4286 }
4287 }
4288 impl R {
4289 ///Bits 0:1 - Memory Lock
4290 #[inline(always)]
4291 pub fn lb(&self) -> LB_R {
4292 LB_R::new(self.bits & 3)
4293 }
4294 }
4295 impl W {
4296 ///Bits 0:1 - Memory Lock
4297 #[inline(always)]
4298 pub fn lb(&mut self) -> LB_W<'_, LOCKBIT_SPEC> {
4299 LB_W::new(self, 0)
4300 }
4301 }
4302 /**No Description.
4303
4304You can [`read`](crate::Reg::read) this register and get [`lockbit::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lockbit::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
4305 pub struct LOCKBIT_SPEC;
4306 impl crate::RegisterSpec for LOCKBIT_SPEC {
4307 type Ux = u8;
4308 }
4309 ///`read()` method returns [`lockbit::R`](R) reader structure
4310 impl crate::Readable for LOCKBIT_SPEC {}
4311 ///`write(|w| ..)` method takes [`lockbit::W`](W) writer structure
4312 impl crate::Writable for LOCKBIT_SPEC {
4313 type Safety = crate::Unsafe;
4314 }
4315 ///`reset()` method sets LOCKBIT to value 0
4316 impl crate::Resettable for LOCKBIT_SPEC {}
4317 }
4318}
4319///I/O Port
4320pub type PORTB = crate::Periph<portb::RegisterBlock, 0x36>;
4321impl core::fmt::Debug for PORTB {
4322 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
4323 f.debug_struct("PORTB").finish()
4324 }
4325}
4326///I/O Port
4327pub mod portb {
4328 #[repr(C)]
4329 ///Register block
4330 pub struct RegisterBlock {
4331 pinb: PINB,
4332 ddrb: DDRB,
4333 portb: PORTB,
4334 }
4335 impl RegisterBlock {
4336 ///0x00 - Input Pins, Port B
4337 #[inline(always)]
4338 pub const fn pinb(&self) -> &PINB {
4339 &self.pinb
4340 }
4341 ///0x01 - Data Direction Register, Port B
4342 #[inline(always)]
4343 pub const fn ddrb(&self) -> &DDRB {
4344 &self.ddrb
4345 }
4346 ///0x02 - Data Register, Port B
4347 #[inline(always)]
4348 pub const fn portb(&self) -> &PORTB {
4349 &self.portb
4350 }
4351 }
4352 /**DDRB (rw) register accessor: Data Direction Register, Port B
4353
4354You can [`read`](crate::Reg::read) this register and get [`ddrb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ddrb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
4355
4356For information about available fields see [`mod@ddrb`] module*/
4357 pub type DDRB = crate::Reg<ddrb::DDRB_SPEC>;
4358 ///Data Direction Register, Port B
4359 pub mod ddrb {
4360 ///Register `DDRB` reader
4361 pub type R = crate::R<DDRB_SPEC>;
4362 ///Register `DDRB` writer
4363 pub type W = crate::W<DDRB_SPEC>;
4364 ///Field `PB0` reader - Pin B0
4365 pub type PB0_R = crate::BitReader;
4366 ///Field `PB0` writer - Pin B0
4367 pub type PB0_W<'a, REG> = crate::BitWriter<'a, REG>;
4368 ///Field `PB1` reader - Pin B1
4369 pub type PB1_R = crate::BitReader;
4370 ///Field `PB1` writer - Pin B1
4371 pub type PB1_W<'a, REG> = crate::BitWriter<'a, REG>;
4372 ///Field `PB2` reader - Pin B2
4373 pub type PB2_R = crate::BitReader;
4374 ///Field `PB2` writer - Pin B2
4375 pub type PB2_W<'a, REG> = crate::BitWriter<'a, REG>;
4376 ///Field `PB3` reader - Pin B3
4377 pub type PB3_R = crate::BitReader;
4378 ///Field `PB3` writer - Pin B3
4379 pub type PB3_W<'a, REG> = crate::BitWriter<'a, REG>;
4380 ///Field `PB4` reader - Pin B4
4381 pub type PB4_R = crate::BitReader;
4382 ///Field `PB4` writer - Pin B4
4383 pub type PB4_W<'a, REG> = crate::BitWriter<'a, REG>;
4384 ///Field `PB5` reader - Pin B5
4385 pub type PB5_R = crate::BitReader;
4386 ///Field `PB5` writer - Pin B5
4387 pub type PB5_W<'a, REG> = crate::BitWriter<'a, REG>;
4388 impl R {
4389 ///Bit 0 - Pin B0
4390 #[inline(always)]
4391 pub fn pb0(&self) -> PB0_R {
4392 PB0_R::new((self.bits & 1) != 0)
4393 }
4394 ///Bit 1 - Pin B1
4395 #[inline(always)]
4396 pub fn pb1(&self) -> PB1_R {
4397 PB1_R::new(((self.bits >> 1) & 1) != 0)
4398 }
4399 ///Bit 2 - Pin B2
4400 #[inline(always)]
4401 pub fn pb2(&self) -> PB2_R {
4402 PB2_R::new(((self.bits >> 2) & 1) != 0)
4403 }
4404 ///Bit 3 - Pin B3
4405 #[inline(always)]
4406 pub fn pb3(&self) -> PB3_R {
4407 PB3_R::new(((self.bits >> 3) & 1) != 0)
4408 }
4409 ///Bit 4 - Pin B4
4410 #[inline(always)]
4411 pub fn pb4(&self) -> PB4_R {
4412 PB4_R::new(((self.bits >> 4) & 1) != 0)
4413 }
4414 ///Bit 5 - Pin B5
4415 #[inline(always)]
4416 pub fn pb5(&self) -> PB5_R {
4417 PB5_R::new(((self.bits >> 5) & 1) != 0)
4418 }
4419 }
4420 impl W {
4421 ///Bit 0 - Pin B0
4422 #[inline(always)]
4423 pub fn pb0(&mut self) -> PB0_W<'_, DDRB_SPEC> {
4424 PB0_W::new(self, 0)
4425 }
4426 ///Bit 1 - Pin B1
4427 #[inline(always)]
4428 pub fn pb1(&mut self) -> PB1_W<'_, DDRB_SPEC> {
4429 PB1_W::new(self, 1)
4430 }
4431 ///Bit 2 - Pin B2
4432 #[inline(always)]
4433 pub fn pb2(&mut self) -> PB2_W<'_, DDRB_SPEC> {
4434 PB2_W::new(self, 2)
4435 }
4436 ///Bit 3 - Pin B3
4437 #[inline(always)]
4438 pub fn pb3(&mut self) -> PB3_W<'_, DDRB_SPEC> {
4439 PB3_W::new(self, 3)
4440 }
4441 ///Bit 4 - Pin B4
4442 #[inline(always)]
4443 pub fn pb4(&mut self) -> PB4_W<'_, DDRB_SPEC> {
4444 PB4_W::new(self, 4)
4445 }
4446 ///Bit 5 - Pin B5
4447 #[inline(always)]
4448 pub fn pb5(&mut self) -> PB5_W<'_, DDRB_SPEC> {
4449 PB5_W::new(self, 5)
4450 }
4451 }
4452 /**Data Direction Register, Port B
4453
4454You can [`read`](crate::Reg::read) this register and get [`ddrb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ddrb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
4455 pub struct DDRB_SPEC;
4456 impl crate::RegisterSpec for DDRB_SPEC {
4457 type Ux = u8;
4458 }
4459 ///`read()` method returns [`ddrb::R`](R) reader structure
4460 impl crate::Readable for DDRB_SPEC {}
4461 ///`write(|w| ..)` method takes [`ddrb::W`](W) writer structure
4462 impl crate::Writable for DDRB_SPEC {
4463 type Safety = crate::Unsafe;
4464 }
4465 ///`reset()` method sets DDRB to value 0
4466 impl crate::Resettable for DDRB_SPEC {}
4467 }
4468 /**PINB (rw) register accessor: Input Pins, Port B
4469
4470You can [`read`](crate::Reg::read) this register and get [`pinb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pinb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
4471
4472For information about available fields see [`mod@pinb`] module*/
4473 pub type PINB = crate::Reg<pinb::PINB_SPEC>;
4474 ///Input Pins, Port B
4475 pub mod pinb {
4476 ///Register `PINB` reader
4477 pub type R = crate::R<PINB_SPEC>;
4478 ///Register `PINB` writer
4479 pub type W = crate::W<PINB_SPEC>;
4480 ///Field `PB0` reader - Pin B0
4481 pub type PB0_R = crate::BitReader;
4482 ///Field `PB0` writer - Pin B0
4483 pub type PB0_W<'a, REG> = crate::BitWriter<'a, REG>;
4484 ///Field `PB1` reader - Pin B1
4485 pub type PB1_R = crate::BitReader;
4486 ///Field `PB1` writer - Pin B1
4487 pub type PB1_W<'a, REG> = crate::BitWriter<'a, REG>;
4488 ///Field `PB2` reader - Pin B2
4489 pub type PB2_R = crate::BitReader;
4490 ///Field `PB2` writer - Pin B2
4491 pub type PB2_W<'a, REG> = crate::BitWriter<'a, REG>;
4492 ///Field `PB3` reader - Pin B3
4493 pub type PB3_R = crate::BitReader;
4494 ///Field `PB3` writer - Pin B3
4495 pub type PB3_W<'a, REG> = crate::BitWriter<'a, REG>;
4496 ///Field `PB4` reader - Pin B4
4497 pub type PB4_R = crate::BitReader;
4498 ///Field `PB4` writer - Pin B4
4499 pub type PB4_W<'a, REG> = crate::BitWriter<'a, REG>;
4500 ///Field `PB5` reader - Pin B5
4501 pub type PB5_R = crate::BitReader;
4502 ///Field `PB5` writer - Pin B5
4503 pub type PB5_W<'a, REG> = crate::BitWriter<'a, REG>;
4504 impl R {
4505 ///Bit 0 - Pin B0
4506 #[inline(always)]
4507 pub fn pb0(&self) -> PB0_R {
4508 PB0_R::new((self.bits & 1) != 0)
4509 }
4510 ///Bit 1 - Pin B1
4511 #[inline(always)]
4512 pub fn pb1(&self) -> PB1_R {
4513 PB1_R::new(((self.bits >> 1) & 1) != 0)
4514 }
4515 ///Bit 2 - Pin B2
4516 #[inline(always)]
4517 pub fn pb2(&self) -> PB2_R {
4518 PB2_R::new(((self.bits >> 2) & 1) != 0)
4519 }
4520 ///Bit 3 - Pin B3
4521 #[inline(always)]
4522 pub fn pb3(&self) -> PB3_R {
4523 PB3_R::new(((self.bits >> 3) & 1) != 0)
4524 }
4525 ///Bit 4 - Pin B4
4526 #[inline(always)]
4527 pub fn pb4(&self) -> PB4_R {
4528 PB4_R::new(((self.bits >> 4) & 1) != 0)
4529 }
4530 ///Bit 5 - Pin B5
4531 #[inline(always)]
4532 pub fn pb5(&self) -> PB5_R {
4533 PB5_R::new(((self.bits >> 5) & 1) != 0)
4534 }
4535 }
4536 impl W {
4537 ///Bit 0 - Pin B0
4538 #[inline(always)]
4539 pub fn pb0(&mut self) -> PB0_W<'_, PINB_SPEC> {
4540 PB0_W::new(self, 0)
4541 }
4542 ///Bit 1 - Pin B1
4543 #[inline(always)]
4544 pub fn pb1(&mut self) -> PB1_W<'_, PINB_SPEC> {
4545 PB1_W::new(self, 1)
4546 }
4547 ///Bit 2 - Pin B2
4548 #[inline(always)]
4549 pub fn pb2(&mut self) -> PB2_W<'_, PINB_SPEC> {
4550 PB2_W::new(self, 2)
4551 }
4552 ///Bit 3 - Pin B3
4553 #[inline(always)]
4554 pub fn pb3(&mut self) -> PB3_W<'_, PINB_SPEC> {
4555 PB3_W::new(self, 3)
4556 }
4557 ///Bit 4 - Pin B4
4558 #[inline(always)]
4559 pub fn pb4(&mut self) -> PB4_W<'_, PINB_SPEC> {
4560 PB4_W::new(self, 4)
4561 }
4562 ///Bit 5 - Pin B5
4563 #[inline(always)]
4564 pub fn pb5(&mut self) -> PB5_W<'_, PINB_SPEC> {
4565 PB5_W::new(self, 5)
4566 }
4567 }
4568 /**Input Pins, Port B
4569
4570You can [`read`](crate::Reg::read) this register and get [`pinb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pinb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
4571 pub struct PINB_SPEC;
4572 impl crate::RegisterSpec for PINB_SPEC {
4573 type Ux = u8;
4574 }
4575 ///`read()` method returns [`pinb::R`](R) reader structure
4576 impl crate::Readable for PINB_SPEC {}
4577 ///`write(|w| ..)` method takes [`pinb::W`](W) writer structure
4578 impl crate::Writable for PINB_SPEC {
4579 type Safety = crate::Unsafe;
4580 }
4581 ///`reset()` method sets PINB to value 0
4582 impl crate::Resettable for PINB_SPEC {}
4583 }
4584 /**PORTB (rw) register accessor: Data Register, Port B
4585
4586You can [`read`](crate::Reg::read) this register and get [`portb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`portb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
4587
4588For information about available fields see [`mod@portb`] module*/
4589 pub type PORTB = crate::Reg<portb::PORTB_SPEC>;
4590 ///Data Register, Port B
4591 pub mod portb {
4592 ///Register `PORTB` reader
4593 pub type R = crate::R<PORTB_SPEC>;
4594 ///Register `PORTB` writer
4595 pub type W = crate::W<PORTB_SPEC>;
4596 ///Field `PB0` reader - Pin B0
4597 pub type PB0_R = crate::BitReader;
4598 ///Field `PB0` writer - Pin B0
4599 pub type PB0_W<'a, REG> = crate::BitWriter<'a, REG>;
4600 ///Field `PB1` reader - Pin B1
4601 pub type PB1_R = crate::BitReader;
4602 ///Field `PB1` writer - Pin B1
4603 pub type PB1_W<'a, REG> = crate::BitWriter<'a, REG>;
4604 ///Field `PB2` reader - Pin B2
4605 pub type PB2_R = crate::BitReader;
4606 ///Field `PB2` writer - Pin B2
4607 pub type PB2_W<'a, REG> = crate::BitWriter<'a, REG>;
4608 ///Field `PB3` reader - Pin B3
4609 pub type PB3_R = crate::BitReader;
4610 ///Field `PB3` writer - Pin B3
4611 pub type PB3_W<'a, REG> = crate::BitWriter<'a, REG>;
4612 ///Field `PB4` reader - Pin B4
4613 pub type PB4_R = crate::BitReader;
4614 ///Field `PB4` writer - Pin B4
4615 pub type PB4_W<'a, REG> = crate::BitWriter<'a, REG>;
4616 ///Field `PB5` reader - Pin B5
4617 pub type PB5_R = crate::BitReader;
4618 ///Field `PB5` writer - Pin B5
4619 pub type PB5_W<'a, REG> = crate::BitWriter<'a, REG>;
4620 impl R {
4621 ///Bit 0 - Pin B0
4622 #[inline(always)]
4623 pub fn pb0(&self) -> PB0_R {
4624 PB0_R::new((self.bits & 1) != 0)
4625 }
4626 ///Bit 1 - Pin B1
4627 #[inline(always)]
4628 pub fn pb1(&self) -> PB1_R {
4629 PB1_R::new(((self.bits >> 1) & 1) != 0)
4630 }
4631 ///Bit 2 - Pin B2
4632 #[inline(always)]
4633 pub fn pb2(&self) -> PB2_R {
4634 PB2_R::new(((self.bits >> 2) & 1) != 0)
4635 }
4636 ///Bit 3 - Pin B3
4637 #[inline(always)]
4638 pub fn pb3(&self) -> PB3_R {
4639 PB3_R::new(((self.bits >> 3) & 1) != 0)
4640 }
4641 ///Bit 4 - Pin B4
4642 #[inline(always)]
4643 pub fn pb4(&self) -> PB4_R {
4644 PB4_R::new(((self.bits >> 4) & 1) != 0)
4645 }
4646 ///Bit 5 - Pin B5
4647 #[inline(always)]
4648 pub fn pb5(&self) -> PB5_R {
4649 PB5_R::new(((self.bits >> 5) & 1) != 0)
4650 }
4651 }
4652 impl W {
4653 ///Bit 0 - Pin B0
4654 #[inline(always)]
4655 pub fn pb0(&mut self) -> PB0_W<'_, PORTB_SPEC> {
4656 PB0_W::new(self, 0)
4657 }
4658 ///Bit 1 - Pin B1
4659 #[inline(always)]
4660 pub fn pb1(&mut self) -> PB1_W<'_, PORTB_SPEC> {
4661 PB1_W::new(self, 1)
4662 }
4663 ///Bit 2 - Pin B2
4664 #[inline(always)]
4665 pub fn pb2(&mut self) -> PB2_W<'_, PORTB_SPEC> {
4666 PB2_W::new(self, 2)
4667 }
4668 ///Bit 3 - Pin B3
4669 #[inline(always)]
4670 pub fn pb3(&mut self) -> PB3_W<'_, PORTB_SPEC> {
4671 PB3_W::new(self, 3)
4672 }
4673 ///Bit 4 - Pin B4
4674 #[inline(always)]
4675 pub fn pb4(&mut self) -> PB4_W<'_, PORTB_SPEC> {
4676 PB4_W::new(self, 4)
4677 }
4678 ///Bit 5 - Pin B5
4679 #[inline(always)]
4680 pub fn pb5(&mut self) -> PB5_W<'_, PORTB_SPEC> {
4681 PB5_W::new(self, 5)
4682 }
4683 }
4684 /**Data Register, Port B
4685
4686You can [`read`](crate::Reg::read) this register and get [`portb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`portb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
4687 pub struct PORTB_SPEC;
4688 impl crate::RegisterSpec for PORTB_SPEC {
4689 type Ux = u8;
4690 }
4691 ///`read()` method returns [`portb::R`](R) reader structure
4692 impl crate::Readable for PORTB_SPEC {}
4693 ///`write(|w| ..)` method takes [`portb::W`](W) writer structure
4694 impl crate::Writable for PORTB_SPEC {
4695 type Safety = crate::Unsafe;
4696 }
4697 ///`reset()` method sets PORTB to value 0
4698 impl crate::Resettable for PORTB_SPEC {}
4699 }
4700}
4701///Timer/Counter0, 8-bit, PWM
4702pub type TC0 = crate::Periph<tc0::RegisterBlock, 0x48>;
4703impl core::fmt::Debug for TC0 {
4704 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
4705 f.debug_struct("TC0").finish()
4706 }
4707}
4708///Timer/Counter0, 8-bit, PWM
4709pub mod tc0 {
4710 #[repr(C)]
4711 ///Register block
4712 pub struct RegisterBlock {
4713 ocr0b: OCR0B,
4714 ocr0a: OCR0A,
4715 tccr0a: TCCR0A,
4716 _reserved3: [u8; 0x01],
4717 gtccr: GTCCR,
4718 _reserved4: [u8; 0x05],
4719 tcnt0: TCNT0,
4720 tccr0b: TCCR0B,
4721 _reserved6: [u8; 0x04],
4722 tifr: TIFR,
4723 timsk: TIMSK,
4724 }
4725 impl RegisterBlock {
4726 ///0x00 - Output Compare Register B
4727 #[inline(always)]
4728 pub const fn ocr0b(&self) -> &OCR0B {
4729 &self.ocr0b
4730 }
4731 ///0x01 - Output Compare Register A
4732 #[inline(always)]
4733 pub const fn ocr0a(&self) -> &OCR0A {
4734 &self.ocr0a
4735 }
4736 ///0x02 - Timer/Counter Control Register A
4737 #[inline(always)]
4738 pub const fn tccr0a(&self) -> &TCCR0A {
4739 &self.tccr0a
4740 }
4741 ///0x04 - General Timer/Counter Control Register
4742 #[inline(always)]
4743 pub const fn gtccr(&self) -> >CCR {
4744 &self.gtccr
4745 }
4746 ///0x0a - Timer/Counter0
4747 #[inline(always)]
4748 pub const fn tcnt0(&self) -> &TCNT0 {
4749 &self.tcnt0
4750 }
4751 ///0x0b - Timer/Counter Control Register B
4752 #[inline(always)]
4753 pub const fn tccr0b(&self) -> &TCCR0B {
4754 &self.tccr0b
4755 }
4756 ///0x10 - Timer/Counter0 Interrupt Flag register
4757 #[inline(always)]
4758 pub const fn tifr(&self) -> &TIFR {
4759 &self.tifr
4760 }
4761 ///0x11 - Timer/Counter Interrupt Mask Register
4762 #[inline(always)]
4763 pub const fn timsk(&self) -> &TIMSK {
4764 &self.timsk
4765 }
4766 }
4767 /**GTCCR (rw) register accessor: General Timer/Counter Control Register
4768
4769You can [`read`](crate::Reg::read) this register and get [`gtccr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gtccr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
4770
4771For information about available fields see [`mod@gtccr`] module*/
4772 pub type GTCCR = crate::Reg<gtccr::GTCCR_SPEC>;
4773 ///General Timer/Counter Control Register
4774 pub mod gtccr {
4775 ///Register `GTCCR` reader
4776 pub type R = crate::R<GTCCR_SPEC>;
4777 ///Register `GTCCR` writer
4778 pub type W = crate::W<GTCCR_SPEC>;
4779 ///Field `PSR0` reader - Prescaler Reset Timer/Counter1 and Timer/Counter0
4780 pub type PSR0_R = crate::BitReader;
4781 ///Field `PSR0` writer - Prescaler Reset Timer/Counter1 and Timer/Counter0
4782 pub type PSR0_W<'a, REG> = crate::BitWriter<'a, REG>;
4783 ///Field `TSM` reader - Timer/Counter Synchronization Mode
4784 pub type TSM_R = crate::BitReader;
4785 ///Field `TSM` writer - Timer/Counter Synchronization Mode
4786 pub type TSM_W<'a, REG> = crate::BitWriter<'a, REG>;
4787 impl R {
4788 ///Bit 0 - Prescaler Reset Timer/Counter1 and Timer/Counter0
4789 #[inline(always)]
4790 pub fn psr0(&self) -> PSR0_R {
4791 PSR0_R::new((self.bits & 1) != 0)
4792 }
4793 ///Bit 7 - Timer/Counter Synchronization Mode
4794 #[inline(always)]
4795 pub fn tsm(&self) -> TSM_R {
4796 TSM_R::new(((self.bits >> 7) & 1) != 0)
4797 }
4798 }
4799 impl W {
4800 ///Bit 0 - Prescaler Reset Timer/Counter1 and Timer/Counter0
4801 #[inline(always)]
4802 pub fn psr0(&mut self) -> PSR0_W<'_, GTCCR_SPEC> {
4803 PSR0_W::new(self, 0)
4804 }
4805 ///Bit 7 - Timer/Counter Synchronization Mode
4806 #[inline(always)]
4807 pub fn tsm(&mut self) -> TSM_W<'_, GTCCR_SPEC> {
4808 TSM_W::new(self, 7)
4809 }
4810 }
4811 /**General Timer/Counter Control Register
4812
4813You can [`read`](crate::Reg::read) this register and get [`gtccr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gtccr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
4814 pub struct GTCCR_SPEC;
4815 impl crate::RegisterSpec for GTCCR_SPEC {
4816 type Ux = u8;
4817 }
4818 ///`read()` method returns [`gtccr::R`](R) reader structure
4819 impl crate::Readable for GTCCR_SPEC {}
4820 ///`write(|w| ..)` method takes [`gtccr::W`](W) writer structure
4821 impl crate::Writable for GTCCR_SPEC {
4822 type Safety = crate::Unsafe;
4823 }
4824 ///`reset()` method sets GTCCR to value 0
4825 impl crate::Resettable for GTCCR_SPEC {}
4826 }
4827 /**OCR0A (rw) register accessor: Output Compare Register A
4828
4829You can [`read`](crate::Reg::read) this register and get [`ocr0a::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ocr0a::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
4830
4831For information about available fields see [`mod@ocr0a`] module*/
4832 pub type OCR0A = crate::Reg<ocr0a::OCR0A_SPEC>;
4833 ///Output Compare Register A
4834 pub mod ocr0a {
4835 ///Register `OCR0A` reader
4836 pub type R = crate::R<OCR0A_SPEC>;
4837 ///Register `OCR0A` writer
4838 pub type W = crate::W<OCR0A_SPEC>;
4839 impl core::fmt::Debug for R {
4840 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
4841 write!(f, "{}", self.bits())
4842 }
4843 }
4844 impl W {}
4845 /**Output Compare Register A
4846
4847You can [`read`](crate::Reg::read) this register and get [`ocr0a::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ocr0a::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
4848 pub struct OCR0A_SPEC;
4849 impl crate::RegisterSpec for OCR0A_SPEC {
4850 type Ux = u8;
4851 }
4852 ///`read()` method returns [`ocr0a::R`](R) reader structure
4853 impl crate::Readable for OCR0A_SPEC {}
4854 ///`write(|w| ..)` method takes [`ocr0a::W`](W) writer structure
4855 impl crate::Writable for OCR0A_SPEC {
4856 type Safety = crate::Safe;
4857 }
4858 ///`reset()` method sets OCR0A to value 0
4859 impl crate::Resettable for OCR0A_SPEC {}
4860 }
4861 /**OCR0B (rw) register accessor: Output Compare Register B
4862
4863You can [`read`](crate::Reg::read) this register and get [`ocr0b::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ocr0b::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
4864
4865For information about available fields see [`mod@ocr0b`] module*/
4866 pub type OCR0B = crate::Reg<ocr0b::OCR0B_SPEC>;
4867 ///Output Compare Register B
4868 pub mod ocr0b {
4869 ///Register `OCR0B` reader
4870 pub type R = crate::R<OCR0B_SPEC>;
4871 ///Register `OCR0B` writer
4872 pub type W = crate::W<OCR0B_SPEC>;
4873 impl core::fmt::Debug for R {
4874 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
4875 write!(f, "{}", self.bits())
4876 }
4877 }
4878 impl W {}
4879 /**Output Compare Register B
4880
4881You can [`read`](crate::Reg::read) this register and get [`ocr0b::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ocr0b::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
4882 pub struct OCR0B_SPEC;
4883 impl crate::RegisterSpec for OCR0B_SPEC {
4884 type Ux = u8;
4885 }
4886 ///`read()` method returns [`ocr0b::R`](R) reader structure
4887 impl crate::Readable for OCR0B_SPEC {}
4888 ///`write(|w| ..)` method takes [`ocr0b::W`](W) writer structure
4889 impl crate::Writable for OCR0B_SPEC {
4890 type Safety = crate::Safe;
4891 }
4892 ///`reset()` method sets OCR0B to value 0
4893 impl crate::Resettable for OCR0B_SPEC {}
4894 }
4895 /**TCCR0A (rw) register accessor: Timer/Counter Control Register A
4896
4897You can [`read`](crate::Reg::read) this register and get [`tccr0a::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tccr0a::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
4898
4899For information about available fields see [`mod@tccr0a`] module*/
4900 pub type TCCR0A = crate::Reg<tccr0a::TCCR0A_SPEC>;
4901 ///Timer/Counter Control Register A
4902 pub mod tccr0a {
4903 ///Register `TCCR0A` reader
4904 pub type R = crate::R<TCCR0A_SPEC>;
4905 ///Register `TCCR0A` writer
4906 pub type W = crate::W<TCCR0A_SPEC>;
4907 /**Waveform Generation Mode
4908
4909Value on reset: 0*/
4910 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
4911 #[repr(u8)]
4912 pub enum WGM0_A {
4913 ///0: Normal, Top: `0xff`, Update: *Immediate*, Flag: *MAX*
4914 NORMAL_TOP = 0,
4915 ///1: Phase Correct PWM, Top: `0xff`, Update: *TOP*, Flag: *BOTTOM*
4916 PWM_PHASE = 1,
4917 ///2: CTC, Top: *OCRA*, Update: *Immediate*, Flag: *MAX*
4918 CTC = 2,
4919 ///3: Fast PWM, Top: `0xff`, Update: *BOTTOM*, Flag: *TOP*
4920 PWM_FAST = 3,
4921 }
4922 impl From<WGM0_A> for u8 {
4923 #[inline(always)]
4924 fn from(variant: WGM0_A) -> Self {
4925 variant as _
4926 }
4927 }
4928 impl crate::FieldSpec for WGM0_A {
4929 type Ux = u8;
4930 }
4931 impl crate::IsEnum for WGM0_A {}
4932 ///Field `WGM0` reader - Waveform Generation Mode
4933 pub type WGM0_R = crate::FieldReader<WGM0_A>;
4934 impl WGM0_R {
4935 ///Get enumerated values variant
4936 #[inline(always)]
4937 pub const fn variant(&self) -> WGM0_A {
4938 match self.bits {
4939 0 => WGM0_A::NORMAL_TOP,
4940 1 => WGM0_A::PWM_PHASE,
4941 2 => WGM0_A::CTC,
4942 3 => WGM0_A::PWM_FAST,
4943 _ => unreachable!(),
4944 }
4945 }
4946 ///Normal, Top: `0xff`, Update: *Immediate*, Flag: *MAX*
4947 #[inline(always)]
4948 pub fn is_normal_top(&self) -> bool {
4949 *self == WGM0_A::NORMAL_TOP
4950 }
4951 ///Phase Correct PWM, Top: `0xff`, Update: *TOP*, Flag: *BOTTOM*
4952 #[inline(always)]
4953 pub fn is_pwm_phase(&self) -> bool {
4954 *self == WGM0_A::PWM_PHASE
4955 }
4956 ///CTC, Top: *OCRA*, Update: *Immediate*, Flag: *MAX*
4957 #[inline(always)]
4958 pub fn is_ctc(&self) -> bool {
4959 *self == WGM0_A::CTC
4960 }
4961 ///Fast PWM, Top: `0xff`, Update: *BOTTOM*, Flag: *TOP*
4962 #[inline(always)]
4963 pub fn is_pwm_fast(&self) -> bool {
4964 *self == WGM0_A::PWM_FAST
4965 }
4966 }
4967 ///Field `WGM0` writer - Waveform Generation Mode
4968 pub type WGM0_W<'a, REG> = crate::FieldWriter<'a, REG, 2, WGM0_A, crate::Safe>;
4969 impl<'a, REG> WGM0_W<'a, REG>
4970 where
4971 REG: crate::Writable + crate::RegisterSpec,
4972 REG::Ux: From<u8>,
4973 {
4974 ///Normal, Top: `0xff`, Update: *Immediate*, Flag: *MAX*
4975 #[inline(always)]
4976 pub fn normal_top(self) -> &'a mut crate::W<REG> {
4977 self.variant(WGM0_A::NORMAL_TOP)
4978 }
4979 ///Phase Correct PWM, Top: `0xff`, Update: *TOP*, Flag: *BOTTOM*
4980 #[inline(always)]
4981 pub fn pwm_phase(self) -> &'a mut crate::W<REG> {
4982 self.variant(WGM0_A::PWM_PHASE)
4983 }
4984 ///CTC, Top: *OCRA*, Update: *Immediate*, Flag: *MAX*
4985 #[inline(always)]
4986 pub fn ctc(self) -> &'a mut crate::W<REG> {
4987 self.variant(WGM0_A::CTC)
4988 }
4989 ///Fast PWM, Top: `0xff`, Update: *BOTTOM*, Flag: *TOP*
4990 #[inline(always)]
4991 pub fn pwm_fast(self) -> &'a mut crate::W<REG> {
4992 self.variant(WGM0_A::PWM_FAST)
4993 }
4994 }
4995 /**Compare Output B Mode
4996
4997Value on reset: 0*/
4998 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
4999 #[repr(u8)]
5000 pub enum COM0B_A {
5001 ///0: Normal port operation, OCix disconnected
5002 DISCONNECTED = 0,
5003 ///1: Toggle OCix on Compare Match (Might depend on WGM)
5004 MATCH_TOGGLE = 1,
5005 ///2: Clear OCix on Compare Match (If PWM is enabled, OCix is set at BOTTOM)
5006 MATCH_CLEAR = 2,
5007 ///3: Set OCix on Compare Match (If PWM is enabled, OCix is cleared at BOTTOM)
5008 MATCH_SET = 3,
5009 }
5010 impl From<COM0B_A> for u8 {
5011 #[inline(always)]
5012 fn from(variant: COM0B_A) -> Self {
5013 variant as _
5014 }
5015 }
5016 impl crate::FieldSpec for COM0B_A {
5017 type Ux = u8;
5018 }
5019 impl crate::IsEnum for COM0B_A {}
5020 ///Field `COM0B` reader - Compare Output B Mode
5021 pub type COM0B_R = crate::FieldReader<COM0B_A>;
5022 impl COM0B_R {
5023 ///Get enumerated values variant
5024 #[inline(always)]
5025 pub const fn variant(&self) -> COM0B_A {
5026 match self.bits {
5027 0 => COM0B_A::DISCONNECTED,
5028 1 => COM0B_A::MATCH_TOGGLE,
5029 2 => COM0B_A::MATCH_CLEAR,
5030 3 => COM0B_A::MATCH_SET,
5031 _ => unreachable!(),
5032 }
5033 }
5034 ///Normal port operation, OCix disconnected
5035 #[inline(always)]
5036 pub fn is_disconnected(&self) -> bool {
5037 *self == COM0B_A::DISCONNECTED
5038 }
5039 ///Toggle OCix on Compare Match (Might depend on WGM)
5040 #[inline(always)]
5041 pub fn is_match_toggle(&self) -> bool {
5042 *self == COM0B_A::MATCH_TOGGLE
5043 }
5044 ///Clear OCix on Compare Match (If PWM is enabled, OCix is set at BOTTOM)
5045 #[inline(always)]
5046 pub fn is_match_clear(&self) -> bool {
5047 *self == COM0B_A::MATCH_CLEAR
5048 }
5049 ///Set OCix on Compare Match (If PWM is enabled, OCix is cleared at BOTTOM)
5050 #[inline(always)]
5051 pub fn is_match_set(&self) -> bool {
5052 *self == COM0B_A::MATCH_SET
5053 }
5054 }
5055 ///Field `COM0B` writer - Compare Output B Mode
5056 pub type COM0B_W<'a, REG> = crate::FieldWriter<'a, REG, 2, COM0B_A, crate::Safe>;
5057 impl<'a, REG> COM0B_W<'a, REG>
5058 where
5059 REG: crate::Writable + crate::RegisterSpec,
5060 REG::Ux: From<u8>,
5061 {
5062 ///Normal port operation, OCix disconnected
5063 #[inline(always)]
5064 pub fn disconnected(self) -> &'a mut crate::W<REG> {
5065 self.variant(COM0B_A::DISCONNECTED)
5066 }
5067 ///Toggle OCix on Compare Match (Might depend on WGM)
5068 #[inline(always)]
5069 pub fn match_toggle(self) -> &'a mut crate::W<REG> {
5070 self.variant(COM0B_A::MATCH_TOGGLE)
5071 }
5072 ///Clear OCix on Compare Match (If PWM is enabled, OCix is set at BOTTOM)
5073 #[inline(always)]
5074 pub fn match_clear(self) -> &'a mut crate::W<REG> {
5075 self.variant(COM0B_A::MATCH_CLEAR)
5076 }
5077 ///Set OCix on Compare Match (If PWM is enabled, OCix is cleared at BOTTOM)
5078 #[inline(always)]
5079 pub fn match_set(self) -> &'a mut crate::W<REG> {
5080 self.variant(COM0B_A::MATCH_SET)
5081 }
5082 }
5083 ///Field `COM0A` reader - Compare Output A Mode
5084 pub use COM0B_R as COM0A_R;
5085 ///Field `COM0A` writer - Compare Output A Mode
5086 pub use COM0B_W as COM0A_W;
5087 impl R {
5088 ///Bits 0:1 - Waveform Generation Mode
5089 #[inline(always)]
5090 pub fn wgm0(&self) -> WGM0_R {
5091 WGM0_R::new(self.bits & 3)
5092 }
5093 ///Bits 4:5 - Compare Output B Mode
5094 #[inline(always)]
5095 pub fn com0b(&self) -> COM0B_R {
5096 COM0B_R::new((self.bits >> 4) & 3)
5097 }
5098 ///Bits 6:7 - Compare Output A Mode
5099 #[inline(always)]
5100 pub fn com0a(&self) -> COM0A_R {
5101 COM0A_R::new((self.bits >> 6) & 3)
5102 }
5103 }
5104 impl W {
5105 ///Bits 0:1 - Waveform Generation Mode
5106 #[inline(always)]
5107 pub fn wgm0(&mut self) -> WGM0_W<'_, TCCR0A_SPEC> {
5108 WGM0_W::new(self, 0)
5109 }
5110 ///Bits 4:5 - Compare Output B Mode
5111 #[inline(always)]
5112 pub fn com0b(&mut self) -> COM0B_W<'_, TCCR0A_SPEC> {
5113 COM0B_W::new(self, 4)
5114 }
5115 ///Bits 6:7 - Compare Output A Mode
5116 #[inline(always)]
5117 pub fn com0a(&mut self) -> COM0A_W<'_, TCCR0A_SPEC> {
5118 COM0A_W::new(self, 6)
5119 }
5120 }
5121 /**Timer/Counter Control Register A
5122
5123You can [`read`](crate::Reg::read) this register and get [`tccr0a::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tccr0a::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
5124 pub struct TCCR0A_SPEC;
5125 impl crate::RegisterSpec for TCCR0A_SPEC {
5126 type Ux = u8;
5127 }
5128 ///`read()` method returns [`tccr0a::R`](R) reader structure
5129 impl crate::Readable for TCCR0A_SPEC {}
5130 ///`write(|w| ..)` method takes [`tccr0a::W`](W) writer structure
5131 impl crate::Writable for TCCR0A_SPEC {
5132 type Safety = crate::Unsafe;
5133 }
5134 ///`reset()` method sets TCCR0A to value 0
5135 impl crate::Resettable for TCCR0A_SPEC {}
5136 }
5137 /**TCCR0B (rw) register accessor: Timer/Counter Control Register B
5138
5139You can [`read`](crate::Reg::read) this register and get [`tccr0b::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tccr0b::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
5140
5141For information about available fields see [`mod@tccr0b`] module*/
5142 pub type TCCR0B = crate::Reg<tccr0b::TCCR0B_SPEC>;
5143 ///Timer/Counter Control Register B
5144 pub mod tccr0b {
5145 ///Register `TCCR0B` reader
5146 pub type R = crate::R<TCCR0B_SPEC>;
5147 ///Register `TCCR0B` writer
5148 pub type W = crate::W<TCCR0B_SPEC>;
5149 /**Clock Select
5150
5151Value on reset: 0*/
5152 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
5153 #[repr(u8)]
5154 pub enum CS0_A {
5155 ///0: No clock source (Timer/Counter stopped)
5156 NO_CLOCK = 0,
5157 ///1: Running, No Prescaling
5158 DIRECT = 1,
5159 ///2: Running, CLK/8
5160 PRESCALE_8 = 2,
5161 ///3: Running, CLK/64
5162 PRESCALE_64 = 3,
5163 ///4: Running, CLK/256
5164 PRESCALE_256 = 4,
5165 ///5: Running, CLK/1024
5166 PRESCALE_1024 = 5,
5167 ///6: Running, ExtClk Tx Falling Edge
5168 EXT_FALLING = 6,
5169 ///7: Running, ExtClk Tx Rising Edge
5170 EXT_RISING = 7,
5171 }
5172 impl From<CS0_A> for u8 {
5173 #[inline(always)]
5174 fn from(variant: CS0_A) -> Self {
5175 variant as _
5176 }
5177 }
5178 impl crate::FieldSpec for CS0_A {
5179 type Ux = u8;
5180 }
5181 impl crate::IsEnum for CS0_A {}
5182 ///Field `CS0` reader - Clock Select
5183 pub type CS0_R = crate::FieldReader<CS0_A>;
5184 impl CS0_R {
5185 ///Get enumerated values variant
5186 #[inline(always)]
5187 pub const fn variant(&self) -> CS0_A {
5188 match self.bits {
5189 0 => CS0_A::NO_CLOCK,
5190 1 => CS0_A::DIRECT,
5191 2 => CS0_A::PRESCALE_8,
5192 3 => CS0_A::PRESCALE_64,
5193 4 => CS0_A::PRESCALE_256,
5194 5 => CS0_A::PRESCALE_1024,
5195 6 => CS0_A::EXT_FALLING,
5196 7 => CS0_A::EXT_RISING,
5197 _ => unreachable!(),
5198 }
5199 }
5200 ///No clock source (Timer/Counter stopped)
5201 #[inline(always)]
5202 pub fn is_no_clock(&self) -> bool {
5203 *self == CS0_A::NO_CLOCK
5204 }
5205 ///Running, No Prescaling
5206 #[inline(always)]
5207 pub fn is_direct(&self) -> bool {
5208 *self == CS0_A::DIRECT
5209 }
5210 ///Running, CLK/8
5211 #[inline(always)]
5212 pub fn is_prescale_8(&self) -> bool {
5213 *self == CS0_A::PRESCALE_8
5214 }
5215 ///Running, CLK/64
5216 #[inline(always)]
5217 pub fn is_prescale_64(&self) -> bool {
5218 *self == CS0_A::PRESCALE_64
5219 }
5220 ///Running, CLK/256
5221 #[inline(always)]
5222 pub fn is_prescale_256(&self) -> bool {
5223 *self == CS0_A::PRESCALE_256
5224 }
5225 ///Running, CLK/1024
5226 #[inline(always)]
5227 pub fn is_prescale_1024(&self) -> bool {
5228 *self == CS0_A::PRESCALE_1024
5229 }
5230 ///Running, ExtClk Tx Falling Edge
5231 #[inline(always)]
5232 pub fn is_ext_falling(&self) -> bool {
5233 *self == CS0_A::EXT_FALLING
5234 }
5235 ///Running, ExtClk Tx Rising Edge
5236 #[inline(always)]
5237 pub fn is_ext_rising(&self) -> bool {
5238 *self == CS0_A::EXT_RISING
5239 }
5240 }
5241 ///Field `CS0` writer - Clock Select
5242 pub type CS0_W<'a, REG> = crate::FieldWriter<'a, REG, 3, CS0_A, crate::Safe>;
5243 impl<'a, REG> CS0_W<'a, REG>
5244 where
5245 REG: crate::Writable + crate::RegisterSpec,
5246 REG::Ux: From<u8>,
5247 {
5248 ///No clock source (Timer/Counter stopped)
5249 #[inline(always)]
5250 pub fn no_clock(self) -> &'a mut crate::W<REG> {
5251 self.variant(CS0_A::NO_CLOCK)
5252 }
5253 ///Running, No Prescaling
5254 #[inline(always)]
5255 pub fn direct(self) -> &'a mut crate::W<REG> {
5256 self.variant(CS0_A::DIRECT)
5257 }
5258 ///Running, CLK/8
5259 #[inline(always)]
5260 pub fn prescale_8(self) -> &'a mut crate::W<REG> {
5261 self.variant(CS0_A::PRESCALE_8)
5262 }
5263 ///Running, CLK/64
5264 #[inline(always)]
5265 pub fn prescale_64(self) -> &'a mut crate::W<REG> {
5266 self.variant(CS0_A::PRESCALE_64)
5267 }
5268 ///Running, CLK/256
5269 #[inline(always)]
5270 pub fn prescale_256(self) -> &'a mut crate::W<REG> {
5271 self.variant(CS0_A::PRESCALE_256)
5272 }
5273 ///Running, CLK/1024
5274 #[inline(always)]
5275 pub fn prescale_1024(self) -> &'a mut crate::W<REG> {
5276 self.variant(CS0_A::PRESCALE_1024)
5277 }
5278 ///Running, ExtClk Tx Falling Edge
5279 #[inline(always)]
5280 pub fn ext_falling(self) -> &'a mut crate::W<REG> {
5281 self.variant(CS0_A::EXT_FALLING)
5282 }
5283 ///Running, ExtClk Tx Rising Edge
5284 #[inline(always)]
5285 pub fn ext_rising(self) -> &'a mut crate::W<REG> {
5286 self.variant(CS0_A::EXT_RISING)
5287 }
5288 }
5289 ///Field `WGM02` reader - Waveform Generation Mode High Bit (Enable Top: *OCRA* for `PWM` modes)
5290 pub type WGM02_R = crate::BitReader;
5291 ///Field `WGM02` writer - Waveform Generation Mode High Bit (Enable Top: *OCRA* for `PWM` modes)
5292 pub type WGM02_W<'a, REG> = crate::BitWriter<'a, REG>;
5293 ///Field `FOC0B` writer - Force Output Compare B
5294 pub type FOC0B_W<'a, REG> = crate::BitWriter<'a, REG>;
5295 ///Field `FOC0A` writer - Force Output Compare A
5296 pub type FOC0A_W<'a, REG> = crate::BitWriter<'a, REG>;
5297 impl R {
5298 ///Bits 0:2 - Clock Select
5299 #[inline(always)]
5300 pub fn cs0(&self) -> CS0_R {
5301 CS0_R::new(self.bits & 7)
5302 }
5303 ///Bit 3 - Waveform Generation Mode High Bit (Enable Top: *OCRA* for `PWM` modes)
5304 #[inline(always)]
5305 pub fn wgm02(&self) -> WGM02_R {
5306 WGM02_R::new(((self.bits >> 3) & 1) != 0)
5307 }
5308 }
5309 impl W {
5310 ///Bits 0:2 - Clock Select
5311 #[inline(always)]
5312 pub fn cs0(&mut self) -> CS0_W<'_, TCCR0B_SPEC> {
5313 CS0_W::new(self, 0)
5314 }
5315 ///Bit 3 - Waveform Generation Mode High Bit (Enable Top: *OCRA* for `PWM` modes)
5316 #[inline(always)]
5317 pub fn wgm02(&mut self) -> WGM02_W<'_, TCCR0B_SPEC> {
5318 WGM02_W::new(self, 3)
5319 }
5320 ///Bit 6 - Force Output Compare B
5321 #[inline(always)]
5322 pub fn foc0b(&mut self) -> FOC0B_W<'_, TCCR0B_SPEC> {
5323 FOC0B_W::new(self, 6)
5324 }
5325 ///Bit 7 - Force Output Compare A
5326 #[inline(always)]
5327 pub fn foc0a(&mut self) -> FOC0A_W<'_, TCCR0B_SPEC> {
5328 FOC0A_W::new(self, 7)
5329 }
5330 }
5331 /**Timer/Counter Control Register B
5332
5333You can [`read`](crate::Reg::read) this register and get [`tccr0b::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tccr0b::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
5334 pub struct TCCR0B_SPEC;
5335 impl crate::RegisterSpec for TCCR0B_SPEC {
5336 type Ux = u8;
5337 }
5338 ///`read()` method returns [`tccr0b::R`](R) reader structure
5339 impl crate::Readable for TCCR0B_SPEC {}
5340 ///`write(|w| ..)` method takes [`tccr0b::W`](W) writer structure
5341 impl crate::Writable for TCCR0B_SPEC {
5342 type Safety = crate::Unsafe;
5343 }
5344 ///`reset()` method sets TCCR0B to value 0
5345 impl crate::Resettable for TCCR0B_SPEC {}
5346 }
5347 /**TCNT0 (rw) register accessor: Timer/Counter0
5348
5349You can [`read`](crate::Reg::read) this register and get [`tcnt0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcnt0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
5350
5351For information about available fields see [`mod@tcnt0`] module*/
5352 pub type TCNT0 = crate::Reg<tcnt0::TCNT0_SPEC>;
5353 ///Timer/Counter0
5354 pub mod tcnt0 {
5355 ///Register `TCNT0` reader
5356 pub type R = crate::R<TCNT0_SPEC>;
5357 ///Register `TCNT0` writer
5358 pub type W = crate::W<TCNT0_SPEC>;
5359 impl core::fmt::Debug for R {
5360 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
5361 write!(f, "{}", self.bits())
5362 }
5363 }
5364 impl W {}
5365 /**Timer/Counter0
5366
5367You can [`read`](crate::Reg::read) this register and get [`tcnt0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcnt0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
5368 pub struct TCNT0_SPEC;
5369 impl crate::RegisterSpec for TCNT0_SPEC {
5370 type Ux = u8;
5371 }
5372 ///`read()` method returns [`tcnt0::R`](R) reader structure
5373 impl crate::Readable for TCNT0_SPEC {}
5374 ///`write(|w| ..)` method takes [`tcnt0::W`](W) writer structure
5375 impl crate::Writable for TCNT0_SPEC {
5376 type Safety = crate::Safe;
5377 }
5378 ///`reset()` method sets TCNT0 to value 0
5379 impl crate::Resettable for TCNT0_SPEC {}
5380 }
5381 /**TIFR (rw) register accessor: Timer/Counter0 Interrupt Flag register
5382
5383You can [`read`](crate::Reg::read) this register and get [`tifr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tifr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
5384
5385For information about available fields see [`mod@tifr`] module*/
5386 pub type TIFR = crate::Reg<tifr::TIFR_SPEC>;
5387 ///Timer/Counter0 Interrupt Flag register
5388 pub mod tifr {
5389 ///Register `TIFR` reader
5390 pub type R = crate::R<TIFR_SPEC>;
5391 ///Register `TIFR` writer
5392 pub type W = crate::W<TIFR_SPEC>;
5393 ///Field `TOV0` reader - Timer/Counter0 Overflow Flag
5394 pub type TOV0_R = crate::BitReader;
5395 ///Field `TOV0` writer - Timer/Counter0 Overflow Flag
5396 pub type TOV0_W<'a, REG> = crate::BitWriter<'a, REG>;
5397 ///Field `OCF0B` reader - Timer/Counter0 Output Compare Flag 0B
5398 pub type OCF0B_R = crate::BitReader;
5399 ///Field `OCF0B` writer - Timer/Counter0 Output Compare Flag 0B
5400 pub type OCF0B_W<'a, REG> = crate::BitWriter<'a, REG>;
5401 ///Field `OCF0A` reader - Timer/Counter0 Output Compare Flag 0A
5402 pub type OCF0A_R = crate::BitReader;
5403 ///Field `OCF0A` writer - Timer/Counter0 Output Compare Flag 0A
5404 pub type OCF0A_W<'a, REG> = crate::BitWriter<'a, REG>;
5405 impl R {
5406 ///Bit 1 - Timer/Counter0 Overflow Flag
5407 #[inline(always)]
5408 pub fn tov0(&self) -> TOV0_R {
5409 TOV0_R::new(((self.bits >> 1) & 1) != 0)
5410 }
5411 ///Bit 3 - Timer/Counter0 Output Compare Flag 0B
5412 #[inline(always)]
5413 pub fn ocf0b(&self) -> OCF0B_R {
5414 OCF0B_R::new(((self.bits >> 3) & 1) != 0)
5415 }
5416 ///Bit 4 - Timer/Counter0 Output Compare Flag 0A
5417 #[inline(always)]
5418 pub fn ocf0a(&self) -> OCF0A_R {
5419 OCF0A_R::new(((self.bits >> 4) & 1) != 0)
5420 }
5421 }
5422 impl W {
5423 ///Bit 1 - Timer/Counter0 Overflow Flag
5424 #[inline(always)]
5425 pub fn tov0(&mut self) -> TOV0_W<'_, TIFR_SPEC> {
5426 TOV0_W::new(self, 1)
5427 }
5428 ///Bit 3 - Timer/Counter0 Output Compare Flag 0B
5429 #[inline(always)]
5430 pub fn ocf0b(&mut self) -> OCF0B_W<'_, TIFR_SPEC> {
5431 OCF0B_W::new(self, 3)
5432 }
5433 ///Bit 4 - Timer/Counter0 Output Compare Flag 0A
5434 #[inline(always)]
5435 pub fn ocf0a(&mut self) -> OCF0A_W<'_, TIFR_SPEC> {
5436 OCF0A_W::new(self, 4)
5437 }
5438 }
5439 /**Timer/Counter0 Interrupt Flag register
5440
5441You can [`read`](crate::Reg::read) this register and get [`tifr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tifr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
5442 pub struct TIFR_SPEC;
5443 impl crate::RegisterSpec for TIFR_SPEC {
5444 type Ux = u8;
5445 }
5446 ///`read()` method returns [`tifr::R`](R) reader structure
5447 impl crate::Readable for TIFR_SPEC {}
5448 ///`write(|w| ..)` method takes [`tifr::W`](W) writer structure
5449 impl crate::Writable for TIFR_SPEC {
5450 type Safety = crate::Unsafe;
5451 }
5452 ///`reset()` method sets TIFR to value 0
5453 impl crate::Resettable for TIFR_SPEC {}
5454 }
5455 /**TIMSK (rw) register accessor: Timer/Counter Interrupt Mask Register
5456
5457You can [`read`](crate::Reg::read) this register and get [`timsk::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timsk::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
5458
5459For information about available fields see [`mod@timsk`] module*/
5460 pub type TIMSK = crate::Reg<timsk::TIMSK_SPEC>;
5461 ///Timer/Counter Interrupt Mask Register
5462 pub mod timsk {
5463 ///Register `TIMSK` reader
5464 pub type R = crate::R<TIMSK_SPEC>;
5465 ///Register `TIMSK` writer
5466 pub type W = crate::W<TIMSK_SPEC>;
5467 ///Field `TOIE0` reader - Timer/Counter0 Overflow Interrupt Enable
5468 pub type TOIE0_R = crate::BitReader;
5469 ///Field `TOIE0` writer - Timer/Counter0 Overflow Interrupt Enable
5470 pub type TOIE0_W<'a, REG> = crate::BitWriter<'a, REG>;
5471 ///Field `OCIE0B` reader - Timer/Counter0 Output Compare Match B Interrupt Enable
5472 pub type OCIE0B_R = crate::BitReader;
5473 ///Field `OCIE0B` writer - Timer/Counter0 Output Compare Match B Interrupt Enable
5474 pub type OCIE0B_W<'a, REG> = crate::BitWriter<'a, REG>;
5475 ///Field `OCIE0A` reader - Timer/Counter0 Output Compare Match A Interrupt Enable
5476 pub type OCIE0A_R = crate::BitReader;
5477 ///Field `OCIE0A` writer - Timer/Counter0 Output Compare Match A Interrupt Enable
5478 pub type OCIE0A_W<'a, REG> = crate::BitWriter<'a, REG>;
5479 impl R {
5480 ///Bit 1 - Timer/Counter0 Overflow Interrupt Enable
5481 #[inline(always)]
5482 pub fn toie0(&self) -> TOIE0_R {
5483 TOIE0_R::new(((self.bits >> 1) & 1) != 0)
5484 }
5485 ///Bit 3 - Timer/Counter0 Output Compare Match B Interrupt Enable
5486 #[inline(always)]
5487 pub fn ocie0b(&self) -> OCIE0B_R {
5488 OCIE0B_R::new(((self.bits >> 3) & 1) != 0)
5489 }
5490 ///Bit 4 - Timer/Counter0 Output Compare Match A Interrupt Enable
5491 #[inline(always)]
5492 pub fn ocie0a(&self) -> OCIE0A_R {
5493 OCIE0A_R::new(((self.bits >> 4) & 1) != 0)
5494 }
5495 }
5496 impl W {
5497 ///Bit 1 - Timer/Counter0 Overflow Interrupt Enable
5498 #[inline(always)]
5499 pub fn toie0(&mut self) -> TOIE0_W<'_, TIMSK_SPEC> {
5500 TOIE0_W::new(self, 1)
5501 }
5502 ///Bit 3 - Timer/Counter0 Output Compare Match B Interrupt Enable
5503 #[inline(always)]
5504 pub fn ocie0b(&mut self) -> OCIE0B_W<'_, TIMSK_SPEC> {
5505 OCIE0B_W::new(self, 3)
5506 }
5507 ///Bit 4 - Timer/Counter0 Output Compare Match A Interrupt Enable
5508 #[inline(always)]
5509 pub fn ocie0a(&mut self) -> OCIE0A_W<'_, TIMSK_SPEC> {
5510 OCIE0A_W::new(self, 4)
5511 }
5512 }
5513 /**Timer/Counter Interrupt Mask Register
5514
5515You can [`read`](crate::Reg::read) this register and get [`timsk::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timsk::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
5516 pub struct TIMSK_SPEC;
5517 impl crate::RegisterSpec for TIMSK_SPEC {
5518 type Ux = u8;
5519 }
5520 ///`read()` method returns [`timsk::R`](R) reader structure
5521 impl crate::Readable for TIMSK_SPEC {}
5522 ///`write(|w| ..)` method takes [`timsk::W`](W) writer structure
5523 impl crate::Writable for TIMSK_SPEC {
5524 type Safety = crate::Unsafe;
5525 }
5526 ///`reset()` method sets TIMSK to value 0
5527 impl crate::Resettable for TIMSK_SPEC {}
5528 }
5529}
5530///Timer/Counter1, 8-bit
5531pub type TC1 = crate::Periph<tc1::RegisterBlock, 0x43>;
5532impl core::fmt::Debug for TC1 {
5533 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
5534 f.debug_struct("TC1").finish()
5535 }
5536}
5537///Timer/Counter1, 8-bit
5538pub mod tc1 {
5539 #[repr(C)]
5540 ///Register block
5541 pub struct RegisterBlock {
5542 dtps: DTPS,
5543 dt1b: DT1B,
5544 dt1a: DT1A,
5545 _reserved3: [u8; 0x05],
5546 ocr1b: OCR1B,
5547 gtccr: GTCCR,
5548 ocr1c: OCR1C,
5549 ocr1a: OCR1A,
5550 tcnt1: TCNT1,
5551 tccr1: TCCR1,
5552 _reserved9: [u8; 0x07],
5553 tifr: TIFR,
5554 timsk: TIMSK,
5555 }
5556 impl RegisterBlock {
5557 ///0x00 - Dead time prescaler register
5558 #[inline(always)]
5559 pub const fn dtps(&self) -> &DTPS {
5560 &self.dtps
5561 }
5562 ///0x01 - Dead Time Value Register B
5563 #[inline(always)]
5564 pub const fn dt1b(&self) -> &DT1B {
5565 &self.dt1b
5566 }
5567 ///0x02 - Dead Time Value Register A
5568 #[inline(always)]
5569 pub const fn dt1a(&self) -> &DT1A {
5570 &self.dt1a
5571 }
5572 ///0x08 - Output Compare Register B
5573 #[inline(always)]
5574 pub const fn ocr1b(&self) -> &OCR1B {
5575 &self.ocr1b
5576 }
5577 ///0x09 - Timer counter control register
5578 #[inline(always)]
5579 pub const fn gtccr(&self) -> >CCR {
5580 &self.gtccr
5581 }
5582 ///0x0a - Output Compare Register C
5583 #[inline(always)]
5584 pub const fn ocr1c(&self) -> &OCR1C {
5585 &self.ocr1c
5586 }
5587 ///0x0b - Output Compare Register A
5588 #[inline(always)]
5589 pub const fn ocr1a(&self) -> &OCR1A {
5590 &self.ocr1a
5591 }
5592 ///0x0c - Timer/Counter Register
5593 #[inline(always)]
5594 pub const fn tcnt1(&self) -> &TCNT1 {
5595 &self.tcnt1
5596 }
5597 ///0x0d - Timer/Counter Control Register
5598 #[inline(always)]
5599 pub const fn tccr1(&self) -> &TCCR1 {
5600 &self.tccr1
5601 }
5602 ///0x15 - Timer/Counter Interrupt Flag Register
5603 #[inline(always)]
5604 pub const fn tifr(&self) -> &TIFR {
5605 &self.tifr
5606 }
5607 ///0x16 - Timer/Counter Interrupt Mask Register
5608 #[inline(always)]
5609 pub const fn timsk(&self) -> &TIMSK {
5610 &self.timsk
5611 }
5612 }
5613 /**DT1A (rw) register accessor: Dead Time Value Register A
5614
5615You can [`read`](crate::Reg::read) this register and get [`dt1a::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dt1a::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
5616
5617For information about available fields see [`mod@dt1a`] module*/
5618 pub type DT1A = crate::Reg<dt1a::DT1A_SPEC>;
5619 ///Dead Time Value Register A
5620 pub mod dt1a {
5621 ///Register `DT1A` reader
5622 pub type R = crate::R<DT1A_SPEC>;
5623 ///Register `DT1A` writer
5624 pub type W = crate::W<DT1A_SPEC>;
5625 ///Field `DTVL` reader - No Description.
5626 pub type DTVL_R = crate::FieldReader;
5627 ///Field `DTVL` writer - No Description.
5628 pub type DTVL_W<'a, REG> = crate::FieldWriter<'a, REG, 4, u8, crate::Safe>;
5629 ///Field `DTVH` reader - No Description.
5630 pub type DTVH_R = crate::FieldReader;
5631 ///Field `DTVH` writer - No Description.
5632 pub type DTVH_W<'a, REG> = crate::FieldWriter<'a, REG, 4, u8, crate::Safe>;
5633 impl R {
5634 ///Bits 0:3 - No Description.
5635 #[inline(always)]
5636 pub fn dtvl(&self) -> DTVL_R {
5637 DTVL_R::new(self.bits & 0x0f)
5638 }
5639 ///Bits 4:7 - No Description.
5640 #[inline(always)]
5641 pub fn dtvh(&self) -> DTVH_R {
5642 DTVH_R::new((self.bits >> 4) & 0x0f)
5643 }
5644 }
5645 impl W {
5646 ///Bits 0:3 - No Description.
5647 #[inline(always)]
5648 pub fn dtvl(&mut self) -> DTVL_W<'_, DT1A_SPEC> {
5649 DTVL_W::new(self, 0)
5650 }
5651 ///Bits 4:7 - No Description.
5652 #[inline(always)]
5653 pub fn dtvh(&mut self) -> DTVH_W<'_, DT1A_SPEC> {
5654 DTVH_W::new(self, 4)
5655 }
5656 }
5657 /**Dead Time Value Register A
5658
5659You can [`read`](crate::Reg::read) this register and get [`dt1a::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dt1a::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
5660 pub struct DT1A_SPEC;
5661 impl crate::RegisterSpec for DT1A_SPEC {
5662 type Ux = u8;
5663 }
5664 ///`read()` method returns [`dt1a::R`](R) reader structure
5665 impl crate::Readable for DT1A_SPEC {}
5666 ///`write(|w| ..)` method takes [`dt1a::W`](W) writer structure
5667 impl crate::Writable for DT1A_SPEC {
5668 type Safety = crate::Unsafe;
5669 }
5670 ///`reset()` method sets DT1A to value 0
5671 impl crate::Resettable for DT1A_SPEC {}
5672 }
5673 /**DT1B (rw) register accessor: Dead Time Value Register B
5674
5675You can [`read`](crate::Reg::read) this register and get [`dt1b::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dt1b::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
5676
5677For information about available fields see [`mod@dt1b`] module*/
5678 pub type DT1B = crate::Reg<dt1b::DT1B_SPEC>;
5679 ///Dead Time Value Register B
5680 pub mod dt1b {
5681 ///Register `DT1B` reader
5682 pub type R = crate::R<DT1B_SPEC>;
5683 ///Register `DT1B` writer
5684 pub type W = crate::W<DT1B_SPEC>;
5685 ///Field `DTVL` reader - No Description.
5686 pub type DTVL_R = crate::FieldReader;
5687 ///Field `DTVL` writer - No Description.
5688 pub type DTVL_W<'a, REG> = crate::FieldWriter<'a, REG, 4, u8, crate::Safe>;
5689 ///Field `DTVH` reader - No Description.
5690 pub type DTVH_R = crate::FieldReader;
5691 ///Field `DTVH` writer - No Description.
5692 pub type DTVH_W<'a, REG> = crate::FieldWriter<'a, REG, 4, u8, crate::Safe>;
5693 impl R {
5694 ///Bits 0:3 - No Description.
5695 #[inline(always)]
5696 pub fn dtvl(&self) -> DTVL_R {
5697 DTVL_R::new(self.bits & 0x0f)
5698 }
5699 ///Bits 4:7 - No Description.
5700 #[inline(always)]
5701 pub fn dtvh(&self) -> DTVH_R {
5702 DTVH_R::new((self.bits >> 4) & 0x0f)
5703 }
5704 }
5705 impl W {
5706 ///Bits 0:3 - No Description.
5707 #[inline(always)]
5708 pub fn dtvl(&mut self) -> DTVL_W<'_, DT1B_SPEC> {
5709 DTVL_W::new(self, 0)
5710 }
5711 ///Bits 4:7 - No Description.
5712 #[inline(always)]
5713 pub fn dtvh(&mut self) -> DTVH_W<'_, DT1B_SPEC> {
5714 DTVH_W::new(self, 4)
5715 }
5716 }
5717 /**Dead Time Value Register B
5718
5719You can [`read`](crate::Reg::read) this register and get [`dt1b::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dt1b::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
5720 pub struct DT1B_SPEC;
5721 impl crate::RegisterSpec for DT1B_SPEC {
5722 type Ux = u8;
5723 }
5724 ///`read()` method returns [`dt1b::R`](R) reader structure
5725 impl crate::Readable for DT1B_SPEC {}
5726 ///`write(|w| ..)` method takes [`dt1b::W`](W) writer structure
5727 impl crate::Writable for DT1B_SPEC {
5728 type Safety = crate::Unsafe;
5729 }
5730 ///`reset()` method sets DT1B to value 0
5731 impl crate::Resettable for DT1B_SPEC {}
5732 }
5733 /**DTPS (rw) register accessor: Dead time prescaler register
5734
5735You can [`read`](crate::Reg::read) this register and get [`dtps::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dtps::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
5736
5737For information about available fields see [`mod@dtps`] module*/
5738 pub type DTPS = crate::Reg<dtps::DTPS_SPEC>;
5739 ///Dead time prescaler register
5740 pub mod dtps {
5741 ///Register `DTPS` reader
5742 pub type R = crate::R<DTPS_SPEC>;
5743 ///Register `DTPS` writer
5744 pub type W = crate::W<DTPS_SPEC>;
5745 /**No Description.
5746
5747Value on reset: 0*/
5748 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
5749 #[repr(u8)]
5750 pub enum DTPS_A {
5751 ///0: No Prescaling
5752 DIRECT = 0,
5753 ///1: Division factor 2
5754 PRESCALE_2 = 1,
5755 ///2: Division factor 4
5756 PRESCALE_4 = 2,
5757 ///3: Division factor 8
5758 PRESCALE_8 = 3,
5759 }
5760 impl From<DTPS_A> for u8 {
5761 #[inline(always)]
5762 fn from(variant: DTPS_A) -> Self {
5763 variant as _
5764 }
5765 }
5766 impl crate::FieldSpec for DTPS_A {
5767 type Ux = u8;
5768 }
5769 impl crate::IsEnum for DTPS_A {}
5770 ///Field `DTPS` reader - No Description.
5771 pub type DTPS_R = crate::FieldReader<DTPS_A>;
5772 impl DTPS_R {
5773 ///Get enumerated values variant
5774 #[inline(always)]
5775 pub const fn variant(&self) -> DTPS_A {
5776 match self.bits {
5777 0 => DTPS_A::DIRECT,
5778 1 => DTPS_A::PRESCALE_2,
5779 2 => DTPS_A::PRESCALE_4,
5780 3 => DTPS_A::PRESCALE_8,
5781 _ => unreachable!(),
5782 }
5783 }
5784 ///No Prescaling
5785 #[inline(always)]
5786 pub fn is_direct(&self) -> bool {
5787 *self == DTPS_A::DIRECT
5788 }
5789 ///Division factor 2
5790 #[inline(always)]
5791 pub fn is_prescale_2(&self) -> bool {
5792 *self == DTPS_A::PRESCALE_2
5793 }
5794 ///Division factor 4
5795 #[inline(always)]
5796 pub fn is_prescale_4(&self) -> bool {
5797 *self == DTPS_A::PRESCALE_4
5798 }
5799 ///Division factor 8
5800 #[inline(always)]
5801 pub fn is_prescale_8(&self) -> bool {
5802 *self == DTPS_A::PRESCALE_8
5803 }
5804 }
5805 ///Field `DTPS` writer - No Description.
5806 pub type DTPS_W<'a, REG> = crate::FieldWriter<'a, REG, 2, DTPS_A, crate::Safe>;
5807 impl<'a, REG> DTPS_W<'a, REG>
5808 where
5809 REG: crate::Writable + crate::RegisterSpec,
5810 REG::Ux: From<u8>,
5811 {
5812 ///No Prescaling
5813 #[inline(always)]
5814 pub fn direct(self) -> &'a mut crate::W<REG> {
5815 self.variant(DTPS_A::DIRECT)
5816 }
5817 ///Division factor 2
5818 #[inline(always)]
5819 pub fn prescale_2(self) -> &'a mut crate::W<REG> {
5820 self.variant(DTPS_A::PRESCALE_2)
5821 }
5822 ///Division factor 4
5823 #[inline(always)]
5824 pub fn prescale_4(self) -> &'a mut crate::W<REG> {
5825 self.variant(DTPS_A::PRESCALE_4)
5826 }
5827 ///Division factor 8
5828 #[inline(always)]
5829 pub fn prescale_8(self) -> &'a mut crate::W<REG> {
5830 self.variant(DTPS_A::PRESCALE_8)
5831 }
5832 }
5833 impl R {
5834 ///Bits 0:1 - No Description.
5835 #[inline(always)]
5836 pub fn dtps(&self) -> DTPS_R {
5837 DTPS_R::new(self.bits & 3)
5838 }
5839 }
5840 impl W {
5841 ///Bits 0:1 - No Description.
5842 #[inline(always)]
5843 pub fn dtps(&mut self) -> DTPS_W<'_, DTPS_SPEC> {
5844 DTPS_W::new(self, 0)
5845 }
5846 }
5847 /**Dead time prescaler register
5848
5849You can [`read`](crate::Reg::read) this register and get [`dtps::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dtps::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
5850 pub struct DTPS_SPEC;
5851 impl crate::RegisterSpec for DTPS_SPEC {
5852 type Ux = u8;
5853 }
5854 ///`read()` method returns [`dtps::R`](R) reader structure
5855 impl crate::Readable for DTPS_SPEC {}
5856 ///`write(|w| ..)` method takes [`dtps::W`](W) writer structure
5857 impl crate::Writable for DTPS_SPEC {
5858 type Safety = crate::Unsafe;
5859 }
5860 ///`reset()` method sets DTPS to value 0
5861 impl crate::Resettable for DTPS_SPEC {}
5862 }
5863 /**GTCCR (rw) register accessor: Timer counter control register
5864
5865You can [`read`](crate::Reg::read) this register and get [`gtccr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gtccr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
5866
5867For information about available fields see [`mod@gtccr`] module*/
5868 pub type GTCCR = crate::Reg<gtccr::GTCCR_SPEC>;
5869 ///Timer counter control register
5870 pub mod gtccr {
5871 ///Register `GTCCR` reader
5872 pub type R = crate::R<GTCCR_SPEC>;
5873 ///Register `GTCCR` writer
5874 pub type W = crate::W<GTCCR_SPEC>;
5875 ///Field `PSR1` reader - Prescaler Reset Timer/Counter1
5876 pub type PSR1_R = crate::BitReader;
5877 ///Field `PSR1` writer - Prescaler Reset Timer/Counter1
5878 pub type PSR1_W<'a, REG> = crate::BitWriter<'a, REG>;
5879 ///Field `FOC1A` writer - Force Output Compare 1A
5880 pub type FOC1A_W<'a, REG> = crate::BitWriter<'a, REG>;
5881 ///Field `FOC1B` writer - Force Output Compare Match 1B
5882 pub type FOC1B_W<'a, REG> = crate::BitWriter<'a, REG>;
5883 /**Comparator B Output Mode
5884
5885Value on reset: 0*/
5886 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
5887 #[repr(u8)]
5888 pub enum COM1B_A {
5889 ///0: Normal port operation, OCix disconnected
5890 DISCONNECTED = 0,
5891 ///1: Toggle OCix on Compare Match
5892 MATCH_TOGGLE = 1,
5893 ///2: Clear OCix on Compare Match
5894 MATCH_CLEAR = 2,
5895 ///3: Set OCix on Compare Match
5896 MATCH_SET = 3,
5897 }
5898 impl From<COM1B_A> for u8 {
5899 #[inline(always)]
5900 fn from(variant: COM1B_A) -> Self {
5901 variant as _
5902 }
5903 }
5904 impl crate::FieldSpec for COM1B_A {
5905 type Ux = u8;
5906 }
5907 impl crate::IsEnum for COM1B_A {}
5908 ///Field `COM1B` reader - Comparator B Output Mode
5909 pub type COM1B_R = crate::FieldReader<COM1B_A>;
5910 impl COM1B_R {
5911 ///Get enumerated values variant
5912 #[inline(always)]
5913 pub const fn variant(&self) -> COM1B_A {
5914 match self.bits {
5915 0 => COM1B_A::DISCONNECTED,
5916 1 => COM1B_A::MATCH_TOGGLE,
5917 2 => COM1B_A::MATCH_CLEAR,
5918 3 => COM1B_A::MATCH_SET,
5919 _ => unreachable!(),
5920 }
5921 }
5922 ///Normal port operation, OCix disconnected
5923 #[inline(always)]
5924 pub fn is_disconnected(&self) -> bool {
5925 *self == COM1B_A::DISCONNECTED
5926 }
5927 ///Toggle OCix on Compare Match
5928 #[inline(always)]
5929 pub fn is_match_toggle(&self) -> bool {
5930 *self == COM1B_A::MATCH_TOGGLE
5931 }
5932 ///Clear OCix on Compare Match
5933 #[inline(always)]
5934 pub fn is_match_clear(&self) -> bool {
5935 *self == COM1B_A::MATCH_CLEAR
5936 }
5937 ///Set OCix on Compare Match
5938 #[inline(always)]
5939 pub fn is_match_set(&self) -> bool {
5940 *self == COM1B_A::MATCH_SET
5941 }
5942 }
5943 ///Field `COM1B` writer - Comparator B Output Mode
5944 pub type COM1B_W<'a, REG> = crate::FieldWriter<'a, REG, 2, COM1B_A, crate::Safe>;
5945 impl<'a, REG> COM1B_W<'a, REG>
5946 where
5947 REG: crate::Writable + crate::RegisterSpec,
5948 REG::Ux: From<u8>,
5949 {
5950 ///Normal port operation, OCix disconnected
5951 #[inline(always)]
5952 pub fn disconnected(self) -> &'a mut crate::W<REG> {
5953 self.variant(COM1B_A::DISCONNECTED)
5954 }
5955 ///Toggle OCix on Compare Match
5956 #[inline(always)]
5957 pub fn match_toggle(self) -> &'a mut crate::W<REG> {
5958 self.variant(COM1B_A::MATCH_TOGGLE)
5959 }
5960 ///Clear OCix on Compare Match
5961 #[inline(always)]
5962 pub fn match_clear(self) -> &'a mut crate::W<REG> {
5963 self.variant(COM1B_A::MATCH_CLEAR)
5964 }
5965 ///Set OCix on Compare Match
5966 #[inline(always)]
5967 pub fn match_set(self) -> &'a mut crate::W<REG> {
5968 self.variant(COM1B_A::MATCH_SET)
5969 }
5970 }
5971 ///Field `PWM1B` reader - Pulse Width Modulator B Enable
5972 pub type PWM1B_R = crate::BitReader;
5973 ///Field `PWM1B` writer - Pulse Width Modulator B Enable
5974 pub type PWM1B_W<'a, REG> = crate::BitWriter<'a, REG>;
5975 impl R {
5976 ///Bit 1 - Prescaler Reset Timer/Counter1
5977 #[inline(always)]
5978 pub fn psr1(&self) -> PSR1_R {
5979 PSR1_R::new(((self.bits >> 1) & 1) != 0)
5980 }
5981 ///Bits 4:5 - Comparator B Output Mode
5982 #[inline(always)]
5983 pub fn com1b(&self) -> COM1B_R {
5984 COM1B_R::new((self.bits >> 4) & 3)
5985 }
5986 ///Bit 6 - Pulse Width Modulator B Enable
5987 #[inline(always)]
5988 pub fn pwm1b(&self) -> PWM1B_R {
5989 PWM1B_R::new(((self.bits >> 6) & 1) != 0)
5990 }
5991 }
5992 impl W {
5993 ///Bit 1 - Prescaler Reset Timer/Counter1
5994 #[inline(always)]
5995 pub fn psr1(&mut self) -> PSR1_W<'_, GTCCR_SPEC> {
5996 PSR1_W::new(self, 1)
5997 }
5998 ///Bit 2 - Force Output Compare 1A
5999 #[inline(always)]
6000 pub fn foc1a(&mut self) -> FOC1A_W<'_, GTCCR_SPEC> {
6001 FOC1A_W::new(self, 2)
6002 }
6003 ///Bit 3 - Force Output Compare Match 1B
6004 #[inline(always)]
6005 pub fn foc1b(&mut self) -> FOC1B_W<'_, GTCCR_SPEC> {
6006 FOC1B_W::new(self, 3)
6007 }
6008 ///Bits 4:5 - Comparator B Output Mode
6009 #[inline(always)]
6010 pub fn com1b(&mut self) -> COM1B_W<'_, GTCCR_SPEC> {
6011 COM1B_W::new(self, 4)
6012 }
6013 ///Bit 6 - Pulse Width Modulator B Enable
6014 #[inline(always)]
6015 pub fn pwm1b(&mut self) -> PWM1B_W<'_, GTCCR_SPEC> {
6016 PWM1B_W::new(self, 6)
6017 }
6018 }
6019 /**Timer counter control register
6020
6021You can [`read`](crate::Reg::read) this register and get [`gtccr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gtccr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
6022 pub struct GTCCR_SPEC;
6023 impl crate::RegisterSpec for GTCCR_SPEC {
6024 type Ux = u8;
6025 }
6026 ///`read()` method returns [`gtccr::R`](R) reader structure
6027 impl crate::Readable for GTCCR_SPEC {}
6028 ///`write(|w| ..)` method takes [`gtccr::W`](W) writer structure
6029 impl crate::Writable for GTCCR_SPEC {
6030 type Safety = crate::Unsafe;
6031 }
6032 ///`reset()` method sets GTCCR to value 0
6033 impl crate::Resettable for GTCCR_SPEC {}
6034 }
6035 /**OCR1A (rw) register accessor: Output Compare Register A
6036
6037You can [`read`](crate::Reg::read) this register and get [`ocr1a::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ocr1a::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
6038
6039For information about available fields see [`mod@ocr1a`] module*/
6040 pub type OCR1A = crate::Reg<ocr1a::OCR1A_SPEC>;
6041 ///Output Compare Register A
6042 pub mod ocr1a {
6043 ///Register `OCR1A` reader
6044 pub type R = crate::R<OCR1A_SPEC>;
6045 ///Register `OCR1A` writer
6046 pub type W = crate::W<OCR1A_SPEC>;
6047 impl core::fmt::Debug for R {
6048 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
6049 write!(f, "{}", self.bits())
6050 }
6051 }
6052 impl W {}
6053 /**Output Compare Register A
6054
6055You can [`read`](crate::Reg::read) this register and get [`ocr1a::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ocr1a::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
6056 pub struct OCR1A_SPEC;
6057 impl crate::RegisterSpec for OCR1A_SPEC {
6058 type Ux = u8;
6059 }
6060 ///`read()` method returns [`ocr1a::R`](R) reader structure
6061 impl crate::Readable for OCR1A_SPEC {}
6062 ///`write(|w| ..)` method takes [`ocr1a::W`](W) writer structure
6063 impl crate::Writable for OCR1A_SPEC {
6064 type Safety = crate::Safe;
6065 }
6066 ///`reset()` method sets OCR1A to value 0
6067 impl crate::Resettable for OCR1A_SPEC {}
6068 }
6069 /**OCR1B (rw) register accessor: Output Compare Register B
6070
6071You can [`read`](crate::Reg::read) this register and get [`ocr1b::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ocr1b::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
6072
6073For information about available fields see [`mod@ocr1b`] module*/
6074 pub type OCR1B = crate::Reg<ocr1b::OCR1B_SPEC>;
6075 ///Output Compare Register B
6076 pub mod ocr1b {
6077 ///Register `OCR1B` reader
6078 pub type R = crate::R<OCR1B_SPEC>;
6079 ///Register `OCR1B` writer
6080 pub type W = crate::W<OCR1B_SPEC>;
6081 impl core::fmt::Debug for R {
6082 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
6083 write!(f, "{}", self.bits())
6084 }
6085 }
6086 impl W {}
6087 /**Output Compare Register B
6088
6089You can [`read`](crate::Reg::read) this register and get [`ocr1b::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ocr1b::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
6090 pub struct OCR1B_SPEC;
6091 impl crate::RegisterSpec for OCR1B_SPEC {
6092 type Ux = u8;
6093 }
6094 ///`read()` method returns [`ocr1b::R`](R) reader structure
6095 impl crate::Readable for OCR1B_SPEC {}
6096 ///`write(|w| ..)` method takes [`ocr1b::W`](W) writer structure
6097 impl crate::Writable for OCR1B_SPEC {
6098 type Safety = crate::Safe;
6099 }
6100 ///`reset()` method sets OCR1B to value 0
6101 impl crate::Resettable for OCR1B_SPEC {}
6102 }
6103 /**OCR1C (rw) register accessor: Output Compare Register C
6104
6105You can [`read`](crate::Reg::read) this register and get [`ocr1c::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ocr1c::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
6106
6107For information about available fields see [`mod@ocr1c`] module*/
6108 pub type OCR1C = crate::Reg<ocr1c::OCR1C_SPEC>;
6109 ///Output Compare Register C
6110 pub mod ocr1c {
6111 ///Register `OCR1C` reader
6112 pub type R = crate::R<OCR1C_SPEC>;
6113 ///Register `OCR1C` writer
6114 pub type W = crate::W<OCR1C_SPEC>;
6115 impl core::fmt::Debug for R {
6116 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
6117 write!(f, "{}", self.bits())
6118 }
6119 }
6120 impl W {}
6121 /**Output Compare Register C
6122
6123You can [`read`](crate::Reg::read) this register and get [`ocr1c::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ocr1c::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
6124 pub struct OCR1C_SPEC;
6125 impl crate::RegisterSpec for OCR1C_SPEC {
6126 type Ux = u8;
6127 }
6128 ///`read()` method returns [`ocr1c::R`](R) reader structure
6129 impl crate::Readable for OCR1C_SPEC {}
6130 ///`write(|w| ..)` method takes [`ocr1c::W`](W) writer structure
6131 impl crate::Writable for OCR1C_SPEC {
6132 type Safety = crate::Safe;
6133 }
6134 ///`reset()` method sets OCR1C to value 0
6135 impl crate::Resettable for OCR1C_SPEC {}
6136 }
6137 /**TCCR1 (rw) register accessor: Timer/Counter Control Register
6138
6139You can [`read`](crate::Reg::read) this register and get [`tccr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tccr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
6140
6141For information about available fields see [`mod@tccr1`] module*/
6142 pub type TCCR1 = crate::Reg<tccr1::TCCR1_SPEC>;
6143 ///Timer/Counter Control Register
6144 pub mod tccr1 {
6145 ///Register `TCCR1` reader
6146 pub type R = crate::R<TCCR1_SPEC>;
6147 ///Register `TCCR1` writer
6148 pub type W = crate::W<TCCR1_SPEC>;
6149 /**Clock Select Bits
6150
6151Value on reset: 0*/
6152 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
6153 #[repr(u8)]
6154 pub enum CS1_A {
6155 ///0: No clock source (Timer/Counter stopped)
6156 NO_CLOCK = 0,
6157 ///1: Running, No Prescaling
6158 DIRECT = 1,
6159 ///2: Running, CLK/2
6160 PRESCALE_2 = 2,
6161 ///3: Running, CLK/4
6162 PRESCALE_4 = 3,
6163 ///4: Running, CLK/8
6164 PRESCALE_8 = 4,
6165 ///5: Running, CLK/16
6166 PRESCALE_16 = 5,
6167 ///6: Running, CLK/32
6168 PRESCALE_32 = 6,
6169 ///7: Running, CLK/64
6170 PRESCALE_64 = 7,
6171 ///8: Running, CLK/128
6172 PRESCALE_128 = 8,
6173 ///9: Running, CLK/256
6174 PRESCALE_256 = 9,
6175 ///10: Running, CLK/512
6176 PRESCALE_512 = 10,
6177 ///11: Running, CLK/1024
6178 PRESCALE_1024 = 11,
6179 ///12: Running, CLK/2048
6180 PRESCALE_2048 = 12,
6181 ///13: Running, CLK/4096
6182 PRESCALE_4096 = 13,
6183 ///14: Running, CLK/8192
6184 PRESCALE_8192 = 14,
6185 ///15: Running, CLK/16384
6186 PRESCALE_16384 = 15,
6187 }
6188 impl From<CS1_A> for u8 {
6189 #[inline(always)]
6190 fn from(variant: CS1_A) -> Self {
6191 variant as _
6192 }
6193 }
6194 impl crate::FieldSpec for CS1_A {
6195 type Ux = u8;
6196 }
6197 impl crate::IsEnum for CS1_A {}
6198 ///Field `CS1` reader - Clock Select Bits
6199 pub type CS1_R = crate::FieldReader<CS1_A>;
6200 impl CS1_R {
6201 ///Get enumerated values variant
6202 #[inline(always)]
6203 pub const fn variant(&self) -> CS1_A {
6204 match self.bits {
6205 0 => CS1_A::NO_CLOCK,
6206 1 => CS1_A::DIRECT,
6207 2 => CS1_A::PRESCALE_2,
6208 3 => CS1_A::PRESCALE_4,
6209 4 => CS1_A::PRESCALE_8,
6210 5 => CS1_A::PRESCALE_16,
6211 6 => CS1_A::PRESCALE_32,
6212 7 => CS1_A::PRESCALE_64,
6213 8 => CS1_A::PRESCALE_128,
6214 9 => CS1_A::PRESCALE_256,
6215 10 => CS1_A::PRESCALE_512,
6216 11 => CS1_A::PRESCALE_1024,
6217 12 => CS1_A::PRESCALE_2048,
6218 13 => CS1_A::PRESCALE_4096,
6219 14 => CS1_A::PRESCALE_8192,
6220 15 => CS1_A::PRESCALE_16384,
6221 _ => unreachable!(),
6222 }
6223 }
6224 ///No clock source (Timer/Counter stopped)
6225 #[inline(always)]
6226 pub fn is_no_clock(&self) -> bool {
6227 *self == CS1_A::NO_CLOCK
6228 }
6229 ///Running, No Prescaling
6230 #[inline(always)]
6231 pub fn is_direct(&self) -> bool {
6232 *self == CS1_A::DIRECT
6233 }
6234 ///Running, CLK/2
6235 #[inline(always)]
6236 pub fn is_prescale_2(&self) -> bool {
6237 *self == CS1_A::PRESCALE_2
6238 }
6239 ///Running, CLK/4
6240 #[inline(always)]
6241 pub fn is_prescale_4(&self) -> bool {
6242 *self == CS1_A::PRESCALE_4
6243 }
6244 ///Running, CLK/8
6245 #[inline(always)]
6246 pub fn is_prescale_8(&self) -> bool {
6247 *self == CS1_A::PRESCALE_8
6248 }
6249 ///Running, CLK/16
6250 #[inline(always)]
6251 pub fn is_prescale_16(&self) -> bool {
6252 *self == CS1_A::PRESCALE_16
6253 }
6254 ///Running, CLK/32
6255 #[inline(always)]
6256 pub fn is_prescale_32(&self) -> bool {
6257 *self == CS1_A::PRESCALE_32
6258 }
6259 ///Running, CLK/64
6260 #[inline(always)]
6261 pub fn is_prescale_64(&self) -> bool {
6262 *self == CS1_A::PRESCALE_64
6263 }
6264 ///Running, CLK/128
6265 #[inline(always)]
6266 pub fn is_prescale_128(&self) -> bool {
6267 *self == CS1_A::PRESCALE_128
6268 }
6269 ///Running, CLK/256
6270 #[inline(always)]
6271 pub fn is_prescale_256(&self) -> bool {
6272 *self == CS1_A::PRESCALE_256
6273 }
6274 ///Running, CLK/512
6275 #[inline(always)]
6276 pub fn is_prescale_512(&self) -> bool {
6277 *self == CS1_A::PRESCALE_512
6278 }
6279 ///Running, CLK/1024
6280 #[inline(always)]
6281 pub fn is_prescale_1024(&self) -> bool {
6282 *self == CS1_A::PRESCALE_1024
6283 }
6284 ///Running, CLK/2048
6285 #[inline(always)]
6286 pub fn is_prescale_2048(&self) -> bool {
6287 *self == CS1_A::PRESCALE_2048
6288 }
6289 ///Running, CLK/4096
6290 #[inline(always)]
6291 pub fn is_prescale_4096(&self) -> bool {
6292 *self == CS1_A::PRESCALE_4096
6293 }
6294 ///Running, CLK/8192
6295 #[inline(always)]
6296 pub fn is_prescale_8192(&self) -> bool {
6297 *self == CS1_A::PRESCALE_8192
6298 }
6299 ///Running, CLK/16384
6300 #[inline(always)]
6301 pub fn is_prescale_16384(&self) -> bool {
6302 *self == CS1_A::PRESCALE_16384
6303 }
6304 }
6305 ///Field `CS1` writer - Clock Select Bits
6306 pub type CS1_W<'a, REG> = crate::FieldWriter<'a, REG, 4, CS1_A, crate::Safe>;
6307 impl<'a, REG> CS1_W<'a, REG>
6308 where
6309 REG: crate::Writable + crate::RegisterSpec,
6310 REG::Ux: From<u8>,
6311 {
6312 ///No clock source (Timer/Counter stopped)
6313 #[inline(always)]
6314 pub fn no_clock(self) -> &'a mut crate::W<REG> {
6315 self.variant(CS1_A::NO_CLOCK)
6316 }
6317 ///Running, No Prescaling
6318 #[inline(always)]
6319 pub fn direct(self) -> &'a mut crate::W<REG> {
6320 self.variant(CS1_A::DIRECT)
6321 }
6322 ///Running, CLK/2
6323 #[inline(always)]
6324 pub fn prescale_2(self) -> &'a mut crate::W<REG> {
6325 self.variant(CS1_A::PRESCALE_2)
6326 }
6327 ///Running, CLK/4
6328 #[inline(always)]
6329 pub fn prescale_4(self) -> &'a mut crate::W<REG> {
6330 self.variant(CS1_A::PRESCALE_4)
6331 }
6332 ///Running, CLK/8
6333 #[inline(always)]
6334 pub fn prescale_8(self) -> &'a mut crate::W<REG> {
6335 self.variant(CS1_A::PRESCALE_8)
6336 }
6337 ///Running, CLK/16
6338 #[inline(always)]
6339 pub fn prescale_16(self) -> &'a mut crate::W<REG> {
6340 self.variant(CS1_A::PRESCALE_16)
6341 }
6342 ///Running, CLK/32
6343 #[inline(always)]
6344 pub fn prescale_32(self) -> &'a mut crate::W<REG> {
6345 self.variant(CS1_A::PRESCALE_32)
6346 }
6347 ///Running, CLK/64
6348 #[inline(always)]
6349 pub fn prescale_64(self) -> &'a mut crate::W<REG> {
6350 self.variant(CS1_A::PRESCALE_64)
6351 }
6352 ///Running, CLK/128
6353 #[inline(always)]
6354 pub fn prescale_128(self) -> &'a mut crate::W<REG> {
6355 self.variant(CS1_A::PRESCALE_128)
6356 }
6357 ///Running, CLK/256
6358 #[inline(always)]
6359 pub fn prescale_256(self) -> &'a mut crate::W<REG> {
6360 self.variant(CS1_A::PRESCALE_256)
6361 }
6362 ///Running, CLK/512
6363 #[inline(always)]
6364 pub fn prescale_512(self) -> &'a mut crate::W<REG> {
6365 self.variant(CS1_A::PRESCALE_512)
6366 }
6367 ///Running, CLK/1024
6368 #[inline(always)]
6369 pub fn prescale_1024(self) -> &'a mut crate::W<REG> {
6370 self.variant(CS1_A::PRESCALE_1024)
6371 }
6372 ///Running, CLK/2048
6373 #[inline(always)]
6374 pub fn prescale_2048(self) -> &'a mut crate::W<REG> {
6375 self.variant(CS1_A::PRESCALE_2048)
6376 }
6377 ///Running, CLK/4096
6378 #[inline(always)]
6379 pub fn prescale_4096(self) -> &'a mut crate::W<REG> {
6380 self.variant(CS1_A::PRESCALE_4096)
6381 }
6382 ///Running, CLK/8192
6383 #[inline(always)]
6384 pub fn prescale_8192(self) -> &'a mut crate::W<REG> {
6385 self.variant(CS1_A::PRESCALE_8192)
6386 }
6387 ///Running, CLK/16384
6388 #[inline(always)]
6389 pub fn prescale_16384(self) -> &'a mut crate::W<REG> {
6390 self.variant(CS1_A::PRESCALE_16384)
6391 }
6392 }
6393 /**Compare Output Mode, Bits
6394
6395Value on reset: 0*/
6396 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
6397 #[repr(u8)]
6398 pub enum COM1A_A {
6399 ///0: Normal port operation, OCix disconnected
6400 DISCONNECTED = 0,
6401 ///1: Toggle OCix on Compare Match
6402 MATCH_TOGGLE = 1,
6403 ///2: Clear OCix on Compare Match
6404 MATCH_CLEAR = 2,
6405 ///3: Set OCix on Compare Match
6406 MATCH_SET = 3,
6407 }
6408 impl From<COM1A_A> for u8 {
6409 #[inline(always)]
6410 fn from(variant: COM1A_A) -> Self {
6411 variant as _
6412 }
6413 }
6414 impl crate::FieldSpec for COM1A_A {
6415 type Ux = u8;
6416 }
6417 impl crate::IsEnum for COM1A_A {}
6418 ///Field `COM1A` reader - Compare Output Mode, Bits
6419 pub type COM1A_R = crate::FieldReader<COM1A_A>;
6420 impl COM1A_R {
6421 ///Get enumerated values variant
6422 #[inline(always)]
6423 pub const fn variant(&self) -> COM1A_A {
6424 match self.bits {
6425 0 => COM1A_A::DISCONNECTED,
6426 1 => COM1A_A::MATCH_TOGGLE,
6427 2 => COM1A_A::MATCH_CLEAR,
6428 3 => COM1A_A::MATCH_SET,
6429 _ => unreachable!(),
6430 }
6431 }
6432 ///Normal port operation, OCix disconnected
6433 #[inline(always)]
6434 pub fn is_disconnected(&self) -> bool {
6435 *self == COM1A_A::DISCONNECTED
6436 }
6437 ///Toggle OCix on Compare Match
6438 #[inline(always)]
6439 pub fn is_match_toggle(&self) -> bool {
6440 *self == COM1A_A::MATCH_TOGGLE
6441 }
6442 ///Clear OCix on Compare Match
6443 #[inline(always)]
6444 pub fn is_match_clear(&self) -> bool {
6445 *self == COM1A_A::MATCH_CLEAR
6446 }
6447 ///Set OCix on Compare Match
6448 #[inline(always)]
6449 pub fn is_match_set(&self) -> bool {
6450 *self == COM1A_A::MATCH_SET
6451 }
6452 }
6453 ///Field `COM1A` writer - Compare Output Mode, Bits
6454 pub type COM1A_W<'a, REG> = crate::FieldWriter<'a, REG, 2, COM1A_A, crate::Safe>;
6455 impl<'a, REG> COM1A_W<'a, REG>
6456 where
6457 REG: crate::Writable + crate::RegisterSpec,
6458 REG::Ux: From<u8>,
6459 {
6460 ///Normal port operation, OCix disconnected
6461 #[inline(always)]
6462 pub fn disconnected(self) -> &'a mut crate::W<REG> {
6463 self.variant(COM1A_A::DISCONNECTED)
6464 }
6465 ///Toggle OCix on Compare Match
6466 #[inline(always)]
6467 pub fn match_toggle(self) -> &'a mut crate::W<REG> {
6468 self.variant(COM1A_A::MATCH_TOGGLE)
6469 }
6470 ///Clear OCix on Compare Match
6471 #[inline(always)]
6472 pub fn match_clear(self) -> &'a mut crate::W<REG> {
6473 self.variant(COM1A_A::MATCH_CLEAR)
6474 }
6475 ///Set OCix on Compare Match
6476 #[inline(always)]
6477 pub fn match_set(self) -> &'a mut crate::W<REG> {
6478 self.variant(COM1A_A::MATCH_SET)
6479 }
6480 }
6481 ///Field `PWM1A` reader - Pulse Width Modulator Enable
6482 pub type PWM1A_R = crate::BitReader;
6483 ///Field `PWM1A` writer - Pulse Width Modulator Enable
6484 pub type PWM1A_W<'a, REG> = crate::BitWriter<'a, REG>;
6485 ///Field `CTC1` reader - Clear Timer/Counter on Compare Match
6486 pub type CTC1_R = crate::BitReader;
6487 ///Field `CTC1` writer - Clear Timer/Counter on Compare Match
6488 pub type CTC1_W<'a, REG> = crate::BitWriter<'a, REG>;
6489 impl R {
6490 ///Bits 0:3 - Clock Select Bits
6491 #[inline(always)]
6492 pub fn cs1(&self) -> CS1_R {
6493 CS1_R::new(self.bits & 0x0f)
6494 }
6495 ///Bits 4:5 - Compare Output Mode, Bits
6496 #[inline(always)]
6497 pub fn com1a(&self) -> COM1A_R {
6498 COM1A_R::new((self.bits >> 4) & 3)
6499 }
6500 ///Bit 6 - Pulse Width Modulator Enable
6501 #[inline(always)]
6502 pub fn pwm1a(&self) -> PWM1A_R {
6503 PWM1A_R::new(((self.bits >> 6) & 1) != 0)
6504 }
6505 ///Bit 7 - Clear Timer/Counter on Compare Match
6506 #[inline(always)]
6507 pub fn ctc1(&self) -> CTC1_R {
6508 CTC1_R::new(((self.bits >> 7) & 1) != 0)
6509 }
6510 }
6511 impl W {
6512 ///Bits 0:3 - Clock Select Bits
6513 #[inline(always)]
6514 pub fn cs1(&mut self) -> CS1_W<'_, TCCR1_SPEC> {
6515 CS1_W::new(self, 0)
6516 }
6517 ///Bits 4:5 - Compare Output Mode, Bits
6518 #[inline(always)]
6519 pub fn com1a(&mut self) -> COM1A_W<'_, TCCR1_SPEC> {
6520 COM1A_W::new(self, 4)
6521 }
6522 ///Bit 6 - Pulse Width Modulator Enable
6523 #[inline(always)]
6524 pub fn pwm1a(&mut self) -> PWM1A_W<'_, TCCR1_SPEC> {
6525 PWM1A_W::new(self, 6)
6526 }
6527 ///Bit 7 - Clear Timer/Counter on Compare Match
6528 #[inline(always)]
6529 pub fn ctc1(&mut self) -> CTC1_W<'_, TCCR1_SPEC> {
6530 CTC1_W::new(self, 7)
6531 }
6532 }
6533 /**Timer/Counter Control Register
6534
6535You can [`read`](crate::Reg::read) this register and get [`tccr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tccr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
6536 pub struct TCCR1_SPEC;
6537 impl crate::RegisterSpec for TCCR1_SPEC {
6538 type Ux = u8;
6539 }
6540 ///`read()` method returns [`tccr1::R`](R) reader structure
6541 impl crate::Readable for TCCR1_SPEC {}
6542 ///`write(|w| ..)` method takes [`tccr1::W`](W) writer structure
6543 impl crate::Writable for TCCR1_SPEC {
6544 type Safety = crate::Unsafe;
6545 }
6546 ///`reset()` method sets TCCR1 to value 0
6547 impl crate::Resettable for TCCR1_SPEC {}
6548 }
6549 /**TCNT1 (rw) register accessor: Timer/Counter Register
6550
6551You can [`read`](crate::Reg::read) this register and get [`tcnt1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcnt1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
6552
6553For information about available fields see [`mod@tcnt1`] module*/
6554 pub type TCNT1 = crate::Reg<tcnt1::TCNT1_SPEC>;
6555 ///Timer/Counter Register
6556 pub mod tcnt1 {
6557 ///Register `TCNT1` reader
6558 pub type R = crate::R<TCNT1_SPEC>;
6559 ///Register `TCNT1` writer
6560 pub type W = crate::W<TCNT1_SPEC>;
6561 impl core::fmt::Debug for R {
6562 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
6563 write!(f, "{}", self.bits())
6564 }
6565 }
6566 impl W {}
6567 /**Timer/Counter Register
6568
6569You can [`read`](crate::Reg::read) this register and get [`tcnt1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcnt1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
6570 pub struct TCNT1_SPEC;
6571 impl crate::RegisterSpec for TCNT1_SPEC {
6572 type Ux = u8;
6573 }
6574 ///`read()` method returns [`tcnt1::R`](R) reader structure
6575 impl crate::Readable for TCNT1_SPEC {}
6576 ///`write(|w| ..)` method takes [`tcnt1::W`](W) writer structure
6577 impl crate::Writable for TCNT1_SPEC {
6578 type Safety = crate::Safe;
6579 }
6580 ///`reset()` method sets TCNT1 to value 0
6581 impl crate::Resettable for TCNT1_SPEC {}
6582 }
6583 /**TIFR (rw) register accessor: Timer/Counter Interrupt Flag Register
6584
6585You can [`read`](crate::Reg::read) this register and get [`tifr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tifr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
6586
6587For information about available fields see [`mod@tifr`] module*/
6588 pub type TIFR = crate::Reg<tifr::TIFR_SPEC>;
6589 ///Timer/Counter Interrupt Flag Register
6590 pub mod tifr {
6591 ///Register `TIFR` reader
6592 pub type R = crate::R<TIFR_SPEC>;
6593 ///Register `TIFR` writer
6594 pub type W = crate::W<TIFR_SPEC>;
6595 ///Field `TOV1` reader - Timer/Counter1 Overflow Flag
6596 pub type TOV1_R = crate::BitReader;
6597 ///Field `TOV1` writer - Timer/Counter1 Overflow Flag
6598 pub type TOV1_W<'a, REG> = crate::BitWriter<'a, REG>;
6599 ///Field `OCF1B` reader - Timer/Counter1 Output Compare Flag 1B
6600 pub type OCF1B_R = crate::BitReader;
6601 ///Field `OCF1B` writer - Timer/Counter1 Output Compare Flag 1B
6602 pub type OCF1B_W<'a, REG> = crate::BitWriter<'a, REG>;
6603 ///Field `OCF1A` reader - Timer/Counter1 Output Compare Flag 1A
6604 pub type OCF1A_R = crate::BitReader;
6605 ///Field `OCF1A` writer - Timer/Counter1 Output Compare Flag 1A
6606 pub type OCF1A_W<'a, REG> = crate::BitWriter<'a, REG>;
6607 impl R {
6608 ///Bit 2 - Timer/Counter1 Overflow Flag
6609 #[inline(always)]
6610 pub fn tov1(&self) -> TOV1_R {
6611 TOV1_R::new(((self.bits >> 2) & 1) != 0)
6612 }
6613 ///Bit 5 - Timer/Counter1 Output Compare Flag 1B
6614 #[inline(always)]
6615 pub fn ocf1b(&self) -> OCF1B_R {
6616 OCF1B_R::new(((self.bits >> 5) & 1) != 0)
6617 }
6618 ///Bit 6 - Timer/Counter1 Output Compare Flag 1A
6619 #[inline(always)]
6620 pub fn ocf1a(&self) -> OCF1A_R {
6621 OCF1A_R::new(((self.bits >> 6) & 1) != 0)
6622 }
6623 }
6624 impl W {
6625 ///Bit 2 - Timer/Counter1 Overflow Flag
6626 #[inline(always)]
6627 pub fn tov1(&mut self) -> TOV1_W<'_, TIFR_SPEC> {
6628 TOV1_W::new(self, 2)
6629 }
6630 ///Bit 5 - Timer/Counter1 Output Compare Flag 1B
6631 #[inline(always)]
6632 pub fn ocf1b(&mut self) -> OCF1B_W<'_, TIFR_SPEC> {
6633 OCF1B_W::new(self, 5)
6634 }
6635 ///Bit 6 - Timer/Counter1 Output Compare Flag 1A
6636 #[inline(always)]
6637 pub fn ocf1a(&mut self) -> OCF1A_W<'_, TIFR_SPEC> {
6638 OCF1A_W::new(self, 6)
6639 }
6640 }
6641 /**Timer/Counter Interrupt Flag Register
6642
6643You can [`read`](crate::Reg::read) this register and get [`tifr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tifr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
6644 pub struct TIFR_SPEC;
6645 impl crate::RegisterSpec for TIFR_SPEC {
6646 type Ux = u8;
6647 }
6648 ///`read()` method returns [`tifr::R`](R) reader structure
6649 impl crate::Readable for TIFR_SPEC {}
6650 ///`write(|w| ..)` method takes [`tifr::W`](W) writer structure
6651 impl crate::Writable for TIFR_SPEC {
6652 type Safety = crate::Unsafe;
6653 }
6654 ///`reset()` method sets TIFR to value 0
6655 impl crate::Resettable for TIFR_SPEC {}
6656 }
6657 /**TIMSK (rw) register accessor: Timer/Counter Interrupt Mask Register
6658
6659You can [`read`](crate::Reg::read) this register and get [`timsk::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timsk::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
6660
6661For information about available fields see [`mod@timsk`] module*/
6662 pub type TIMSK = crate::Reg<timsk::TIMSK_SPEC>;
6663 ///Timer/Counter Interrupt Mask Register
6664 pub mod timsk {
6665 ///Register `TIMSK` reader
6666 pub type R = crate::R<TIMSK_SPEC>;
6667 ///Register `TIMSK` writer
6668 pub type W = crate::W<TIMSK_SPEC>;
6669 ///Field `TOIE1` reader - Timer/Counter1 Overflow Interrupt Enable
6670 pub type TOIE1_R = crate::BitReader;
6671 ///Field `TOIE1` writer - Timer/Counter1 Overflow Interrupt Enable
6672 pub type TOIE1_W<'a, REG> = crate::BitWriter<'a, REG>;
6673 ///Field `OCIE1B` reader - OCIE1A: Timer/Counter1 Output Compare B Interrupt Enable
6674 pub type OCIE1B_R = crate::BitReader;
6675 ///Field `OCIE1B` writer - OCIE1A: Timer/Counter1 Output Compare B Interrupt Enable
6676 pub type OCIE1B_W<'a, REG> = crate::BitWriter<'a, REG>;
6677 ///Field `OCIE1A` reader - OCIE1A: Timer/Counter1 Output Compare Interrupt Enable
6678 pub type OCIE1A_R = crate::BitReader;
6679 ///Field `OCIE1A` writer - OCIE1A: Timer/Counter1 Output Compare Interrupt Enable
6680 pub type OCIE1A_W<'a, REG> = crate::BitWriter<'a, REG>;
6681 impl R {
6682 ///Bit 2 - Timer/Counter1 Overflow Interrupt Enable
6683 #[inline(always)]
6684 pub fn toie1(&self) -> TOIE1_R {
6685 TOIE1_R::new(((self.bits >> 2) & 1) != 0)
6686 }
6687 ///Bit 5 - OCIE1A: Timer/Counter1 Output Compare B Interrupt Enable
6688 #[inline(always)]
6689 pub fn ocie1b(&self) -> OCIE1B_R {
6690 OCIE1B_R::new(((self.bits >> 5) & 1) != 0)
6691 }
6692 ///Bit 6 - OCIE1A: Timer/Counter1 Output Compare Interrupt Enable
6693 #[inline(always)]
6694 pub fn ocie1a(&self) -> OCIE1A_R {
6695 OCIE1A_R::new(((self.bits >> 6) & 1) != 0)
6696 }
6697 }
6698 impl W {
6699 ///Bit 2 - Timer/Counter1 Overflow Interrupt Enable
6700 #[inline(always)]
6701 pub fn toie1(&mut self) -> TOIE1_W<'_, TIMSK_SPEC> {
6702 TOIE1_W::new(self, 2)
6703 }
6704 ///Bit 5 - OCIE1A: Timer/Counter1 Output Compare B Interrupt Enable
6705 #[inline(always)]
6706 pub fn ocie1b(&mut self) -> OCIE1B_W<'_, TIMSK_SPEC> {
6707 OCIE1B_W::new(self, 5)
6708 }
6709 ///Bit 6 - OCIE1A: Timer/Counter1 Output Compare Interrupt Enable
6710 #[inline(always)]
6711 pub fn ocie1a(&mut self) -> OCIE1A_W<'_, TIMSK_SPEC> {
6712 OCIE1A_W::new(self, 6)
6713 }
6714 }
6715 /**Timer/Counter Interrupt Mask Register
6716
6717You can [`read`](crate::Reg::read) this register and get [`timsk::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timsk::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
6718 pub struct TIMSK_SPEC;
6719 impl crate::RegisterSpec for TIMSK_SPEC {
6720 type Ux = u8;
6721 }
6722 ///`read()` method returns [`timsk::R`](R) reader structure
6723 impl crate::Readable for TIMSK_SPEC {}
6724 ///`write(|w| ..)` method takes [`timsk::W`](W) writer structure
6725 impl crate::Writable for TIMSK_SPEC {
6726 type Safety = crate::Unsafe;
6727 }
6728 ///`reset()` method sets TIMSK to value 0
6729 impl crate::Resettable for TIMSK_SPEC {}
6730 }
6731}
6732///Universal Serial Interface
6733pub type USI = crate::Periph<usi::RegisterBlock, 0x2d>;
6734impl core::fmt::Debug for USI {
6735 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
6736 f.debug_struct("USI").finish()
6737 }
6738}
6739///Universal Serial Interface
6740pub mod usi {
6741 #[repr(C)]
6742 ///Register block
6743 pub struct RegisterBlock {
6744 usicr: USICR,
6745 usisr: USISR,
6746 usidr: USIDR,
6747 usibr: USIBR,
6748 }
6749 impl RegisterBlock {
6750 ///0x00 - USI Control Register
6751 #[inline(always)]
6752 pub const fn usicr(&self) -> &USICR {
6753 &self.usicr
6754 }
6755 ///0x01 - USI Status Register
6756 #[inline(always)]
6757 pub const fn usisr(&self) -> &USISR {
6758 &self.usisr
6759 }
6760 ///0x02 - USI Data Register
6761 #[inline(always)]
6762 pub const fn usidr(&self) -> &USIDR {
6763 &self.usidr
6764 }
6765 ///0x03 - USI Buffer Register
6766 #[inline(always)]
6767 pub const fn usibr(&self) -> &USIBR {
6768 &self.usibr
6769 }
6770 }
6771 /**USIBR (rw) register accessor: USI Buffer Register
6772
6773You can [`read`](crate::Reg::read) this register and get [`usibr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usibr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
6774
6775For information about available fields see [`mod@usibr`] module*/
6776 pub type USIBR = crate::Reg<usibr::USIBR_SPEC>;
6777 ///USI Buffer Register
6778 pub mod usibr {
6779 ///Register `USIBR` reader
6780 pub type R = crate::R<USIBR_SPEC>;
6781 ///Register `USIBR` writer
6782 pub type W = crate::W<USIBR_SPEC>;
6783 impl core::fmt::Debug for R {
6784 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
6785 write!(f, "{}", self.bits())
6786 }
6787 }
6788 impl W {}
6789 /**USI Buffer Register
6790
6791You can [`read`](crate::Reg::read) this register and get [`usibr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usibr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
6792 pub struct USIBR_SPEC;
6793 impl crate::RegisterSpec for USIBR_SPEC {
6794 type Ux = u8;
6795 }
6796 ///`read()` method returns [`usibr::R`](R) reader structure
6797 impl crate::Readable for USIBR_SPEC {}
6798 ///`write(|w| ..)` method takes [`usibr::W`](W) writer structure
6799 impl crate::Writable for USIBR_SPEC {
6800 type Safety = crate::Safe;
6801 }
6802 ///`reset()` method sets USIBR to value 0
6803 impl crate::Resettable for USIBR_SPEC {}
6804 }
6805 /**USICR (rw) register accessor: USI Control Register
6806
6807You can [`read`](crate::Reg::read) this register and get [`usicr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usicr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
6808
6809For information about available fields see [`mod@usicr`] module*/
6810 pub type USICR = crate::Reg<usicr::USICR_SPEC>;
6811 ///USI Control Register
6812 pub mod usicr {
6813 ///Register `USICR` reader
6814 pub type R = crate::R<USICR_SPEC>;
6815 ///Register `USICR` writer
6816 pub type W = crate::W<USICR_SPEC>;
6817 ///Field `USITC` writer - Toggle Clock Port Pin
6818 pub type USITC_W<'a, REG> = crate::BitWriter<'a, REG>;
6819 ///Field `USICLK` writer - Clock Strobe
6820 pub type USICLK_W<'a, REG> = crate::BitWriter<'a, REG>;
6821 /**USI Clock Source Select Bits
6822
6823Value on reset: 0*/
6824 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
6825 #[repr(u8)]
6826 pub enum USICS_A {
6827 ///0: No Clock/Software clock strobe
6828 NO_CLOCK = 0,
6829 ///1: Timer/Counter0 Compare Match
6830 TC0 = 1,
6831 ///2: External, positive edge
6832 EXT_POS = 2,
6833 ///3: External, negative edge
6834 EXT_NEG = 3,
6835 }
6836 impl From<USICS_A> for u8 {
6837 #[inline(always)]
6838 fn from(variant: USICS_A) -> Self {
6839 variant as _
6840 }
6841 }
6842 impl crate::FieldSpec for USICS_A {
6843 type Ux = u8;
6844 }
6845 impl crate::IsEnum for USICS_A {}
6846 ///Field `USICS` reader - USI Clock Source Select Bits
6847 pub type USICS_R = crate::FieldReader<USICS_A>;
6848 impl USICS_R {
6849 ///Get enumerated values variant
6850 #[inline(always)]
6851 pub const fn variant(&self) -> USICS_A {
6852 match self.bits {
6853 0 => USICS_A::NO_CLOCK,
6854 1 => USICS_A::TC0,
6855 2 => USICS_A::EXT_POS,
6856 3 => USICS_A::EXT_NEG,
6857 _ => unreachable!(),
6858 }
6859 }
6860 ///No Clock/Software clock strobe
6861 #[inline(always)]
6862 pub fn is_no_clock(&self) -> bool {
6863 *self == USICS_A::NO_CLOCK
6864 }
6865 ///Timer/Counter0 Compare Match
6866 #[inline(always)]
6867 pub fn is_tc0(&self) -> bool {
6868 *self == USICS_A::TC0
6869 }
6870 ///External, positive edge
6871 #[inline(always)]
6872 pub fn is_ext_pos(&self) -> bool {
6873 *self == USICS_A::EXT_POS
6874 }
6875 ///External, negative edge
6876 #[inline(always)]
6877 pub fn is_ext_neg(&self) -> bool {
6878 *self == USICS_A::EXT_NEG
6879 }
6880 }
6881 ///Field `USICS` writer - USI Clock Source Select Bits
6882 pub type USICS_W<'a, REG> = crate::FieldWriter<'a, REG, 2, USICS_A, crate::Safe>;
6883 impl<'a, REG> USICS_W<'a, REG>
6884 where
6885 REG: crate::Writable + crate::RegisterSpec,
6886 REG::Ux: From<u8>,
6887 {
6888 ///No Clock/Software clock strobe
6889 #[inline(always)]
6890 pub fn no_clock(self) -> &'a mut crate::W<REG> {
6891 self.variant(USICS_A::NO_CLOCK)
6892 }
6893 ///Timer/Counter0 Compare Match
6894 #[inline(always)]
6895 pub fn tc0(self) -> &'a mut crate::W<REG> {
6896 self.variant(USICS_A::TC0)
6897 }
6898 ///External, positive edge
6899 #[inline(always)]
6900 pub fn ext_pos(self) -> &'a mut crate::W<REG> {
6901 self.variant(USICS_A::EXT_POS)
6902 }
6903 ///External, negative edge
6904 #[inline(always)]
6905 pub fn ext_neg(self) -> &'a mut crate::W<REG> {
6906 self.variant(USICS_A::EXT_NEG)
6907 }
6908 }
6909 /**USI Wire Mode Bits
6910
6911Value on reset: 0*/
6912 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
6913 #[repr(u8)]
6914 pub enum USIWM_A {
6915 ///0: All detectors disabled. Port pins operates as normal.
6916 DISABLED = 0,
6917 ///1: Three-wire mode. Uses DO, DI, and USCK pins.
6918 THREE_WIRE = 1,
6919 ///2: Two-wire mode (Slave). Uses SDA (DI) and SCL (USCK) pins.
6920 TWO_WIRE_SLAVE = 2,
6921 ///3: Two-wire mode (Master). Uses SDA and SCL pins.
6922 TWO_WIRE_MASTER = 3,
6923 }
6924 impl From<USIWM_A> for u8 {
6925 #[inline(always)]
6926 fn from(variant: USIWM_A) -> Self {
6927 variant as _
6928 }
6929 }
6930 impl crate::FieldSpec for USIWM_A {
6931 type Ux = u8;
6932 }
6933 impl crate::IsEnum for USIWM_A {}
6934 ///Field `USIWM` reader - USI Wire Mode Bits
6935 pub type USIWM_R = crate::FieldReader<USIWM_A>;
6936 impl USIWM_R {
6937 ///Get enumerated values variant
6938 #[inline(always)]
6939 pub const fn variant(&self) -> USIWM_A {
6940 match self.bits {
6941 0 => USIWM_A::DISABLED,
6942 1 => USIWM_A::THREE_WIRE,
6943 2 => USIWM_A::TWO_WIRE_SLAVE,
6944 3 => USIWM_A::TWO_WIRE_MASTER,
6945 _ => unreachable!(),
6946 }
6947 }
6948 ///All detectors disabled. Port pins operates as normal.
6949 #[inline(always)]
6950 pub fn is_disabled(&self) -> bool {
6951 *self == USIWM_A::DISABLED
6952 }
6953 ///Three-wire mode. Uses DO, DI, and USCK pins.
6954 #[inline(always)]
6955 pub fn is_three_wire(&self) -> bool {
6956 *self == USIWM_A::THREE_WIRE
6957 }
6958 ///Two-wire mode (Slave). Uses SDA (DI) and SCL (USCK) pins.
6959 #[inline(always)]
6960 pub fn is_two_wire_slave(&self) -> bool {
6961 *self == USIWM_A::TWO_WIRE_SLAVE
6962 }
6963 ///Two-wire mode (Master). Uses SDA and SCL pins.
6964 #[inline(always)]
6965 pub fn is_two_wire_master(&self) -> bool {
6966 *self == USIWM_A::TWO_WIRE_MASTER
6967 }
6968 }
6969 ///Field `USIWM` writer - USI Wire Mode Bits
6970 pub type USIWM_W<'a, REG> = crate::FieldWriter<'a, REG, 2, USIWM_A, crate::Safe>;
6971 impl<'a, REG> USIWM_W<'a, REG>
6972 where
6973 REG: crate::Writable + crate::RegisterSpec,
6974 REG::Ux: From<u8>,
6975 {
6976 ///All detectors disabled. Port pins operates as normal.
6977 #[inline(always)]
6978 pub fn disabled(self) -> &'a mut crate::W<REG> {
6979 self.variant(USIWM_A::DISABLED)
6980 }
6981 ///Three-wire mode. Uses DO, DI, and USCK pins.
6982 #[inline(always)]
6983 pub fn three_wire(self) -> &'a mut crate::W<REG> {
6984 self.variant(USIWM_A::THREE_WIRE)
6985 }
6986 ///Two-wire mode (Slave). Uses SDA (DI) and SCL (USCK) pins.
6987 #[inline(always)]
6988 pub fn two_wire_slave(self) -> &'a mut crate::W<REG> {
6989 self.variant(USIWM_A::TWO_WIRE_SLAVE)
6990 }
6991 ///Two-wire mode (Master). Uses SDA and SCL pins.
6992 #[inline(always)]
6993 pub fn two_wire_master(self) -> &'a mut crate::W<REG> {
6994 self.variant(USIWM_A::TWO_WIRE_MASTER)
6995 }
6996 }
6997 ///Field `USIOIE` reader - Counter Overflow Interrupt Enable
6998 pub type USIOIE_R = crate::BitReader;
6999 ///Field `USIOIE` writer - Counter Overflow Interrupt Enable
7000 pub type USIOIE_W<'a, REG> = crate::BitWriter<'a, REG>;
7001 ///Field `USISIE` reader - Start Condition Interrupt Enable
7002 pub type USISIE_R = crate::BitReader;
7003 ///Field `USISIE` writer - Start Condition Interrupt Enable
7004 pub type USISIE_W<'a, REG> = crate::BitWriter<'a, REG>;
7005 impl R {
7006 ///Bits 2:3 - USI Clock Source Select Bits
7007 #[inline(always)]
7008 pub fn usics(&self) -> USICS_R {
7009 USICS_R::new((self.bits >> 2) & 3)
7010 }
7011 ///Bits 4:5 - USI Wire Mode Bits
7012 #[inline(always)]
7013 pub fn usiwm(&self) -> USIWM_R {
7014 USIWM_R::new((self.bits >> 4) & 3)
7015 }
7016 ///Bit 6 - Counter Overflow Interrupt Enable
7017 #[inline(always)]
7018 pub fn usioie(&self) -> USIOIE_R {
7019 USIOIE_R::new(((self.bits >> 6) & 1) != 0)
7020 }
7021 ///Bit 7 - Start Condition Interrupt Enable
7022 #[inline(always)]
7023 pub fn usisie(&self) -> USISIE_R {
7024 USISIE_R::new(((self.bits >> 7) & 1) != 0)
7025 }
7026 }
7027 impl W {
7028 ///Bit 0 - Toggle Clock Port Pin
7029 #[inline(always)]
7030 pub fn usitc(&mut self) -> USITC_W<'_, USICR_SPEC> {
7031 USITC_W::new(self, 0)
7032 }
7033 ///Bit 1 - Clock Strobe
7034 #[inline(always)]
7035 pub fn usiclk(&mut self) -> USICLK_W<'_, USICR_SPEC> {
7036 USICLK_W::new(self, 1)
7037 }
7038 ///Bits 2:3 - USI Clock Source Select Bits
7039 #[inline(always)]
7040 pub fn usics(&mut self) -> USICS_W<'_, USICR_SPEC> {
7041 USICS_W::new(self, 2)
7042 }
7043 ///Bits 4:5 - USI Wire Mode Bits
7044 #[inline(always)]
7045 pub fn usiwm(&mut self) -> USIWM_W<'_, USICR_SPEC> {
7046 USIWM_W::new(self, 4)
7047 }
7048 ///Bit 6 - Counter Overflow Interrupt Enable
7049 #[inline(always)]
7050 pub fn usioie(&mut self) -> USIOIE_W<'_, USICR_SPEC> {
7051 USIOIE_W::new(self, 6)
7052 }
7053 ///Bit 7 - Start Condition Interrupt Enable
7054 #[inline(always)]
7055 pub fn usisie(&mut self) -> USISIE_W<'_, USICR_SPEC> {
7056 USISIE_W::new(self, 7)
7057 }
7058 }
7059 /**USI Control Register
7060
7061You can [`read`](crate::Reg::read) this register and get [`usicr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usicr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
7062 pub struct USICR_SPEC;
7063 impl crate::RegisterSpec for USICR_SPEC {
7064 type Ux = u8;
7065 }
7066 ///`read()` method returns [`usicr::R`](R) reader structure
7067 impl crate::Readable for USICR_SPEC {}
7068 ///`write(|w| ..)` method takes [`usicr::W`](W) writer structure
7069 impl crate::Writable for USICR_SPEC {
7070 type Safety = crate::Unsafe;
7071 }
7072 ///`reset()` method sets USICR to value 0
7073 impl crate::Resettable for USICR_SPEC {}
7074 }
7075 /**USIDR (rw) register accessor: USI Data Register
7076
7077You can [`read`](crate::Reg::read) this register and get [`usidr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usidr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
7078
7079For information about available fields see [`mod@usidr`] module*/
7080 pub type USIDR = crate::Reg<usidr::USIDR_SPEC>;
7081 ///USI Data Register
7082 pub mod usidr {
7083 ///Register `USIDR` reader
7084 pub type R = crate::R<USIDR_SPEC>;
7085 ///Register `USIDR` writer
7086 pub type W = crate::W<USIDR_SPEC>;
7087 impl core::fmt::Debug for R {
7088 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
7089 write!(f, "{}", self.bits())
7090 }
7091 }
7092 impl W {}
7093 /**USI Data Register
7094
7095You can [`read`](crate::Reg::read) this register and get [`usidr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usidr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
7096 pub struct USIDR_SPEC;
7097 impl crate::RegisterSpec for USIDR_SPEC {
7098 type Ux = u8;
7099 }
7100 ///`read()` method returns [`usidr::R`](R) reader structure
7101 impl crate::Readable for USIDR_SPEC {}
7102 ///`write(|w| ..)` method takes [`usidr::W`](W) writer structure
7103 impl crate::Writable for USIDR_SPEC {
7104 type Safety = crate::Safe;
7105 }
7106 ///`reset()` method sets USIDR to value 0
7107 impl crate::Resettable for USIDR_SPEC {}
7108 }
7109 /**USISR (rw) register accessor: USI Status Register
7110
7111You can [`read`](crate::Reg::read) this register and get [`usisr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usisr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
7112
7113For information about available fields see [`mod@usisr`] module*/
7114 pub type USISR = crate::Reg<usisr::USISR_SPEC>;
7115 ///USI Status Register
7116 pub mod usisr {
7117 ///Register `USISR` reader
7118 pub type R = crate::R<USISR_SPEC>;
7119 ///Register `USISR` writer
7120 pub type W = crate::W<USISR_SPEC>;
7121 ///Field `USICNT` reader - USI Counter Value Bits
7122 pub type USICNT_R = crate::FieldReader;
7123 ///Field `USICNT` writer - USI Counter Value Bits
7124 pub type USICNT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, u8, crate::Safe>;
7125 ///Field `USIDC` reader - Data Output Collision
7126 pub type USIDC_R = crate::BitReader;
7127 ///Field `USIPF` reader - Stop Condition Flag
7128 pub type USIPF_R = crate::BitReader;
7129 ///Field `USIPF` writer - Stop Condition Flag
7130 pub type USIPF_W<'a, REG> = crate::BitWriter<'a, REG>;
7131 ///Field `USIOIF` reader - Counter Overflow Interrupt Flag
7132 pub type USIOIF_R = crate::BitReader;
7133 ///Field `USIOIF` writer - Counter Overflow Interrupt Flag
7134 pub type USIOIF_W<'a, REG> = crate::BitWriter<'a, REG>;
7135 ///Field `USISIF` reader - Start Condition Interrupt Flag
7136 pub type USISIF_R = crate::BitReader;
7137 ///Field `USISIF` writer - Start Condition Interrupt Flag
7138 pub type USISIF_W<'a, REG> = crate::BitWriter<'a, REG>;
7139 impl R {
7140 ///Bits 0:3 - USI Counter Value Bits
7141 #[inline(always)]
7142 pub fn usicnt(&self) -> USICNT_R {
7143 USICNT_R::new(self.bits & 0x0f)
7144 }
7145 ///Bit 4 - Data Output Collision
7146 #[inline(always)]
7147 pub fn usidc(&self) -> USIDC_R {
7148 USIDC_R::new(((self.bits >> 4) & 1) != 0)
7149 }
7150 ///Bit 5 - Stop Condition Flag
7151 #[inline(always)]
7152 pub fn usipf(&self) -> USIPF_R {
7153 USIPF_R::new(((self.bits >> 5) & 1) != 0)
7154 }
7155 ///Bit 6 - Counter Overflow Interrupt Flag
7156 #[inline(always)]
7157 pub fn usioif(&self) -> USIOIF_R {
7158 USIOIF_R::new(((self.bits >> 6) & 1) != 0)
7159 }
7160 ///Bit 7 - Start Condition Interrupt Flag
7161 #[inline(always)]
7162 pub fn usisif(&self) -> USISIF_R {
7163 USISIF_R::new(((self.bits >> 7) & 1) != 0)
7164 }
7165 }
7166 impl W {
7167 ///Bits 0:3 - USI Counter Value Bits
7168 #[inline(always)]
7169 pub fn usicnt(&mut self) -> USICNT_W<'_, USISR_SPEC> {
7170 USICNT_W::new(self, 0)
7171 }
7172 ///Bit 5 - Stop Condition Flag
7173 #[inline(always)]
7174 pub fn usipf(&mut self) -> USIPF_W<'_, USISR_SPEC> {
7175 USIPF_W::new(self, 5)
7176 }
7177 ///Bit 6 - Counter Overflow Interrupt Flag
7178 #[inline(always)]
7179 pub fn usioif(&mut self) -> USIOIF_W<'_, USISR_SPEC> {
7180 USIOIF_W::new(self, 6)
7181 }
7182 ///Bit 7 - Start Condition Interrupt Flag
7183 #[inline(always)]
7184 pub fn usisif(&mut self) -> USISIF_W<'_, USISR_SPEC> {
7185 USISIF_W::new(self, 7)
7186 }
7187 }
7188 /**USI Status Register
7189
7190You can [`read`](crate::Reg::read) this register and get [`usisr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usisr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
7191 pub struct USISR_SPEC;
7192 impl crate::RegisterSpec for USISR_SPEC {
7193 type Ux = u8;
7194 }
7195 ///`read()` method returns [`usisr::R`](R) reader structure
7196 impl crate::Readable for USISR_SPEC {}
7197 ///`write(|w| ..)` method takes [`usisr::W`](W) writer structure
7198 impl crate::Writable for USISR_SPEC {
7199 type Safety = crate::Unsafe;
7200 }
7201 ///`reset()` method sets USISR to value 0
7202 impl crate::Resettable for USISR_SPEC {}
7203 }
7204}
7205///Watchdog Timer
7206pub type WDT = crate::Periph<wdt::RegisterBlock, 0x41>;
7207impl core::fmt::Debug for WDT {
7208 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
7209 f.debug_struct("WDT").finish()
7210 }
7211}
7212///Watchdog Timer
7213pub mod wdt {
7214 #[repr(C)]
7215 ///Register block
7216 pub struct RegisterBlock {
7217 wdtcr: WDTCR,
7218 }
7219 impl RegisterBlock {
7220 ///0x00 - Watchdog Timer Control Register
7221 #[inline(always)]
7222 pub const fn wdtcr(&self) -> &WDTCR {
7223 &self.wdtcr
7224 }
7225 }
7226 /**WDTCR (rw) register accessor: Watchdog Timer Control Register
7227
7228You can [`read`](crate::Reg::read) this register and get [`wdtcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdtcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
7229
7230For information about available fields see [`mod@wdtcr`] module*/
7231 pub type WDTCR = crate::Reg<wdtcr::WDTCR_SPEC>;
7232 ///Watchdog Timer Control Register
7233 pub mod wdtcr {
7234 ///Register `WDTCR` reader
7235 pub type R = crate::R<WDTCR_SPEC>;
7236 ///Register `WDTCR` writer
7237 pub type W = crate::W<WDTCR_SPEC>;
7238 /**Watchdog Timer Prescaler - Low Bits
7239
7240Value on reset: 0*/
7241 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
7242 #[repr(u8)]
7243 pub enum WDPL_A {
7244 ///0: - 2048 cycles, ~16ms/512K (524288) cycles, ~4s if WDPH is set
7245 CYCLES_2K_512K = 0,
7246 ///1: - 4096 cycles, ~32ms/1024K (1048576) cycles, ~8s if WDPH is set
7247 CYCLES_4K_1024K = 1,
7248 ///2: - 8192 cycles, ~64ms
7249 CYCLES_8K = 2,
7250 ///3: - 16K (16384) cycles, ~0.125s
7251 CYCLES_16K = 3,
7252 ///4: - 32K (32768) cycles, ~0.25s
7253 CYCLES_32K = 4,
7254 ///5: - 64K (65536) cycles, ~0.5s
7255 CYCLES_64K = 5,
7256 ///6: - 128K (131072) cycles, ~1s
7257 CYCLES_128K = 6,
7258 ///7: - 256K (262144) cycles, ~2s
7259 CYCLES_256K = 7,
7260 }
7261 impl From<WDPL_A> for u8 {
7262 #[inline(always)]
7263 fn from(variant: WDPL_A) -> Self {
7264 variant as _
7265 }
7266 }
7267 impl crate::FieldSpec for WDPL_A {
7268 type Ux = u8;
7269 }
7270 impl crate::IsEnum for WDPL_A {}
7271 ///Field `WDPL` reader - Watchdog Timer Prescaler - Low Bits
7272 pub type WDPL_R = crate::FieldReader<WDPL_A>;
7273 impl WDPL_R {
7274 ///Get enumerated values variant
7275 #[inline(always)]
7276 pub const fn variant(&self) -> WDPL_A {
7277 match self.bits {
7278 0 => WDPL_A::CYCLES_2K_512K,
7279 1 => WDPL_A::CYCLES_4K_1024K,
7280 2 => WDPL_A::CYCLES_8K,
7281 3 => WDPL_A::CYCLES_16K,
7282 4 => WDPL_A::CYCLES_32K,
7283 5 => WDPL_A::CYCLES_64K,
7284 6 => WDPL_A::CYCLES_128K,
7285 7 => WDPL_A::CYCLES_256K,
7286 _ => unreachable!(),
7287 }
7288 }
7289 ///- 2048 cycles, ~16ms/512K (524288) cycles, ~4s if WDPH is set
7290 #[inline(always)]
7291 pub fn is_cycles_2k_512k(&self) -> bool {
7292 *self == WDPL_A::CYCLES_2K_512K
7293 }
7294 ///- 4096 cycles, ~32ms/1024K (1048576) cycles, ~8s if WDPH is set
7295 #[inline(always)]
7296 pub fn is_cycles_4k_1024k(&self) -> bool {
7297 *self == WDPL_A::CYCLES_4K_1024K
7298 }
7299 ///- 8192 cycles, ~64ms
7300 #[inline(always)]
7301 pub fn is_cycles_8k(&self) -> bool {
7302 *self == WDPL_A::CYCLES_8K
7303 }
7304 ///- 16K (16384) cycles, ~0.125s
7305 #[inline(always)]
7306 pub fn is_cycles_16k(&self) -> bool {
7307 *self == WDPL_A::CYCLES_16K
7308 }
7309 ///- 32K (32768) cycles, ~0.25s
7310 #[inline(always)]
7311 pub fn is_cycles_32k(&self) -> bool {
7312 *self == WDPL_A::CYCLES_32K
7313 }
7314 ///- 64K (65536) cycles, ~0.5s
7315 #[inline(always)]
7316 pub fn is_cycles_64k(&self) -> bool {
7317 *self == WDPL_A::CYCLES_64K
7318 }
7319 ///- 128K (131072) cycles, ~1s
7320 #[inline(always)]
7321 pub fn is_cycles_128k(&self) -> bool {
7322 *self == WDPL_A::CYCLES_128K
7323 }
7324 ///- 256K (262144) cycles, ~2s
7325 #[inline(always)]
7326 pub fn is_cycles_256k(&self) -> bool {
7327 *self == WDPL_A::CYCLES_256K
7328 }
7329 }
7330 ///Field `WDPL` writer - Watchdog Timer Prescaler - Low Bits
7331 pub type WDPL_W<'a, REG> = crate::FieldWriter<'a, REG, 3, WDPL_A, crate::Safe>;
7332 impl<'a, REG> WDPL_W<'a, REG>
7333 where
7334 REG: crate::Writable + crate::RegisterSpec,
7335 REG::Ux: From<u8>,
7336 {
7337 ///- 2048 cycles, ~16ms/512K (524288) cycles, ~4s if WDPH is set
7338 #[inline(always)]
7339 pub fn cycles_2k_512k(self) -> &'a mut crate::W<REG> {
7340 self.variant(WDPL_A::CYCLES_2K_512K)
7341 }
7342 ///- 4096 cycles, ~32ms/1024K (1048576) cycles, ~8s if WDPH is set
7343 #[inline(always)]
7344 pub fn cycles_4k_1024k(self) -> &'a mut crate::W<REG> {
7345 self.variant(WDPL_A::CYCLES_4K_1024K)
7346 }
7347 ///- 8192 cycles, ~64ms
7348 #[inline(always)]
7349 pub fn cycles_8k(self) -> &'a mut crate::W<REG> {
7350 self.variant(WDPL_A::CYCLES_8K)
7351 }
7352 ///- 16K (16384) cycles, ~0.125s
7353 #[inline(always)]
7354 pub fn cycles_16k(self) -> &'a mut crate::W<REG> {
7355 self.variant(WDPL_A::CYCLES_16K)
7356 }
7357 ///- 32K (32768) cycles, ~0.25s
7358 #[inline(always)]
7359 pub fn cycles_32k(self) -> &'a mut crate::W<REG> {
7360 self.variant(WDPL_A::CYCLES_32K)
7361 }
7362 ///- 64K (65536) cycles, ~0.5s
7363 #[inline(always)]
7364 pub fn cycles_64k(self) -> &'a mut crate::W<REG> {
7365 self.variant(WDPL_A::CYCLES_64K)
7366 }
7367 ///- 128K (131072) cycles, ~1s
7368 #[inline(always)]
7369 pub fn cycles_128k(self) -> &'a mut crate::W<REG> {
7370 self.variant(WDPL_A::CYCLES_128K)
7371 }
7372 ///- 256K (262144) cycles, ~2s
7373 #[inline(always)]
7374 pub fn cycles_256k(self) -> &'a mut crate::W<REG> {
7375 self.variant(WDPL_A::CYCLES_256K)
7376 }
7377 }
7378 ///Field `WDE` reader - Watch Dog Enable
7379 pub type WDE_R = crate::BitReader;
7380 ///Field `WDE` writer - Watch Dog Enable
7381 pub type WDE_W<'a, REG> = crate::BitWriter<'a, REG>;
7382 ///Field `WDCE` reader - Watchdog Change Enable
7383 pub type WDCE_R = crate::BitReader;
7384 ///Field `WDCE` writer - Watchdog Change Enable
7385 pub type WDCE_W<'a, REG> = crate::BitWriter<'a, REG>;
7386 ///Field `WDPH` reader - Watchdog Timer Prescaler - High Bit
7387 pub type WDPH_R = crate::BitReader;
7388 ///Field `WDPH` writer - Watchdog Timer Prescaler - High Bit
7389 pub type WDPH_W<'a, REG> = crate::BitWriter<'a, REG>;
7390 ///Field `WDIE` reader - Watchdog Timeout Interrupt Enable
7391 pub type WDIE_R = crate::BitReader;
7392 ///Field `WDIE` writer - Watchdog Timeout Interrupt Enable
7393 pub type WDIE_W<'a, REG> = crate::BitWriter<'a, REG>;
7394 ///Field `WDIF` reader - Watchdog Timeout Interrupt Flag
7395 pub type WDIF_R = crate::BitReader;
7396 ///Field `WDIF` writer - Watchdog Timeout Interrupt Flag
7397 pub type WDIF_W<'a, REG> = crate::BitWriter<'a, REG>;
7398 impl R {
7399 ///Bits 0:2 - Watchdog Timer Prescaler - Low Bits
7400 #[inline(always)]
7401 pub fn wdpl(&self) -> WDPL_R {
7402 WDPL_R::new(self.bits & 7)
7403 }
7404 ///Bit 3 - Watch Dog Enable
7405 #[inline(always)]
7406 pub fn wde(&self) -> WDE_R {
7407 WDE_R::new(((self.bits >> 3) & 1) != 0)
7408 }
7409 ///Bit 4 - Watchdog Change Enable
7410 #[inline(always)]
7411 pub fn wdce(&self) -> WDCE_R {
7412 WDCE_R::new(((self.bits >> 4) & 1) != 0)
7413 }
7414 ///Bit 5 - Watchdog Timer Prescaler - High Bit
7415 #[inline(always)]
7416 pub fn wdph(&self) -> WDPH_R {
7417 WDPH_R::new(((self.bits >> 5) & 1) != 0)
7418 }
7419 ///Bit 6 - Watchdog Timeout Interrupt Enable
7420 #[inline(always)]
7421 pub fn wdie(&self) -> WDIE_R {
7422 WDIE_R::new(((self.bits >> 6) & 1) != 0)
7423 }
7424 ///Bit 7 - Watchdog Timeout Interrupt Flag
7425 #[inline(always)]
7426 pub fn wdif(&self) -> WDIF_R {
7427 WDIF_R::new(((self.bits >> 7) & 1) != 0)
7428 }
7429 }
7430 impl W {
7431 ///Bits 0:2 - Watchdog Timer Prescaler - Low Bits
7432 #[inline(always)]
7433 pub fn wdpl(&mut self) -> WDPL_W<'_, WDTCR_SPEC> {
7434 WDPL_W::new(self, 0)
7435 }
7436 ///Bit 3 - Watch Dog Enable
7437 #[inline(always)]
7438 pub fn wde(&mut self) -> WDE_W<'_, WDTCR_SPEC> {
7439 WDE_W::new(self, 3)
7440 }
7441 ///Bit 4 - Watchdog Change Enable
7442 #[inline(always)]
7443 pub fn wdce(&mut self) -> WDCE_W<'_, WDTCR_SPEC> {
7444 WDCE_W::new(self, 4)
7445 }
7446 ///Bit 5 - Watchdog Timer Prescaler - High Bit
7447 #[inline(always)]
7448 pub fn wdph(&mut self) -> WDPH_W<'_, WDTCR_SPEC> {
7449 WDPH_W::new(self, 5)
7450 }
7451 ///Bit 6 - Watchdog Timeout Interrupt Enable
7452 #[inline(always)]
7453 pub fn wdie(&mut self) -> WDIE_W<'_, WDTCR_SPEC> {
7454 WDIE_W::new(self, 6)
7455 }
7456 ///Bit 7 - Watchdog Timeout Interrupt Flag
7457 #[inline(always)]
7458 pub fn wdif(&mut self) -> WDIF_W<'_, WDTCR_SPEC> {
7459 WDIF_W::new(self, 7)
7460 }
7461 }
7462 /**Watchdog Timer Control Register
7463
7464You can [`read`](crate::Reg::read) this register and get [`wdtcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdtcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
7465 pub struct WDTCR_SPEC;
7466 impl crate::RegisterSpec for WDTCR_SPEC {
7467 type Ux = u8;
7468 }
7469 ///`read()` method returns [`wdtcr::R`](R) reader structure
7470 impl crate::Readable for WDTCR_SPEC {}
7471 ///`write(|w| ..)` method takes [`wdtcr::W`](W) writer structure
7472 impl crate::Writable for WDTCR_SPEC {
7473 type Safety = crate::Unsafe;
7474 }
7475 ///`reset()` method sets WDTCR to value 0
7476 impl crate::Resettable for WDTCR_SPEC {}
7477 }
7478}
7479use super::DEVICE_PERIPHERALS;
7480/// All the peripherals.
7481#[allow(non_snake_case)]
7482pub struct Peripherals {
7483 ///AC
7484 pub AC: AC,
7485 ///ADC
7486 pub ADC: ADC,
7487 ///BOOT_LOAD
7488 pub BOOT_LOAD: BOOT_LOAD,
7489 ///CPU
7490 pub CPU: CPU,
7491 ///EEPROM
7492 pub EEPROM: EEPROM,
7493 ///EXINT
7494 pub EXINT: EXINT,
7495 ///FUSE
7496 pub FUSE: FUSE,
7497 ///LOCKBIT
7498 pub LOCKBIT: LOCKBIT,
7499 ///PORTB
7500 pub PORTB: PORTB,
7501 ///TC0
7502 pub TC0: TC0,
7503 ///TC1
7504 pub TC1: TC1,
7505 ///USI
7506 pub USI: USI,
7507 ///WDT
7508 pub WDT: WDT,
7509}
7510impl Peripherals {
7511 /// Returns all the peripherals *once*.
7512 #[cfg(feature = "critical-section")]
7513 #[inline]
7514 pub fn take() -> Option<Self> {
7515 critical_section::with(|_| {
7516 if unsafe { DEVICE_PERIPHERALS } {
7517 return None;
7518 }
7519 Some(unsafe { Peripherals::steal() })
7520 })
7521 }
7522 /// Unchecked version of `Peripherals::take`.
7523 ///
7524 /// # Safety
7525 ///
7526 /// Each of the returned peripherals must be used at most once.
7527 #[inline]
7528 pub unsafe fn steal() -> Self {
7529 DEVICE_PERIPHERALS = true;
7530 Peripherals {
7531 AC: AC::steal(),
7532 ADC: ADC::steal(),
7533 BOOT_LOAD: BOOT_LOAD::steal(),
7534 CPU: CPU::steal(),
7535 EEPROM: EEPROM::steal(),
7536 EXINT: EXINT::steal(),
7537 FUSE: FUSE::steal(),
7538 LOCKBIT: LOCKBIT::steal(),
7539 PORTB: PORTB::steal(),
7540 TC0: TC0::steal(),
7541 TC1: TC1::steal(),
7542 USI: USI::steal(),
7543 WDT: WDT::steal(),
7544 }
7545 }
7546}