pub fn lookup_vector(chip: &str, intr: &str) -> Option<usize> {
match chip {
"at90usb1286" => match intr {
"RESET" => Some(0),
"INT0" => Some(1),
"INT1" => Some(2),
"INT2" => Some(3),
"INT3" => Some(4),
"INT4" => Some(5),
"INT5" => Some(6),
"INT6" => Some(7),
"INT7" => Some(8),
"PCINT0" => Some(9),
"USB_GEN" => Some(10),
"USB_COM" => Some(11),
"WDT" => Some(12),
"TIMER2_COMPA" => Some(13),
"TIMER2_COMPB" => Some(14),
"TIMER2_OVF" => Some(15),
"TIMER1_CAPT" => Some(16),
"TIMER1_COMPA" => Some(17),
"TIMER1_COMPB" => Some(18),
"TIMER1_COMPC" => Some(19),
"TIMER1_OVF" => Some(20),
"TIMER0_COMPA" => Some(21),
"TIMER0_COMPB" => Some(22),
"TIMER0_OVF" => Some(23),
"SPI_STC" => Some(24),
"USART1_RX" => Some(25),
"USART1_UDRE" => Some(26),
"USART1_TX" => Some(27),
"ANALOG_COMP" => Some(28),
"ADC" => Some(29),
"EE_READY" => Some(30),
"TIMER3_CAPT" => Some(31),
"TIMER3_COMPA" => Some(32),
"TIMER3_COMPB" => Some(33),
"TIMER3_COMPC" => Some(34),
"TIMER3_OVF" => Some(35),
"TWI" => Some(36),
"SPM_READY" => Some(37),
_ => None,
},
"atmega1280" => match intr {
"RESET" => Some(0),
"INT0" => Some(1),
"INT1" => Some(2),
"INT2" => Some(3),
"INT3" => Some(4),
"INT4" => Some(5),
"INT5" => Some(6),
"INT6" => Some(7),
"INT7" => Some(8),
"PCINT0" => Some(9),
"PCINT1" => Some(10),
"PCINT2" => Some(11),
"WDT" => Some(12),
"TIMER2_COMPA" => Some(13),
"TIMER2_COMPB" => Some(14),
"TIMER2_OVF" => Some(15),
"TIMER1_CAPT" => Some(16),
"TIMER1_COMPA" => Some(17),
"TIMER1_COMPB" => Some(18),
"TIMER1_COMPC" => Some(19),
"TIMER1_OVF" => Some(20),
"TIMER0_COMPA" => Some(21),
"TIMER0_COMPB" => Some(22),
"TIMER0_OVF" => Some(23),
"SPI_STC" => Some(24),
"USART0_RX" => Some(25),
"USART0_UDRE" => Some(26),
"USART0_TX" => Some(27),
"ANALOG_COMP" => Some(28),
"ADC" => Some(29),
"EE_READY" => Some(30),
"TIMER3_CAPT" => Some(31),
"TIMER3_COMPA" => Some(32),
"TIMER3_COMPB" => Some(33),
"TIMER3_COMPC" => Some(34),
"TIMER3_OVF" => Some(35),
"USART1_RX" => Some(36),
"USART1_UDRE" => Some(37),
"USART1_TX" => Some(38),
"TWI" => Some(39),
"SPM_READY" => Some(40),
"TIMER4_CAPT" => Some(41),
"TIMER4_COMPA" => Some(42),
"TIMER4_COMPB" => Some(43),
"TIMER4_COMPC" => Some(44),
"TIMER4_OVF" => Some(45),
"TIMER5_CAPT" => Some(46),
"TIMER5_COMPA" => Some(47),
"TIMER5_COMPB" => Some(48),
"TIMER5_COMPC" => Some(49),
"TIMER5_OVF" => Some(50),
"USART2_RX" => Some(51),
"USART2_UDRE" => Some(52),
"USART2_TX" => Some(53),
"USART3_RX" => Some(54),
"USART3_UDRE" => Some(55),
"USART3_TX" => Some(56),
_ => None,
},
"atmega1284p" => match intr {
"RESET" => Some(0),
"INT0" => Some(1),
"INT1" => Some(2),
"INT2" => Some(3),
"PCINT0" => Some(4),
"PCINT1" => Some(5),
"PCINT2" => Some(6),
"PCINT3" => Some(7),
"WDT" => Some(8),
"TIMER2_COMPA" => Some(9),
"TIMER2_COMPB" => Some(10),
"TIMER2_OVF" => Some(11),
"TIMER1_CAPT" => Some(12),
"TIMER1_COMPA" => Some(13),
"TIMER1_COMPB" => Some(14),
"TIMER1_OVF" => Some(15),
"TIMER0_COMPA" => Some(16),
"TIMER0_COMPB" => Some(17),
"TIMER0_OVF" => Some(18),
"SPI_STC" => Some(19),
"USART0_RX" => Some(20),
"USART0_UDRE" => Some(21),
"USART0_TX" => Some(22),
"ANALOG_COMP" => Some(23),
"ADC" => Some(24),
"EE_READY" => Some(25),
"TWI" => Some(26),
"SPM_READY" => Some(27),
"USART1_RX" => Some(28),
"USART1_UDRE" => Some(29),
"USART1_TX" => Some(30),
"TIMER3_CAPT" => Some(31),
"TIMER3_COMPA" => Some(32),
"TIMER3_COMPB" => Some(33),
"TIMER3_OVF" => Some(34),
_ => None,
},
"atmega128a" => match intr {
"RESET" => Some(0),
"INT0" => Some(1),
"INT1" => Some(2),
"INT2" => Some(3),
"INT3" => Some(4),
"INT4" => Some(5),
"INT5" => Some(6),
"INT6" => Some(7),
"INT7" => Some(8),
"TIMER2_COMP" => Some(9),
"TIMER2_OVF" => Some(10),
"TIMER1_CAPT" => Some(11),
"TIMER1_COMPA" => Some(12),
"TIMER1_COMPB" => Some(13),
"TIMER1_OVF" => Some(14),
"TIMER0_COMP" => Some(15),
"TIMER0_OVF" => Some(16),
"SPI_STC" => Some(17),
"USART0_RX" => Some(18),
"USART0_UDRE" => Some(19),
"USART0_TX" => Some(20),
"ADC" => Some(21),
"EE_READY" => Some(22),
"ANALOG_COMP" => Some(23),
"TIMER1_COMPC" => Some(24),
"TIMER3_CAPT" => Some(25),
"TIMER3_COMPA" => Some(26),
"TIMER3_COMPB" => Some(27),
"TIMER3_COMPC" => Some(28),
"TIMER3_OVF" => Some(29),
"USART1_RX" => Some(30),
"USART1_UDRE" => Some(31),
"USART1_TX" => Some(32),
"TWI" => Some(33),
"SPM_READY" => Some(34),
_ => None,
},
"atmega128rfa1" => match intr {
"RESET" => Some(0),
"INT0" => Some(1),
"INT1" => Some(2),
"INT2" => Some(3),
"INT3" => Some(4),
"INT4" => Some(5),
"INT5" => Some(6),
"INT6" => Some(7),
"INT7" => Some(8),
"PCINT0" => Some(9),
"PCINT1" => Some(10),
"PCINT2" => Some(11),
"WDT" => Some(12),
"TIMER2_COMPA" => Some(13),
"TIMER2_COMPB" => Some(14),
"TIMER2_OVF" => Some(15),
"TIMER1_CAPT" => Some(16),
"TIMER1_COMPA" => Some(17),
"TIMER1_COMPB" => Some(18),
"TIMER1_COMPC" => Some(19),
"TIMER1_OVF" => Some(20),
"TIMER0_COMPA" => Some(21),
"TIMER0_COMPB" => Some(22),
"TIMER0_OVF" => Some(23),
"SPI_STC" => Some(24),
"USART0_RX" => Some(25),
"USART0_UDRE" => Some(26),
"USART0_TX" => Some(27),
"ANALOG_COMP" => Some(28),
"ADC" => Some(29),
"EE_READY" => Some(30),
"TIMER3_CAPT" => Some(31),
"TIMER3_COMPA" => Some(32),
"TIMER3_COMPB" => Some(33),
"TIMER3_COMPC" => Some(34),
"TIMER3_OVF" => Some(35),
"USART1_RX" => Some(36),
"USART1_UDRE" => Some(37),
"USART1_TX" => Some(38),
"TWI" => Some(39),
"SPM_READY" => Some(40),
"TIMER4_CAPT" => Some(41),
"TIMER4_COMPA" => Some(42),
"TIMER4_COMPB" => Some(43),
"TIMER4_COMPC" => Some(44),
"TIMER4_OVF" => Some(45),
"TIMER5_CAPT" => Some(46),
"TIMER5_COMPA" => Some(47),
"TIMER5_COMPB" => Some(48),
"TIMER5_COMPC" => Some(49),
"TIMER5_OVF" => Some(50),
"USART2_RX" => Some(51),
"USART2_UDRE" => Some(52),
"USART2_TX" => Some(53),
"USART3_RX" => Some(54),
"USART3_UDRE" => Some(55),
"USART3_TX" => Some(56),
"TRX24_PLL_LOCK" => Some(57),
"TRX24_PLL_UNLOCK" => Some(58),
"TRX24_RX_START" => Some(59),
"TRX24_RX_END" => Some(60),
"TRX24_CCA_ED_DONE" => Some(61),
"TRX24_XAH_AMI" => Some(62),
"TRX24_TX_END" => Some(63),
"TRX24_AWAKE" => Some(64),
"SCNT_CMP1" => Some(65),
"SCNT_CMP2" => Some(66),
"SCNT_CMP3" => Some(67),
"SCNT_OVFL" => Some(68),
"SCNT_BACKOFF" => Some(69),
"AES_READY" => Some(70),
"BAT_LOW" => Some(71),
_ => None,
},
"atmega16" => match intr {
"RESET" => Some(0),
"INT0" => Some(1),
"INT1" => Some(2),
"TIMER2_COMP" => Some(3),
"TIMER2_OVF" => Some(4),
"TIMER1_CAPT" => Some(5),
"TIMER1_COMPA" => Some(6),
"TIMER1_COMPB" => Some(7),
"TIMER1_OVF" => Some(8),
"TIMER0_OVF" => Some(9),
"SPI_STC" => Some(10),
"USART_RXC" => Some(11),
"USART_UDRE" => Some(12),
"USART_TXC" => Some(13),
"ADC" => Some(14),
"EE_RDY" => Some(15),
"ANA_COMP" => Some(16),
"TWI" => Some(17),
"INT2" => Some(18),
"TIMER0_COMP" => Some(19),
"SPM_RDY" => Some(20),
_ => None,
},
"atmega164pa" => match intr {
"RESET" => Some(0),
"INT0" => Some(1),
"INT1" => Some(2),
"INT2" => Some(3),
"PCINT0" => Some(4),
"PCINT1" => Some(5),
"PCINT2" => Some(6),
"PCINT3" => Some(7),
"WDT" => Some(8),
"TIMER2_COMPA" => Some(9),
"TIMER2_COMPB" => Some(10),
"TIMER2_OVF" => Some(11),
"TIMER1_CAPT" => Some(12),
"TIMER1_COMPA" => Some(13),
"TIMER1_COMPB" => Some(14),
"TIMER1_OVF" => Some(15),
"TIMER0_COMPA" => Some(16),
"TIMER0_COMPB" => Some(17),
"TIMER0_OVF" => Some(18),
"SPI_STC" => Some(19),
"USART0_RX" => Some(20),
"USART0_UDRE" => Some(21),
"USART0_TX" => Some(22),
"ANALOG_COMP" => Some(23),
"ADC" => Some(24),
"EE_READY" => Some(25),
"TWI" => Some(26),
"SPM_READY" => Some(27),
"USART1_RX" => Some(28),
"USART1_UDRE" => Some(29),
"USART1_TX" => Some(30),
_ => None,
},
"atmega168" => match intr {
"RESET" => Some(0),
"INT0" => Some(1),
"INT1" => Some(2),
"PCINT0" => Some(3),
"PCINT1" => Some(4),
"PCINT2" => Some(5),
"WDT" => Some(6),
"TIMER2_COMPA" => Some(7),
"TIMER2_COMPB" => Some(8),
"TIMER2_OVF" => Some(9),
"TIMER1_CAPT" => Some(10),
"TIMER1_COMPA" => Some(11),
"TIMER1_COMPB" => Some(12),
"TIMER1_OVF" => Some(13),
"TIMER0_COMPA" => Some(14),
"TIMER0_COMPB" => Some(15),
"TIMER0_OVF" => Some(16),
"SPI_STC" => Some(17),
"USART_RX" => Some(18),
"USART_UDRE" => Some(19),
"USART_TX" => Some(20),
"ADC" => Some(21),
"EE_READY" => Some(22),
"ANALOG_COMP" => Some(23),
"TWI" => Some(24),
"SPM_READY" => Some(25),
_ => None,
},
"atmega16u2" => match intr {
"RESET" => Some(0),
"INT0" => Some(1),
"INT1" => Some(2),
"INT2" => Some(3),
"INT3" => Some(4),
"INT4" => Some(5),
"INT5" => Some(6),
"INT6" => Some(7),
"INT7" => Some(8),
"PCINT0" => Some(9),
"PCINT1" => Some(10),
"USB_GEN" => Some(11),
"USB_COM" => Some(12),
"WDT" => Some(13),
"TIMER1_CAPT" => Some(14),
"TIMER1_COMPA" => Some(15),
"TIMER1_COMPB" => Some(16),
"TIMER1_COMPC" => Some(17),
"TIMER1_OVF" => Some(18),
"TIMER0_COMPA" => Some(19),
"TIMER0_COMPB" => Some(20),
"TIMER0_OVF" => Some(21),
"SPI_STC" => Some(22),
"USART1_RX" => Some(23),
"USART1_UDRE" => Some(24),
"USART1_TX" => Some(25),
"ANALOG_COMP" => Some(26),
"EE_READY" => Some(27),
"SPM_READY" => Some(28),
_ => None,
},
"atmega2560" => match intr {
"RESET" => Some(0),
"INT0" => Some(1),
"INT1" => Some(2),
"INT2" => Some(3),
"INT3" => Some(4),
"INT4" => Some(5),
"INT5" => Some(6),
"INT6" => Some(7),
"INT7" => Some(8),
"PCINT0" => Some(9),
"PCINT1" => Some(10),
"PCINT2" => Some(11),
"WDT" => Some(12),
"TIMER2_COMPA" => Some(13),
"TIMER2_COMPB" => Some(14),
"TIMER2_OVF" => Some(15),
"TIMER1_CAPT" => Some(16),
"TIMER1_COMPA" => Some(17),
"TIMER1_COMPB" => Some(18),
"TIMER1_COMPC" => Some(19),
"TIMER1_OVF" => Some(20),
"TIMER0_COMPA" => Some(21),
"TIMER0_COMPB" => Some(22),
"TIMER0_OVF" => Some(23),
"SPI_STC" => Some(24),
"USART0_RX" => Some(25),
"USART0_UDRE" => Some(26),
"USART0_TX" => Some(27),
"ANALOG_COMP" => Some(28),
"ADC" => Some(29),
"EE_READY" => Some(30),
"TIMER3_CAPT" => Some(31),
"TIMER3_COMPA" => Some(32),
"TIMER3_COMPB" => Some(33),
"TIMER3_COMPC" => Some(34),
"TIMER3_OVF" => Some(35),
"USART1_RX" => Some(36),
"USART1_UDRE" => Some(37),
"USART1_TX" => Some(38),
"TWI" => Some(39),
"SPM_READY" => Some(40),
"TIMER4_CAPT" => Some(41),
"TIMER4_COMPA" => Some(42),
"TIMER4_COMPB" => Some(43),
"TIMER4_COMPC" => Some(44),
"TIMER4_OVF" => Some(45),
"TIMER5_CAPT" => Some(46),
"TIMER5_COMPA" => Some(47),
"TIMER5_COMPB" => Some(48),
"TIMER5_COMPC" => Some(49),
"TIMER5_OVF" => Some(50),
"USART2_RX" => Some(51),
"USART2_UDRE" => Some(52),
"USART2_TX" => Some(53),
"USART3_RX" => Some(54),
"USART3_UDRE" => Some(55),
"USART3_TX" => Some(56),
_ => None,
},
"atmega3208" => match intr {
"CRCSCAN_NMI" => Some(1),
"BOD_VLM" => Some(2),
"RTC_CNT" => Some(3),
"RTC_PIT" => Some(4),
"CCL_CCL" => Some(5),
"PORTA_PORT" => Some(6),
"TCA0_LUNF_OVF" => Some(7),
"TCA0_HUNF" => Some(8),
"TCA0_CMP0_LCMP0" => Some(9),
"TCA0_CMP1_LCMP1" => Some(10),
"TCA0_CMP2_LCMP2" => Some(11),
"TCB0_INT" => Some(12),
"TCB1_INT" => Some(13),
"TWI0_TWIS" => Some(14),
"TWI0_TWIM" => Some(15),
"SPI0_INT" => Some(16),
"USART0_RXC" => Some(17),
"USART0_DRE" => Some(18),
"USART0_TXC" => Some(19),
"PORTD_PORT" => Some(20),
"AC0_AC" => Some(21),
"ADC0_RESRDY" => Some(22),
"ADC0_WCOMP" => Some(23),
"PORTC_PORT" => Some(24),
"TCB2_INT" => Some(25),
"USART1_RXC" => Some(26),
"USART1_DRE" => Some(27),
"USART1_TXC" => Some(28),
"PORTF_PORT" => Some(29),
"NVMCTRL_EE" => Some(30),
"USART2_RXC" => Some(31),
"USART2_DRE" => Some(32),
"USART2_TXC" => Some(33),
"PORTB_PORT" => Some(34),
"PORTE_PORT" => Some(35),
_ => None,
},
"atmega3209" => match intr {
"CRCSCAN_NMI" => Some(1),
"BOD_VLM" => Some(2),
"RTC_CNT" => Some(3),
"RTC_PIT" => Some(4),
"CCL_CCL" => Some(5),
"PORTA_PORT" => Some(6),
"TCA0_LUNF_OVF" => Some(7),
"TCA0_HUNF" => Some(8),
"TCA0_CMP0_LCMP0" => Some(9),
"TCA0_CMP1_LCMP1" => Some(10),
"TCA0_CMP2_LCMP2" => Some(11),
"TCB0_INT" => Some(12),
"TCB1_INT" => Some(13),
"TWI0_TWIS" => Some(14),
"TWI0_TWIM" => Some(15),
"SPI0_INT" => Some(16),
"USART0_RXC" => Some(17),
"USART0_DRE" => Some(18),
"USART0_TXC" => Some(19),
"PORTD_PORT" => Some(20),
"AC0_AC" => Some(21),
"ADC0_RESRDY" => Some(22),
"ADC0_WCOMP" => Some(23),
"PORTC_PORT" => Some(24),
"TCB2_INT" => Some(25),
"USART1_RXC" => Some(26),
"USART1_DRE" => Some(27),
"USART1_TXC" => Some(28),
"PORTF_PORT" => Some(29),
"NVMCTRL_EE" => Some(30),
"USART2_RXC" => Some(31),
"USART2_DRE" => Some(32),
"USART2_TXC" => Some(33),
"PORTB_PORT" => Some(34),
"PORTE_PORT" => Some(35),
"TCB3_INT" => Some(36),
"USART3_RXC" => Some(37),
"USART3_DRE" => Some(38),
"USART3_TXC" => Some(39),
_ => None,
},
"atmega324pa" => match intr {
"RESET" => Some(0),
"INT0" => Some(1),
"INT1" => Some(2),
"INT2" => Some(3),
"PCINT0" => Some(4),
"PCINT1" => Some(5),
"PCINT2" => Some(6),
"PCINT3" => Some(7),
"WDT" => Some(8),
"TIMER2_COMPA" => Some(9),
"TIMER2_COMPB" => Some(10),
"TIMER2_OVF" => Some(11),
"TIMER1_CAPT" => Some(12),
"TIMER1_COMPA" => Some(13),
"TIMER1_COMPB" => Some(14),
"TIMER1_OVF" => Some(15),
"TIMER0_COMPA" => Some(16),
"TIMER0_COMPB" => Some(17),
"TIMER0_OVF" => Some(18),
"SPI_STC" => Some(19),
"USART0_RX" => Some(20),
"USART0_UDRE" => Some(21),
"USART0_TX" => Some(22),
"ANALOG_COMP" => Some(23),
"ADC" => Some(24),
"EE_READY" => Some(25),
"TWI" => Some(26),
"SPM_READY" => Some(27),
"USART1_RX" => Some(28),
"USART1_UDRE" => Some(29),
"USART1_TX" => Some(30),
_ => None,
},
"atmega328p" => match intr {
"RESET" => Some(0),
"INT0" => Some(1),
"INT1" => Some(2),
"PCINT0" => Some(3),
"PCINT1" => Some(4),
"PCINT2" => Some(5),
"WDT" => Some(6),
"TIMER2_COMPA" => Some(7),
"TIMER2_COMPB" => Some(8),
"TIMER2_OVF" => Some(9),
"TIMER1_CAPT" => Some(10),
"TIMER1_COMPA" => Some(11),
"TIMER1_COMPB" => Some(12),
"TIMER1_OVF" => Some(13),
"TIMER0_COMPA" => Some(14),
"TIMER0_COMPB" => Some(15),
"TIMER0_OVF" => Some(16),
"SPI_STC" => Some(17),
"USART_RX" => Some(18),
"USART_UDRE" => Some(19),
"USART_TX" => Some(20),
"ADC" => Some(21),
"EE_READY" => Some(22),
"ANALOG_COMP" => Some(23),
"TWI" => Some(24),
"SPM_READY" => Some(25),
_ => None,
},
"atmega328pb" => match intr {
"RESET" => Some(0),
"INT0" => Some(1),
"INT1" => Some(2),
"PCINT0" => Some(3),
"PCINT1" => Some(4),
"PCINT2" => Some(5),
"WDT" => Some(6),
"TIMER2_COMPA" => Some(7),
"TIMER2_COMPB" => Some(8),
"TIMER2_OVF" => Some(9),
"TIMER1_CAPT" => Some(10),
"TIMER1_COMPA" => Some(11),
"TIMER1_COMPB" => Some(12),
"TIMER1_OVF" => Some(13),
"TIMER0_COMPA" => Some(14),
"TIMER0_COMPB" => Some(15),
"TIMER0_OVF" => Some(16),
"SPI0_STC" => Some(17),
"USART0_RX" => Some(18),
"USART0_UDRE" => Some(19),
"USART0_TX" => Some(20),
"ADC" => Some(21),
"EE_READY" => Some(22),
"ANALOG_COMP" => Some(23),
"TWI0" => Some(24),
"SPM_READY" => Some(25),
"USART0_START" => Some(26),
"PCINT3" => Some(27),
"USART1_RX" => Some(28),
"USART1_UDRE" => Some(29),
"USART1_TX" => Some(30),
"USART1_START" => Some(31),
"TIMER3_CAPT" => Some(32),
"TIMER3_COMPA" => Some(33),
"TIMER3_COMPB" => Some(34),
"TIMER3_OVF" => Some(35),
"CFD" => Some(36),
"PTC_EOC" => Some(37),
"PTC_WCOMP" => Some(38),
"SPI1_STC" => Some(39),
"TWI1" => Some(40),
"TIMER4_CAPT" => Some(41),
"TIMER4_COMPA" => Some(42),
"TIMER4_COMPB" => Some(43),
"TIMER4_OVF" => Some(44),
_ => None,
},
"atmega32a" => match intr {
"RESET" => Some(0),
"INT0" => Some(1),
"INT1" => Some(2),
"INT2" => Some(3),
"TIMER2_COMP" => Some(4),
"TIMER2_OVF" => Some(5),
"TIMER1_CAPT" => Some(6),
"TIMER1_COMPA" => Some(7),
"TIMER1_COMPB" => Some(8),
"TIMER1_OVF" => Some(9),
"TIMER0_COMP" => Some(10),
"TIMER0_OVF" => Some(11),
"SPI_STC" => Some(12),
"USART_RXC" => Some(13),
"USART_UDRE" => Some(14),
"USART_TXC" => Some(15),
"ADC" => Some(16),
"EE_RDY" => Some(17),
"ANA_COMP" => Some(18),
"TWI" => Some(19),
"SPM_RDY" => Some(20),
_ => None,
},
"atmega32u2" => match intr {
"RESET" => Some(0),
"INT0" => Some(1),
"INT1" => Some(2),
"INT2" => Some(3),
"INT3" => Some(4),
"INT4" => Some(5),
"INT5" => Some(6),
"INT6" => Some(7),
"INT7" => Some(8),
"PCINT0" => Some(9),
"PCINT1" => Some(10),
"USB_GEN" => Some(11),
"USB_COM" => Some(12),
"WDT" => Some(13),
"TIMER1_CAPT" => Some(14),
"TIMER1_COMPA" => Some(15),
"TIMER1_COMPB" => Some(16),
"TIMER1_COMPC" => Some(17),
"TIMER1_OVF" => Some(18),
"TIMER0_COMPA" => Some(19),
"TIMER0_COMPB" => Some(20),
"TIMER0_OVF" => Some(21),
"SPI_STC" => Some(22),
"USART1_RX" => Some(23),
"USART1_UDRE" => Some(24),
"USART1_TX" => Some(25),
"ANALOG_COMP" => Some(26),
"EE_READY" => Some(27),
"SPM_READY" => Some(28),
_ => None,
},
"atmega32u4" => match intr {
"RESET" => Some(0),
"INT0" => Some(1),
"INT1" => Some(2),
"INT2" => Some(3),
"INT3" => Some(4),
"RESERVED1" => Some(5),
"RESERVED2" => Some(6),
"INT6" => Some(7),
"RESERVED3" => Some(8),
"PCINT0" => Some(9),
"USB_GEN" => Some(10),
"USB_COM" => Some(11),
"WDT" => Some(12),
"RESERVED4" => Some(13),
"RESERVED5" => Some(14),
"RESERVED6" => Some(15),
"TIMER1_CAPT" => Some(16),
"TIMER1_COMPA" => Some(17),
"TIMER1_COMPB" => Some(18),
"TIMER1_COMPC" => Some(19),
"TIMER1_OVF" => Some(20),
"TIMER0_COMPA" => Some(21),
"TIMER0_COMPB" => Some(22),
"TIMER0_OVF" => Some(23),
"SPI_STC" => Some(24),
"USART1_RX" => Some(25),
"USART1_UDRE" => Some(26),
"USART1_TX" => Some(27),
"ANALOG_COMP" => Some(28),
"ADC" => Some(29),
"EE_READY" => Some(30),
"TIMER3_CAPT" => Some(31),
"TIMER3_COMPA" => Some(32),
"TIMER3_COMPB" => Some(33),
"TIMER3_COMPC" => Some(34),
"TIMER3_OVF" => Some(35),
"TWI" => Some(36),
"SPM_READY" => Some(37),
"TIMER4_COMPA" => Some(38),
"TIMER4_COMPB" => Some(39),
"TIMER4_COMPD" => Some(40),
"TIMER4_OVF" => Some(41),
"TIMER4_FPF" => Some(42),
_ => None,
},
"atmega4808" => match intr {
"CRCSCAN_NMI" => Some(1),
"BOD_VLM" => Some(2),
"RTC_CNT" => Some(3),
"RTC_PIT" => Some(4),
"CCL_CCL" => Some(5),
"PORTA_PORT" => Some(6),
"TCA0_LUNF_OVF" => Some(7),
"TCA0_HUNF" => Some(8),
"TCA0_CMP0_LCMP0" => Some(9),
"TCA0_CMP1_LCMP1" => Some(10),
"TCA0_CMP2_LCMP2" => Some(11),
"TCB0_INT" => Some(12),
"TCB1_INT" => Some(13),
"TWI0_TWIS" => Some(14),
"TWI0_TWIM" => Some(15),
"SPI0_INT" => Some(16),
"USART0_RXC" => Some(17),
"USART0_DRE" => Some(18),
"USART0_TXC" => Some(19),
"PORTD_PORT" => Some(20),
"AC0_AC" => Some(21),
"ADC0_RESRDY" => Some(22),
"ADC0_WCOMP" => Some(23),
"PORTC_PORT" => Some(24),
"TCB2_INT" => Some(25),
"USART1_RXC" => Some(26),
"USART1_DRE" => Some(27),
"USART1_TXC" => Some(28),
"PORTF_PORT" => Some(29),
"NVMCTRL_EE" => Some(30),
"USART2_RXC" => Some(31),
"USART2_DRE" => Some(32),
"USART2_TXC" => Some(33),
"PORTB_PORT" => Some(34),
"PORTE_PORT" => Some(35),
_ => None,
},
"atmega4809" => match intr {
"CRCSCAN_NMI" => Some(1),
"BOD_VLM" => Some(2),
"RTC_CNT" => Some(3),
"RTC_PIT" => Some(4),
"CCL_CCL" => Some(5),
"PORTA_PORT" => Some(6),
"TCA0_LUNF_OVF" => Some(7),
"TCA0_HUNF" => Some(8),
"TCA0_CMP0_LCMP0" => Some(9),
"TCA0_CMP1_LCMP1" => Some(10),
"TCA0_CMP2_LCMP2" => Some(11),
"TCB0_INT" => Some(12),
"TCB1_INT" => Some(13),
"TWI0_TWIS" => Some(14),
"TWI0_TWIM" => Some(15),
"SPI0_INT" => Some(16),
"USART0_RXC" => Some(17),
"USART0_DRE" => Some(18),
"USART0_TXC" => Some(19),
"PORTD_PORT" => Some(20),
"AC0_AC" => Some(21),
"ADC0_RESRDY" => Some(22),
"ADC0_WCOMP" => Some(23),
"PORTC_PORT" => Some(24),
"TCB2_INT" => Some(25),
"USART1_RXC" => Some(26),
"USART1_DRE" => Some(27),
"USART1_TXC" => Some(28),
"PORTF_PORT" => Some(29),
"NVMCTRL_EE" => Some(30),
"USART2_RXC" => Some(31),
"USART2_DRE" => Some(32),
"USART2_TXC" => Some(33),
"PORTB_PORT" => Some(34),
"PORTE_PORT" => Some(35),
"TCB3_INT" => Some(36),
"USART3_RXC" => Some(37),
"USART3_DRE" => Some(38),
"USART3_TXC" => Some(39),
_ => None,
},
"atmega48p" => match intr {
"RESET" => Some(0),
"INT0" => Some(1),
"INT1" => Some(2),
"PCINT0" => Some(3),
"PCINT1" => Some(4),
"PCINT2" => Some(5),
"WDT" => Some(6),
"TIMER2_COMPA" => Some(7),
"TIMER2_COMPB" => Some(8),
"TIMER2_OVF" => Some(9),
"TIMER1_CAPT" => Some(10),
"TIMER1_COMPA" => Some(11),
"TIMER1_COMPB" => Some(12),
"TIMER1_OVF" => Some(13),
"TIMER0_COMPA" => Some(14),
"TIMER0_COMPB" => Some(15),
"TIMER0_OVF" => Some(16),
"SPI_STC" => Some(17),
"USART_RX" => Some(18),
"USART_UDRE" => Some(19),
"USART_TX" => Some(20),
"ADC" => Some(21),
"EE_READY" => Some(22),
"ANALOG_COMP" => Some(23),
"TWI" => Some(24),
"SPM_READY" => Some(25),
_ => None,
},
"atmega64" => match intr {
"RESET" => Some(0),
"INT0" => Some(1),
"INT1" => Some(2),
"INT2" => Some(3),
"INT3" => Some(4),
"INT4" => Some(5),
"INT5" => Some(6),
"INT6" => Some(7),
"INT7" => Some(8),
"TIMER2_COMP" => Some(9),
"TIMER2_OVF" => Some(10),
"TIMER1_CAPT" => Some(11),
"TIMER1_COMPA" => Some(12),
"TIMER1_COMPB" => Some(13),
"TIMER1_OVF" => Some(14),
"TIMER0_COMP" => Some(15),
"TIMER0_OVF" => Some(16),
"SPI_STC" => Some(17),
"USART0_RX" => Some(18),
"USART0_UDRE" => Some(19),
"USART0_TX" => Some(20),
"ADC" => Some(21),
"EE_READY" => Some(22),
"ANALOG_COMP" => Some(23),
"TIMER1_COMPC" => Some(24),
"TIMER3_CAPT" => Some(25),
"TIMER3_COMPA" => Some(26),
"TIMER3_COMPB" => Some(27),
"TIMER3_COMPC" => Some(28),
"TIMER3_OVF" => Some(29),
"USART1_RX" => Some(30),
"USART1_UDRE" => Some(31),
"USART1_TX" => Some(32),
"TWI" => Some(33),
"SPM_READY" => Some(34),
_ => None,
},
"atmega644" => match intr {
"RESET" => Some(0),
"INT0" => Some(1),
"INT1" => Some(2),
"INT2" => Some(3),
"PCINT0" => Some(4),
"PCINT1" => Some(5),
"PCINT2" => Some(6),
"PCINT3" => Some(7),
"WDT" => Some(8),
"TIMER2_COMPA" => Some(9),
"TIMER2_COMPB" => Some(10),
"TIMER2_OVF" => Some(11),
"TIMER1_CAPT" => Some(12),
"TIMER1_COMPA" => Some(13),
"TIMER1_COMPB" => Some(14),
"TIMER1_OVF" => Some(15),
"TIMER0_COMPA" => Some(16),
"TIMER0_COMPB" => Some(17),
"TIMER0_OVF" => Some(18),
"SPI_STC" => Some(19),
"USART0_RX" => Some(20),
"USART0_UDRE" => Some(21),
"USART0_TX" => Some(22),
"ANALOG_COMP" => Some(23),
"ADC" => Some(24),
"EE_READY" => Some(25),
"TWI" => Some(26),
"SPM_READY" => Some(27),
_ => None,
},
"atmega8" => match intr {
"RESET" => Some(0),
"INT0" => Some(1),
"INT1" => Some(2),
"TIMER2_COMP" => Some(3),
"TIMER2_OVF" => Some(4),
"TIMER1_CAPT" => Some(5),
"TIMER1_COMPA" => Some(6),
"TIMER1_COMPB" => Some(7),
"TIMER1_OVF" => Some(8),
"TIMER0_OVF" => Some(9),
"SPI_STC" => Some(10),
"USART_RXC" => Some(11),
"USART_UDRE" => Some(12),
"USART_TXC" => Some(13),
"ADC" => Some(14),
"EE_RDY" => Some(15),
"ANA_COMP" => Some(16),
"TWI" => Some(17),
"SPM_RDY" => Some(18),
_ => None,
},
"atmega88p" => match intr {
"RESET" => Some(0),
"INT0" => Some(1),
"INT1" => Some(2),
"PCINT0" => Some(3),
"PCINT1" => Some(4),
"PCINT2" => Some(5),
"WDT" => Some(6),
"TIMER2_COMPA" => Some(7),
"TIMER2_COMPB" => Some(8),
"TIMER2_OVF" => Some(9),
"TIMER1_CAPT" => Some(10),
"TIMER1_COMPA" => Some(11),
"TIMER1_COMPB" => Some(12),
"TIMER1_OVF" => Some(13),
"TIMER0_COMPA" => Some(14),
"TIMER0_COMPB" => Some(15),
"TIMER0_OVF" => Some(16),
"SPI_STC" => Some(17),
"USART_RX" => Some(18),
"USART_UDRE" => Some(19),
"USART_TX" => Some(20),
"ADC" => Some(21),
"EE_READY" => Some(22),
"ANALOG_COMP" => Some(23),
"TWI" => Some(24),
"SPM_READY" => Some(25),
_ => None,
},
"atmega8u2" => match intr {
"RESET" => Some(0),
"INT0" => Some(1),
"INT1" => Some(2),
"INT2" => Some(3),
"INT3" => Some(4),
"INT4" => Some(5),
"INT5" => Some(6),
"INT6" => Some(7),
"INT7" => Some(8),
"PCINT0" => Some(9),
"PCINT1" => Some(10),
"USB_GEN" => Some(11),
"USB_COM" => Some(12),
"WDT" => Some(13),
"TIMER1_CAPT" => Some(14),
"TIMER1_COMPA" => Some(15),
"TIMER1_COMPB" => Some(16),
"TIMER1_COMPC" => Some(17),
"TIMER1_OVF" => Some(18),
"TIMER0_COMPA" => Some(19),
"TIMER0_COMPB" => Some(20),
"TIMER0_OVF" => Some(21),
"SPI_STC" => Some(22),
"USART1_RX" => Some(23),
"USART1_UDRE" => Some(24),
"USART1_TX" => Some(25),
"ANALOG_COMP" => Some(26),
"EE_READY" => Some(27),
"SPM_READY" => Some(28),
_ => None,
},
"attiny13a" => match intr {
"RESET" => Some(0),
"INT0" => Some(1),
"PCINT0" => Some(2),
"TIM0_OVF" => Some(3),
"EE_RDY" => Some(4),
"ANA_COMP" => Some(5),
"TIM0_COMPA" => Some(6),
"TIM0_COMPB" => Some(7),
"WDT" => Some(8),
"ADC" => Some(9),
_ => None,
},
"attiny1614" => match intr {
"CRCSCAN_NMI" => Some(1),
"BOD_VLM" => Some(2),
"PORTA_PORT" => Some(3),
"PORTB_PORT" => Some(4),
"RTC_CNT" => Some(6),
"RTC_PIT" => Some(7),
"TCA0_LUNF_OVF" => Some(8),
"TCA0_HUNF" => Some(9),
"TCA0_CMP0_LCMP0" => Some(10),
"TCA0_CMP1_LCMP1" => Some(11),
"TCA0_CMP2_LCMP2" => Some(12),
"TCB0_INT" => Some(13),
"TCB1_INT" => Some(14),
"TCD0_OVF" => Some(15),
"TCD0_TRIG" => Some(16),
"AC0_AC" => Some(17),
"AC1_AC" => Some(18),
"AC2_AC" => Some(19),
"ADC0_RESRDY" => Some(20),
"ADC0_WCOMP" => Some(21),
"ADC1_RESRDY" => Some(22),
"ADC1_WCOMP" => Some(23),
"TWI0_TWIS" => Some(24),
"TWI0_TWIM" => Some(25),
"SPI0_INT" => Some(26),
"USART0_RXC" => Some(27),
"USART0_DRE" => Some(28),
"USART0_TXC" => Some(29),
"NVMCTRL_EE" => Some(30),
_ => None,
},
"attiny167" => match intr {
"RESET" => Some(0),
"INT0" => Some(1),
"INT1" => Some(2),
"PCINT0" => Some(3),
"PCINT1" => Some(4),
"WDT" => Some(5),
"TIMER1_CAPT" => Some(6),
"TIMER1_COMPA" => Some(7),
"TIMER1_COMPB" => Some(8),
"TIMER1_OVF" => Some(9),
"TIMER0_COMPA" => Some(10),
"TIMER0_OVF" => Some(11),
"LIN_TC" => Some(12),
"LIN_ERR" => Some(13),
"SPI_STC" => Some(14),
"ADC" => Some(15),
"EE_RDY" => Some(16),
"ANA_COMP" => Some(17),
"USI_START" => Some(18),
"USI_OVF" => Some(19),
_ => None,
},
"attiny202" => match intr {
"CRCSCAN_NMI" => Some(1),
"BOD_VLM" => Some(2),
"PORTA_PORT" => Some(3),
"RTC_CNT" => Some(6),
"RTC_PIT" => Some(7),
"TCA0_LUNF_OVF" => Some(8),
"TCA0_HUNF" => Some(9),
"TCA0_CMP0_LCMP0" => Some(10),
"TCA0_CMP1_LCMP1" => Some(11),
"TCA0_CMP2_LCMP2" => Some(12),
"TCB0_INT" => Some(13),
"AC0_AC" => Some(16),
"ADC0_RESRDY" => Some(17),
"ADC0_WCOMP" => Some(18),
"TWI0_TWIS" => Some(19),
"TWI0_TWIM" => Some(20),
"SPI0_INT" => Some(21),
"USART0_RXC" => Some(22),
"USART0_DRE" => Some(23),
"USART0_TXC" => Some(24),
"NVMCTRL_EE" => Some(25),
_ => None,
},
"attiny212" => match intr {
"CRCSCAN_NMI" => Some(1),
"BOD_VLM" => Some(2),
"PORTA_PORT" => Some(3),
"RTC_CNT" => Some(6),
"RTC_PIT" => Some(7),
"TCA0_LUNF_OVF" => Some(8),
"TCA0_HUNF" => Some(9),
"TCA0_LCMP0_CMP0" => Some(10),
"TCA0_CMP1_LCMP1" => Some(11),
"TCA0_CMP2_LCMP2" => Some(12),
"TCB0_INT" => Some(13),
"TCD0_OVF" => Some(14),
"TCD0_TRIG" => Some(15),
"AC0_AC" => Some(16),
"ADC0_RESRDY" => Some(17),
"ADC0_WCOMP" => Some(18),
"TWI0_TWIS" => Some(19),
"TWI0_TWIM" => Some(20),
"SPI0_INT" => Some(21),
"USART0_RXC" => Some(22),
"USART0_DRE" => Some(23),
"USART0_TXC" => Some(24),
"NVMCTRL_EE" => Some(25),
_ => None,
},
"attiny214" => match intr {
"CRCSCAN_NMI" => Some(1),
"BOD_VLM" => Some(2),
"PORTA_PORT" => Some(3),
"PORTB_PORT" => Some(4),
"RTC_CNT" => Some(6),
"RTC_PIT" => Some(7),
"TCA0_LUNF_OVF" => Some(8),
"TCA0_HUNF" => Some(9),
"TCA0_LCMP0_CMP0" => Some(10),
"TCA0_CMP1_LCMP1" => Some(11),
"TCA0_CMP2_LCMP2" => Some(12),
"TCB0_INT" => Some(13),
"TCD0_OVF" => Some(14),
"TCD0_TRIG" => Some(15),
"AC0_AC" => Some(16),
"ADC0_RESRDY" => Some(17),
"ADC0_WCOMP" => Some(18),
"TWI0_TWIS" => Some(19),
"TWI0_TWIM" => Some(20),
"SPI0_INT" => Some(21),
"USART0_RXC" => Some(22),
"USART0_DRE" => Some(23),
"USART0_TXC" => Some(24),
"NVMCTRL_EE" => Some(25),
_ => None,
},
"attiny2313" => match intr {
"RESET" => Some(0),
"INT0" => Some(1),
"INT1" => Some(2),
"TIMER1_CAPT" => Some(3),
"TIMER1_COMPA" => Some(4),
"TIMER1_OVF" => Some(5),
"TIMER0_OVF" => Some(6),
"USART_RX" => Some(7),
"USART_UDRE" => Some(8),
"USART_TX" => Some(9),
"ANA_COMP" => Some(10),
"PCINT" => Some(11),
"TIMER1_COMPB" => Some(12),
"TIMER0_COMPA" => Some(13),
"TIMER0_COMPB" => Some(14),
"USI_START" => Some(15),
"USI_OVERFLOW" => Some(16),
"EEPROM_READY" => Some(17),
"WDT_OVERFLOW" => Some(18),
_ => None,
},
"attiny2313a" => match intr {
"RESET" => Some(0),
"INT0" => Some(1),
"INT1" => Some(2),
"TIMER1_CAPT" => Some(3),
"TIMER1_COMPA" => Some(4),
"TIMER1_OVF" => Some(5),
"TIMER0_OVF" => Some(6),
"USART_RX" => Some(7),
"USART_UDRE" => Some(8),
"USART_TX" => Some(9),
"ANA_COMP" => Some(10),
"PCINT_B" => Some(11),
"TIMER1_COMPB" => Some(12),
"TIMER0_COMPA" => Some(13),
"TIMER0_COMPB" => Some(14),
"USI_START" => Some(15),
"USI_OVERFLOW" => Some(16),
"EEPROM_READY" => Some(17),
"WDT_OVERFLOW" => Some(18),
"PCINT_A" => Some(19),
"PCINT_D" => Some(20),
_ => None,
},
"attiny26" => match intr {
"RESET" => Some(0),
"INT0" => Some(1),
"IO_PINS" => Some(2),
"TIMER1_CMPA" => Some(3),
"TIMER1_CMPB" => Some(4),
"TIMER1_OVF1" => Some(5),
"TIMER0_OVF0" => Some(6),
"USI_STRT" => Some(7),
"USI_OVF" => Some(8),
"EE_RDY" => Some(9),
"ANA_COMP" => Some(10),
"ADC" => Some(11),
_ => None,
},
"attiny402" => match intr {
"CRCSCAN_NMI" => Some(1),
"BOD_VLM" => Some(2),
"PORTA_PORT" => Some(3),
"RTC_CNT" => Some(6),
"RTC_PIT" => Some(7),
"TCA0_LUNF_OVF" => Some(8),
"TCA0_HUNF" => Some(9),
"TCA0_CMP0_LCMP0" => Some(10),
"TCA0_CMP1_LCMP1" => Some(11),
"TCA0_CMP2_LCMP2" => Some(12),
"TCB0_INT" => Some(13),
"AC0_AC" => Some(16),
"ADC0_RESRDY" => Some(17),
"ADC0_WCOMP" => Some(18),
"TWI0_TWIS" => Some(19),
"TWI0_TWIM" => Some(20),
"SPI0_INT" => Some(21),
"USART0_RXC" => Some(22),
"USART0_DRE" => Some(23),
"USART0_TXC" => Some(24),
"NVMCTRL_EE" => Some(25),
_ => None,
},
"attiny404" => match intr {
"CRCSCAN_NMI" => Some(1),
"BOD_VLM" => Some(2),
"PORTA_PORT" => Some(3),
"PORTB_PORT" => Some(4),
"RTC_CNT" => Some(6),
"RTC_PIT" => Some(7),
"TCA0_LUNF_OVF" => Some(8),
"TCA0_HUNF" => Some(9),
"TCA0_CMP0_LCMP0" => Some(10),
"TCA0_CMP1_LCMP1" => Some(11),
"TCA0_CMP2_LCMP2" => Some(12),
"TCB0_INT" => Some(13),
"AC0_AC" => Some(16),
"ADC0_RESRDY" => Some(17),
"ADC0_WCOMP" => Some(18),
"TWI0_TWIS" => Some(19),
"TWI0_TWIM" => Some(20),
"SPI0_INT" => Some(21),
"USART0_RXC" => Some(22),
"USART0_DRE" => Some(23),
"USART0_TXC" => Some(24),
"NVMCTRL_EE" => Some(25),
_ => None,
},
"attiny412" => match intr {
"CRCSCAN_NMI" => Some(1),
"BOD_VLM" => Some(2),
"PORTA_PORT" => Some(3),
"RTC_CNT" => Some(6),
"RTC_PIT" => Some(7),
"TCA0_LUNF_OVF" => Some(8),
"TCA0_HUNF" => Some(9),
"TCA0_LCMP0_CMP0" => Some(10),
"TCA0_CMP1_LCMP1" => Some(11),
"TCA0_CMP2_LCMP2" => Some(12),
"TCB0_INT" => Some(13),
"TCD0_OVF" => Some(14),
"TCD0_TRIG" => Some(15),
"AC0_AC" => Some(16),
"ADC0_RESRDY" => Some(17),
"ADC0_WCOMP" => Some(18),
"TWI0_TWIS" => Some(19),
"TWI0_TWIM" => Some(20),
"SPI0_INT" => Some(21),
"USART0_RXC" => Some(22),
"USART0_DRE" => Some(23),
"USART0_TXC" => Some(24),
"NVMCTRL_EE" => Some(25),
_ => None,
},
"attiny414" => match intr {
"CRCSCAN_NMI" => Some(1),
"BOD_VLM" => Some(2),
"PORTA_PORT" => Some(3),
"PORTB_PORT" => Some(4),
"RTC_CNT" => Some(6),
"RTC_PIT" => Some(7),
"TCA0_LUNF_OVF" => Some(8),
"TCA0_HUNF" => Some(9),
"TCA0_LCMP0_CMP0" => Some(10),
"TCA0_CMP1_LCMP1" => Some(11),
"TCA0_CMP2_LCMP2" => Some(12),
"TCB0_INT" => Some(13),
"TCD0_OVF" => Some(14),
"TCD0_TRIG" => Some(15),
"AC0_AC" => Some(16),
"ADC0_RESRDY" => Some(17),
"ADC0_WCOMP" => Some(18),
"TWI0_TWIS" => Some(19),
"TWI0_TWIM" => Some(20),
"SPI0_INT" => Some(21),
"USART0_RXC" => Some(22),
"USART0_DRE" => Some(23),
"USART0_TXC" => Some(24),
"NVMCTRL_EE" => Some(25),
_ => None,
},
"attiny416" => match intr {
"CRCSCAN_NMI" => Some(1),
"BOD_VLM" => Some(2),
"PORTA_PORT" => Some(3),
"PORTB_PORT" => Some(4),
"PORTC_PORT" => Some(5),
"RTC_CNT" => Some(6),
"RTC_PIT" => Some(7),
"TCA0_LUNF_OVF" => Some(8),
"TCA0_HUNF" => Some(9),
"TCA0_LCMP0_CMP0" => Some(10),
"TCA0_CMP1_LCMP1" => Some(11),
"TCA0_CMP2_LCMP2" => Some(12),
"TCB0_INT" => Some(13),
"TCD0_OVF" => Some(14),
"TCD0_TRIG" => Some(15),
"AC0_AC" => Some(16),
"ADC0_RESRDY" => Some(17),
"ADC0_WCOMP" => Some(18),
"TWI0_TWIS" => Some(19),
"TWI0_TWIM" => Some(20),
"SPI0_INT" => Some(21),
"USART0_RXC" => Some(22),
"USART0_DRE" => Some(23),
"USART0_TXC" => Some(24),
"NVMCTRL_EE" => Some(25),
_ => None,
},
"attiny44a" => match intr {
"RESET" => Some(0),
"EXT_INT0" => Some(1),
"PCINT0" => Some(2),
"PCINT1" => Some(3),
"WDT" => Some(4),
"TIM1_CAPT" => Some(5),
"TIM1_COMPA" => Some(6),
"TIM1_COMPB" => Some(7),
"TIM1_OVF" => Some(8),
"TIM0_COMPA" => Some(9),
"TIM0_COMPB" => Some(10),
"TIM0_OVF" => Some(11),
"ANA_COMP" => Some(12),
"ADC" => Some(13),
"EE_RDY" => Some(14),
"USI_STR" => Some(15),
"USI_OVF" => Some(16),
_ => None,
},
"attiny816" => match intr {
"CRCSCAN_NMI" => Some(1),
"BOD_VLM" => Some(2),
"PORTA_PORT" => Some(3),
"PORTB_PORT" => Some(4),
"PORTC_PORT" => Some(5),
"RTC_CNT" => Some(6),
"RTC_PIT" => Some(7),
"TCA0_LUNF_OVF" => Some(8),
"TCA0_HUNF" => Some(9),
"TCA0_CMP0_LCMP0" => Some(10),
"TCA0_CMP1_LCMP1" => Some(11),
"TCA0_CMP2_LCMP2" => Some(12),
"TCB0_INT" => Some(13),
"TCD0_OVF" => Some(14),
"TCD0_TRIG" => Some(15),
"AC0_AC" => Some(16),
"ADC0_RESRDY" => Some(17),
"ADC0_WCOMP" => Some(18),
"TWI0_TWIS" => Some(19),
"TWI0_TWIM" => Some(20),
"SPI0_INT" => Some(21),
"USART0_RXC" => Some(22),
"USART0_DRE" => Some(23),
"USART0_TXC" => Some(24),
"NVMCTRL_EE" => Some(25),
_ => None,
},
"attiny828" => match intr {
"RESET" => Some(0),
"INT0" => Some(1),
"INT1" => Some(2),
"PCINT0" => Some(3),
"PCINT1" => Some(4),
"PCINT2" => Some(5),
"PCINT3" => Some(6),
"WDT" => Some(7),
"TIMER1_CAPT" => Some(8),
"TIMER1_COMPA" => Some(9),
"TIMER1_COMPB" => Some(10),
"TIMER1_OVF" => Some(11),
"TIMER0_COMPA" => Some(12),
"TIMER0_COMPB" => Some(13),
"TIMER0_OVF" => Some(14),
"SPI_STC" => Some(15),
"USART_START" => Some(16),
"USART_RX" => Some(17),
"USART_UDRE" => Some(18),
"USART_TX" => Some(19),
"ADC" => Some(20),
"EE_READY" => Some(21),
"ANALOG_COMP" => Some(22),
"TWI_SLAVE" => Some(23),
"SPM_READY" => Some(24),
"QTRIP" => Some(25),
_ => None,
},
"attiny84" => match intr {
"RESET" => Some(0),
"EXT_INT0" => Some(1),
"PCINT0" => Some(2),
"PCINT1" => Some(3),
"WDT" => Some(4),
"TIM1_CAPT" => Some(5),
"TIM1_COMPA" => Some(6),
"TIM1_COMPB" => Some(7),
"TIM1_OVF" => Some(8),
"TIM0_COMPA" => Some(9),
"TIM0_COMPB" => Some(10),
"TIM0_OVF" => Some(11),
"ANA_COMP" => Some(12),
"ADC" => Some(13),
"EE_RDY" => Some(14),
"USI_STR" => Some(15),
"USI_OVF" => Some(16),
_ => None,
},
"attiny841" => match intr {
"RESET" => Some(0),
"INT0" => Some(1),
"PCINT0" => Some(2),
"PCINT1" => Some(3),
"WDT" => Some(4),
"TIMER1_CAPT" => Some(5),
"TIMER1_COMPA" => Some(6),
"TIMER1_COMPB" => Some(7),
"TIMER1_OVF" => Some(8),
"TIMER0_COMPA" => Some(9),
"TIMER0_COMPB" => Some(10),
"TIMER0_OVF" => Some(11),
"ANA_COMP0" => Some(12),
"ADC" => Some(13),
"EE_RDY" => Some(14),
"ANA_COMP1" => Some(15),
"TIMER2_CAPT" => Some(16),
"TIMER2_COMPA" => Some(17),
"TIMER2_COMPB" => Some(18),
"TIMER2_OVF" => Some(19),
"SPI" => Some(20),
"USART0_START" => Some(21),
"USART0_RX" => Some(22),
"USART0_UDRE" => Some(23),
"USART0_TX" => Some(24),
"USART1_START" => Some(25),
"USART1_RX" => Some(26),
"USART1_UDRE" => Some(27),
"USART1_TX" => Some(28),
"TWI_SLAVE" => Some(29),
_ => None,
},
"attiny84a" => match intr {
"RESET" => Some(0),
"EXT_INT0" => Some(1),
"PCINT0" => Some(2),
"PCINT1" => Some(3),
"WDT" => Some(4),
"TIM1_CAPT" => Some(5),
"TIM1_COMPA" => Some(6),
"TIM1_COMPB" => Some(7),
"TIM1_OVF" => Some(8),
"TIM0_COMPA" => Some(9),
"TIM0_COMPB" => Some(10),
"TIM0_OVF" => Some(11),
"ANA_COMP" => Some(12),
"ADC" => Some(13),
"EE_RDY" => Some(14),
"USI_STR" => Some(15),
"USI_OVF" => Some(16),
_ => None,
},
"attiny85" => match intr {
"RESET" => Some(0),
"INT0" => Some(1),
"PCINT0" => Some(2),
"TIMER1_COMPA" => Some(3),
"TIMER1_OVF" => Some(4),
"TIMER0_OVF" => Some(5),
"EE_RDY" => Some(6),
"ANA_COMP" => Some(7),
"ADC" => Some(8),
"TIMER1_COMPB" => Some(9),
"TIMER0_COMPA" => Some(10),
"TIMER0_COMPB" => Some(11),
"WDT" => Some(12),
"USI_START" => Some(13),
"USI_OVF" => Some(14),
_ => None,
},
"attiny861" => match intr {
"RESET" => Some(0),
"INT0" => Some(1),
"PCINT" => Some(2),
"TIMER1_COMPA" => Some(3),
"TIMER1_COMPB" => Some(4),
"TIMER1_OVF" => Some(5),
"TIMER0_OVF" => Some(6),
"USI_START" => Some(7),
"USI_OVF" => Some(8),
"EE_RDY" => Some(9),
"ANA_COMP" => Some(10),
"ADC" => Some(11),
"WDT" => Some(12),
"INT1" => Some(13),
"TIMER0_COMPA" => Some(14),
"TIMER0_COMPB" => Some(15),
"TIMER0_CAPT" => Some(16),
"TIMER1_COMPD" => Some(17),
"FAULT_PROTECTION" => Some(18),
_ => None,
},
"attiny88" => match intr {
"RESET" => Some(0),
"INT0" => Some(1),
"INT1" => Some(2),
"PCINT0" => Some(3),
"PCINT1" => Some(4),
"PCINT2" => Some(5),
"PCINT3" => Some(6),
"WDT" => Some(7),
"TIMER1_CAPT" => Some(8),
"TIMER1_COMPA" => Some(9),
"TIMER1_COMPB" => Some(10),
"TIMER1_OVF" => Some(11),
"TIMER0_COMPA" => Some(12),
"TIMER0_COMPB" => Some(13),
"TIMER0_OVF" => Some(14),
"SPI_STC" => Some(15),
"ADC" => Some(16),
"EE_RDY" => Some(17),
"ANALOG_COMP" => Some(18),
"TWI" => Some(19),
_ => None,
},
"avr64du28" => match intr {
"CRCSCAN_NMI" => Some(1),
"BOD_VLM" => Some(2),
"CLKCTRL_CFD" => Some(3),
"RTC_CNT" => Some(4),
"RTC_PIT" => Some(5),
"CCL_CCL" => Some(6),
"USB0_BUSEVENT" => Some(7),
"USB0_TRNCOMPL" => Some(8),
"PORTA_PORT" => Some(9),
"TCA0_LUNF_OVF" => Some(10),
"TCA0_HUNF" => Some(11),
"TCA0_CMP0_LCMP0" => Some(12),
"TCA0_CMP1_LCMP1" => Some(13),
"TCA0_CMP2_LCMP2" => Some(14),
"TCB0_INT" => Some(15),
"TWI0_TWIS" => Some(16),
"TWI0_TWIM" => Some(17),
"SPI0_INT" => Some(18),
"USART0_RXC" => Some(19),
"USART0_DRE" => Some(20),
"USART0_TXC" => Some(21),
"PORTD_PORT" => Some(22),
"PORTC_PORT" => Some(23),
"PORTF_PORT" => Some(24),
"NVMCTRL_NVMREADY" => Some(25),
"USART1_RXC" => Some(26),
"USART1_DRE" => Some(27),
"USART1_TXC" => Some(28),
"TCB1_INT" => Some(29),
"AC0_AC" => Some(30),
"ADC0_ERROR" => Some(31),
"ADC0_RESRDY" => Some(32),
"ADC0_SAMPRDY" => Some(33),
_ => None,
},
"avr64du32" => match intr {
"CRCSCAN_NMI" => Some(1),
"BOD_VLM" => Some(2),
"CLKCTRL_CFD" => Some(3),
"RTC_CNT" => Some(4),
"RTC_PIT" => Some(5),
"CCL_CCL" => Some(6),
"USB0_BUSEVENT" => Some(7),
"USB0_TRNCOMPL" => Some(8),
"PORTA_PORT" => Some(9),
"TCA0_LUNF_OVF" => Some(10),
"TCA0_HUNF" => Some(11),
"TCA0_CMP0_LCMP0" => Some(12),
"TCA0_CMP1_LCMP1" => Some(13),
"TCA0_CMP2_LCMP2" => Some(14),
"TCB0_INT" => Some(15),
"TWI0_TWIS" => Some(16),
"TWI0_TWIM" => Some(17),
"SPI0_INT" => Some(18),
"USART0_RXC" => Some(19),
"USART0_DRE" => Some(20),
"USART0_TXC" => Some(21),
"PORTD_PORT" => Some(22),
"PORTC_PORT" => Some(23),
"PORTF_PORT" => Some(24),
"NVMCTRL_NVMREADY" => Some(25),
"USART1_RXC" => Some(26),
"USART1_DRE" => Some(27),
"USART1_TXC" => Some(28),
"TCB1_INT" => Some(29),
"AC0_AC" => Some(30),
"ADC0_ERROR" => Some(31),
"ADC0_RESRDY" => Some(32),
"ADC0_SAMPRDY" => Some(33),
_ => None,
},
_ => None,
}
}