1pub fn lookup_vector(chip: &str, intr: &str) -> Option<usize> {
3 match chip {
4 "at90usb1286" => match intr {
5 "RESET" => Some(0),
6 "INT0" => Some(1),
7 "INT1" => Some(2),
8 "INT2" => Some(3),
9 "INT3" => Some(4),
10 "INT4" => Some(5),
11 "INT5" => Some(6),
12 "INT6" => Some(7),
13 "INT7" => Some(8),
14 "PCINT0" => Some(9),
15 "USB_GEN" => Some(10),
16 "USB_COM" => Some(11),
17 "WDT" => Some(12),
18 "TIMER2_COMPA" => Some(13),
19 "TIMER2_COMPB" => Some(14),
20 "TIMER2_OVF" => Some(15),
21 "TIMER1_CAPT" => Some(16),
22 "TIMER1_COMPA" => Some(17),
23 "TIMER1_COMPB" => Some(18),
24 "TIMER1_COMPC" => Some(19),
25 "TIMER1_OVF" => Some(20),
26 "TIMER0_COMPA" => Some(21),
27 "TIMER0_COMPB" => Some(22),
28 "TIMER0_OVF" => Some(23),
29 "SPI_STC" => Some(24),
30 "USART1_RX" => Some(25),
31 "USART1_UDRE" => Some(26),
32 "USART1_TX" => Some(27),
33 "ANALOG_COMP" => Some(28),
34 "ADC" => Some(29),
35 "EE_READY" => Some(30),
36 "TIMER3_CAPT" => Some(31),
37 "TIMER3_COMPA" => Some(32),
38 "TIMER3_COMPB" => Some(33),
39 "TIMER3_COMPC" => Some(34),
40 "TIMER3_OVF" => Some(35),
41 "TWI" => Some(36),
42 "SPM_READY" => Some(37),
43 _ => None,
44 },
45 "atmega1280" => match intr {
46 "RESET" => Some(0),
47 "INT0" => Some(1),
48 "INT1" => Some(2),
49 "INT2" => Some(3),
50 "INT3" => Some(4),
51 "INT4" => Some(5),
52 "INT5" => Some(6),
53 "INT6" => Some(7),
54 "INT7" => Some(8),
55 "PCINT0" => Some(9),
56 "PCINT1" => Some(10),
57 "PCINT2" => Some(11),
58 "WDT" => Some(12),
59 "TIMER2_COMPA" => Some(13),
60 "TIMER2_COMPB" => Some(14),
61 "TIMER2_OVF" => Some(15),
62 "TIMER1_CAPT" => Some(16),
63 "TIMER1_COMPA" => Some(17),
64 "TIMER1_COMPB" => Some(18),
65 "TIMER1_COMPC" => Some(19),
66 "TIMER1_OVF" => Some(20),
67 "TIMER0_COMPA" => Some(21),
68 "TIMER0_COMPB" => Some(22),
69 "TIMER0_OVF" => Some(23),
70 "SPI_STC" => Some(24),
71 "USART0_RX" => Some(25),
72 "USART0_UDRE" => Some(26),
73 "USART0_TX" => Some(27),
74 "ANALOG_COMP" => Some(28),
75 "ADC" => Some(29),
76 "EE_READY" => Some(30),
77 "TIMER3_CAPT" => Some(31),
78 "TIMER3_COMPA" => Some(32),
79 "TIMER3_COMPB" => Some(33),
80 "TIMER3_COMPC" => Some(34),
81 "TIMER3_OVF" => Some(35),
82 "USART1_RX" => Some(36),
83 "USART1_UDRE" => Some(37),
84 "USART1_TX" => Some(38),
85 "TWI" => Some(39),
86 "SPM_READY" => Some(40),
87 "TIMER4_CAPT" => Some(41),
88 "TIMER4_COMPA" => Some(42),
89 "TIMER4_COMPB" => Some(43),
90 "TIMER4_COMPC" => Some(44),
91 "TIMER4_OVF" => Some(45),
92 "TIMER5_CAPT" => Some(46),
93 "TIMER5_COMPA" => Some(47),
94 "TIMER5_COMPB" => Some(48),
95 "TIMER5_COMPC" => Some(49),
96 "TIMER5_OVF" => Some(50),
97 "USART2_RX" => Some(51),
98 "USART2_UDRE" => Some(52),
99 "USART2_TX" => Some(53),
100 "USART3_RX" => Some(54),
101 "USART3_UDRE" => Some(55),
102 "USART3_TX" => Some(56),
103 _ => None,
104 },
105 "atmega1284p" => match intr {
106 "RESET" => Some(0),
107 "INT0" => Some(1),
108 "INT1" => Some(2),
109 "INT2" => Some(3),
110 "PCINT0" => Some(4),
111 "PCINT1" => Some(5),
112 "PCINT2" => Some(6),
113 "PCINT3" => Some(7),
114 "WDT" => Some(8),
115 "TIMER2_COMPA" => Some(9),
116 "TIMER2_COMPB" => Some(10),
117 "TIMER2_OVF" => Some(11),
118 "TIMER1_CAPT" => Some(12),
119 "TIMER1_COMPA" => Some(13),
120 "TIMER1_COMPB" => Some(14),
121 "TIMER1_OVF" => Some(15),
122 "TIMER0_COMPA" => Some(16),
123 "TIMER0_COMPB" => Some(17),
124 "TIMER0_OVF" => Some(18),
125 "SPI_STC" => Some(19),
126 "USART0_RX" => Some(20),
127 "USART0_UDRE" => Some(21),
128 "USART0_TX" => Some(22),
129 "ANALOG_COMP" => Some(23),
130 "ADC" => Some(24),
131 "EE_READY" => Some(25),
132 "TWI" => Some(26),
133 "SPM_READY" => Some(27),
134 "USART1_RX" => Some(28),
135 "USART1_UDRE" => Some(29),
136 "USART1_TX" => Some(30),
137 "TIMER3_CAPT" => Some(31),
138 "TIMER3_COMPA" => Some(32),
139 "TIMER3_COMPB" => Some(33),
140 "TIMER3_OVF" => Some(34),
141 _ => None,
142 },
143 "atmega128a" => match intr {
144 "RESET" => Some(0),
145 "INT0" => Some(1),
146 "INT1" => Some(2),
147 "INT2" => Some(3),
148 "INT3" => Some(4),
149 "INT4" => Some(5),
150 "INT5" => Some(6),
151 "INT6" => Some(7),
152 "INT7" => Some(8),
153 "TIMER2_COMP" => Some(9),
154 "TIMER2_OVF" => Some(10),
155 "TIMER1_CAPT" => Some(11),
156 "TIMER1_COMPA" => Some(12),
157 "TIMER1_COMPB" => Some(13),
158 "TIMER1_OVF" => Some(14),
159 "TIMER0_COMP" => Some(15),
160 "TIMER0_OVF" => Some(16),
161 "SPI_STC" => Some(17),
162 "USART0_RX" => Some(18),
163 "USART0_UDRE" => Some(19),
164 "USART0_TX" => Some(20),
165 "ADC" => Some(21),
166 "EE_READY" => Some(22),
167 "ANALOG_COMP" => Some(23),
168 "TIMER1_COMPC" => Some(24),
169 "TIMER3_CAPT" => Some(25),
170 "TIMER3_COMPA" => Some(26),
171 "TIMER3_COMPB" => Some(27),
172 "TIMER3_COMPC" => Some(28),
173 "TIMER3_OVF" => Some(29),
174 "USART1_RX" => Some(30),
175 "USART1_UDRE" => Some(31),
176 "USART1_TX" => Some(32),
177 "TWI" => Some(33),
178 "SPM_READY" => Some(34),
179 _ => None,
180 },
181 "atmega128rfa1" => match intr {
182 "RESET" => Some(0),
183 "INT0" => Some(1),
184 "INT1" => Some(2),
185 "INT2" => Some(3),
186 "INT3" => Some(4),
187 "INT4" => Some(5),
188 "INT5" => Some(6),
189 "INT6" => Some(7),
190 "INT7" => Some(8),
191 "PCINT0" => Some(9),
192 "PCINT1" => Some(10),
193 "PCINT2" => Some(11),
194 "WDT" => Some(12),
195 "TIMER2_COMPA" => Some(13),
196 "TIMER2_COMPB" => Some(14),
197 "TIMER2_OVF" => Some(15),
198 "TIMER1_CAPT" => Some(16),
199 "TIMER1_COMPA" => Some(17),
200 "TIMER1_COMPB" => Some(18),
201 "TIMER1_COMPC" => Some(19),
202 "TIMER1_OVF" => Some(20),
203 "TIMER0_COMPA" => Some(21),
204 "TIMER0_COMPB" => Some(22),
205 "TIMER0_OVF" => Some(23),
206 "SPI_STC" => Some(24),
207 "USART0_RX" => Some(25),
208 "USART0_UDRE" => Some(26),
209 "USART0_TX" => Some(27),
210 "ANALOG_COMP" => Some(28),
211 "ADC" => Some(29),
212 "EE_READY" => Some(30),
213 "TIMER3_CAPT" => Some(31),
214 "TIMER3_COMPA" => Some(32),
215 "TIMER3_COMPB" => Some(33),
216 "TIMER3_COMPC" => Some(34),
217 "TIMER3_OVF" => Some(35),
218 "USART1_RX" => Some(36),
219 "USART1_UDRE" => Some(37),
220 "USART1_TX" => Some(38),
221 "TWI" => Some(39),
222 "SPM_READY" => Some(40),
223 "TIMER4_CAPT" => Some(41),
224 "TIMER4_COMPA" => Some(42),
225 "TIMER4_COMPB" => Some(43),
226 "TIMER4_COMPC" => Some(44),
227 "TIMER4_OVF" => Some(45),
228 "TIMER5_CAPT" => Some(46),
229 "TIMER5_COMPA" => Some(47),
230 "TIMER5_COMPB" => Some(48),
231 "TIMER5_COMPC" => Some(49),
232 "TIMER5_OVF" => Some(50),
233 "USART2_RX" => Some(51),
234 "USART2_UDRE" => Some(52),
235 "USART2_TX" => Some(53),
236 "USART3_RX" => Some(54),
237 "USART3_UDRE" => Some(55),
238 "USART3_TX" => Some(56),
239 "TRX24_PLL_LOCK" => Some(57),
240 "TRX24_PLL_UNLOCK" => Some(58),
241 "TRX24_RX_START" => Some(59),
242 "TRX24_RX_END" => Some(60),
243 "TRX24_CCA_ED_DONE" => Some(61),
244 "TRX24_XAH_AMI" => Some(62),
245 "TRX24_TX_END" => Some(63),
246 "TRX24_AWAKE" => Some(64),
247 "SCNT_CMP1" => Some(65),
248 "SCNT_CMP2" => Some(66),
249 "SCNT_CMP3" => Some(67),
250 "SCNT_OVFL" => Some(68),
251 "SCNT_BACKOFF" => Some(69),
252 "AES_READY" => Some(70),
253 "BAT_LOW" => Some(71),
254 _ => None,
255 },
256 "atmega16" => match intr {
257 "RESET" => Some(0),
258 "INT0" => Some(1),
259 "INT1" => Some(2),
260 "TIMER2_COMP" => Some(3),
261 "TIMER2_OVF" => Some(4),
262 "TIMER1_CAPT" => Some(5),
263 "TIMER1_COMPA" => Some(6),
264 "TIMER1_COMPB" => Some(7),
265 "TIMER1_OVF" => Some(8),
266 "TIMER0_OVF" => Some(9),
267 "SPI_STC" => Some(10),
268 "USART_RXC" => Some(11),
269 "USART_UDRE" => Some(12),
270 "USART_TXC" => Some(13),
271 "ADC" => Some(14),
272 "EE_RDY" => Some(15),
273 "ANA_COMP" => Some(16),
274 "TWI" => Some(17),
275 "INT2" => Some(18),
276 "TIMER0_COMP" => Some(19),
277 "SPM_RDY" => Some(20),
278 _ => None,
279 },
280 "atmega164pa" => match intr {
281 "RESET" => Some(0),
282 "INT0" => Some(1),
283 "INT1" => Some(2),
284 "INT2" => Some(3),
285 "PCINT0" => Some(4),
286 "PCINT1" => Some(5),
287 "PCINT2" => Some(6),
288 "PCINT3" => Some(7),
289 "WDT" => Some(8),
290 "TIMER2_COMPA" => Some(9),
291 "TIMER2_COMPB" => Some(10),
292 "TIMER2_OVF" => Some(11),
293 "TIMER1_CAPT" => Some(12),
294 "TIMER1_COMPA" => Some(13),
295 "TIMER1_COMPB" => Some(14),
296 "TIMER1_OVF" => Some(15),
297 "TIMER0_COMPA" => Some(16),
298 "TIMER0_COMPB" => Some(17),
299 "TIMER0_OVF" => Some(18),
300 "SPI_STC" => Some(19),
301 "USART0_RX" => Some(20),
302 "USART0_UDRE" => Some(21),
303 "USART0_TX" => Some(22),
304 "ANALOG_COMP" => Some(23),
305 "ADC" => Some(24),
306 "EE_READY" => Some(25),
307 "TWI" => Some(26),
308 "SPM_READY" => Some(27),
309 "USART1_RX" => Some(28),
310 "USART1_UDRE" => Some(29),
311 "USART1_TX" => Some(30),
312 _ => None,
313 },
314 "atmega168" => match intr {
315 "RESET" => Some(0),
316 "INT0" => Some(1),
317 "INT1" => Some(2),
318 "PCINT0" => Some(3),
319 "PCINT1" => Some(4),
320 "PCINT2" => Some(5),
321 "WDT" => Some(6),
322 "TIMER2_COMPA" => Some(7),
323 "TIMER2_COMPB" => Some(8),
324 "TIMER2_OVF" => Some(9),
325 "TIMER1_CAPT" => Some(10),
326 "TIMER1_COMPA" => Some(11),
327 "TIMER1_COMPB" => Some(12),
328 "TIMER1_OVF" => Some(13),
329 "TIMER0_COMPA" => Some(14),
330 "TIMER0_COMPB" => Some(15),
331 "TIMER0_OVF" => Some(16),
332 "SPI_STC" => Some(17),
333 "USART_RX" => Some(18),
334 "USART_UDRE" => Some(19),
335 "USART_TX" => Some(20),
336 "ADC" => Some(21),
337 "EE_READY" => Some(22),
338 "ANALOG_COMP" => Some(23),
339 "TWI" => Some(24),
340 "SPM_READY" => Some(25),
341 _ => None,
342 },
343 "atmega16u2" => match intr {
344 "RESET" => Some(0),
345 "INT0" => Some(1),
346 "INT1" => Some(2),
347 "INT2" => Some(3),
348 "INT3" => Some(4),
349 "INT4" => Some(5),
350 "INT5" => Some(6),
351 "INT6" => Some(7),
352 "INT7" => Some(8),
353 "PCINT0" => Some(9),
354 "PCINT1" => Some(10),
355 "USB_GEN" => Some(11),
356 "USB_COM" => Some(12),
357 "WDT" => Some(13),
358 "TIMER1_CAPT" => Some(14),
359 "TIMER1_COMPA" => Some(15),
360 "TIMER1_COMPB" => Some(16),
361 "TIMER1_COMPC" => Some(17),
362 "TIMER1_OVF" => Some(18),
363 "TIMER0_COMPA" => Some(19),
364 "TIMER0_COMPB" => Some(20),
365 "TIMER0_OVF" => Some(21),
366 "SPI_STC" => Some(22),
367 "USART1_RX" => Some(23),
368 "USART1_UDRE" => Some(24),
369 "USART1_TX" => Some(25),
370 "ANALOG_COMP" => Some(26),
371 "EE_READY" => Some(27),
372 "SPM_READY" => Some(28),
373 _ => None,
374 },
375 "atmega2560" => match intr {
376 "RESET" => Some(0),
377 "INT0" => Some(1),
378 "INT1" => Some(2),
379 "INT2" => Some(3),
380 "INT3" => Some(4),
381 "INT4" => Some(5),
382 "INT5" => Some(6),
383 "INT6" => Some(7),
384 "INT7" => Some(8),
385 "PCINT0" => Some(9),
386 "PCINT1" => Some(10),
387 "PCINT2" => Some(11),
388 "WDT" => Some(12),
389 "TIMER2_COMPA" => Some(13),
390 "TIMER2_COMPB" => Some(14),
391 "TIMER2_OVF" => Some(15),
392 "TIMER1_CAPT" => Some(16),
393 "TIMER1_COMPA" => Some(17),
394 "TIMER1_COMPB" => Some(18),
395 "TIMER1_COMPC" => Some(19),
396 "TIMER1_OVF" => Some(20),
397 "TIMER0_COMPA" => Some(21),
398 "TIMER0_COMPB" => Some(22),
399 "TIMER0_OVF" => Some(23),
400 "SPI_STC" => Some(24),
401 "USART0_RX" => Some(25),
402 "USART0_UDRE" => Some(26),
403 "USART0_TX" => Some(27),
404 "ANALOG_COMP" => Some(28),
405 "ADC" => Some(29),
406 "EE_READY" => Some(30),
407 "TIMER3_CAPT" => Some(31),
408 "TIMER3_COMPA" => Some(32),
409 "TIMER3_COMPB" => Some(33),
410 "TIMER3_COMPC" => Some(34),
411 "TIMER3_OVF" => Some(35),
412 "USART1_RX" => Some(36),
413 "USART1_UDRE" => Some(37),
414 "USART1_TX" => Some(38),
415 "TWI" => Some(39),
416 "SPM_READY" => Some(40),
417 "TIMER4_CAPT" => Some(41),
418 "TIMER4_COMPA" => Some(42),
419 "TIMER4_COMPB" => Some(43),
420 "TIMER4_COMPC" => Some(44),
421 "TIMER4_OVF" => Some(45),
422 "TIMER5_CAPT" => Some(46),
423 "TIMER5_COMPA" => Some(47),
424 "TIMER5_COMPB" => Some(48),
425 "TIMER5_COMPC" => Some(49),
426 "TIMER5_OVF" => Some(50),
427 "USART2_RX" => Some(51),
428 "USART2_UDRE" => Some(52),
429 "USART2_TX" => Some(53),
430 "USART3_RX" => Some(54),
431 "USART3_UDRE" => Some(55),
432 "USART3_TX" => Some(56),
433 _ => None,
434 },
435 "atmega3208" => match intr {
436 "CRCSCAN_NMI" => Some(1),
437 "BOD_VLM" => Some(2),
438 "RTC_CNT" => Some(3),
439 "RTC_PIT" => Some(4),
440 "CCL_CCL" => Some(5),
441 "PORTA_PORT" => Some(6),
442 "TCA0_LUNF_OVF" => Some(7),
443 "TCA0_HUNF" => Some(8),
444 "TCA0_CMP0_LCMP0" => Some(9),
445 "TCA0_CMP1_LCMP1" => Some(10),
446 "TCA0_CMP2_LCMP2" => Some(11),
447 "TCB0_INT" => Some(12),
448 "TCB1_INT" => Some(13),
449 "TWI0_TWIS" => Some(14),
450 "TWI0_TWIM" => Some(15),
451 "SPI0_INT" => Some(16),
452 "USART0_RXC" => Some(17),
453 "USART0_DRE" => Some(18),
454 "USART0_TXC" => Some(19),
455 "PORTD_PORT" => Some(20),
456 "AC0_AC" => Some(21),
457 "ADC0_RESRDY" => Some(22),
458 "ADC0_WCOMP" => Some(23),
459 "PORTC_PORT" => Some(24),
460 "TCB2_INT" => Some(25),
461 "USART1_RXC" => Some(26),
462 "USART1_DRE" => Some(27),
463 "USART1_TXC" => Some(28),
464 "PORTF_PORT" => Some(29),
465 "NVMCTRL_EE" => Some(30),
466 "USART2_RXC" => Some(31),
467 "USART2_DRE" => Some(32),
468 "USART2_TXC" => Some(33),
469 "PORTB_PORT" => Some(34),
470 "PORTE_PORT" => Some(35),
471 _ => None,
472 },
473 "atmega3209" => match intr {
474 "CRCSCAN_NMI" => Some(1),
475 "BOD_VLM" => Some(2),
476 "RTC_CNT" => Some(3),
477 "RTC_PIT" => Some(4),
478 "CCL_CCL" => Some(5),
479 "PORTA_PORT" => Some(6),
480 "TCA0_LUNF_OVF" => Some(7),
481 "TCA0_HUNF" => Some(8),
482 "TCA0_CMP0_LCMP0" => Some(9),
483 "TCA0_CMP1_LCMP1" => Some(10),
484 "TCA0_CMP2_LCMP2" => Some(11),
485 "TCB0_INT" => Some(12),
486 "TCB1_INT" => Some(13),
487 "TWI0_TWIS" => Some(14),
488 "TWI0_TWIM" => Some(15),
489 "SPI0_INT" => Some(16),
490 "USART0_RXC" => Some(17),
491 "USART0_DRE" => Some(18),
492 "USART0_TXC" => Some(19),
493 "PORTD_PORT" => Some(20),
494 "AC0_AC" => Some(21),
495 "ADC0_RESRDY" => Some(22),
496 "ADC0_WCOMP" => Some(23),
497 "PORTC_PORT" => Some(24),
498 "TCB2_INT" => Some(25),
499 "USART1_RXC" => Some(26),
500 "USART1_DRE" => Some(27),
501 "USART1_TXC" => Some(28),
502 "PORTF_PORT" => Some(29),
503 "NVMCTRL_EE" => Some(30),
504 "USART2_RXC" => Some(31),
505 "USART2_DRE" => Some(32),
506 "USART2_TXC" => Some(33),
507 "PORTB_PORT" => Some(34),
508 "PORTE_PORT" => Some(35),
509 "TCB3_INT" => Some(36),
510 "USART3_RXC" => Some(37),
511 "USART3_DRE" => Some(38),
512 "USART3_TXC" => Some(39),
513 _ => None,
514 },
515 "atmega324pa" => match intr {
516 "RESET" => Some(0),
517 "INT0" => Some(1),
518 "INT1" => Some(2),
519 "INT2" => Some(3),
520 "PCINT0" => Some(4),
521 "PCINT1" => Some(5),
522 "PCINT2" => Some(6),
523 "PCINT3" => Some(7),
524 "WDT" => Some(8),
525 "TIMER2_COMPA" => Some(9),
526 "TIMER2_COMPB" => Some(10),
527 "TIMER2_OVF" => Some(11),
528 "TIMER1_CAPT" => Some(12),
529 "TIMER1_COMPA" => Some(13),
530 "TIMER1_COMPB" => Some(14),
531 "TIMER1_OVF" => Some(15),
532 "TIMER0_COMPA" => Some(16),
533 "TIMER0_COMPB" => Some(17),
534 "TIMER0_OVF" => Some(18),
535 "SPI_STC" => Some(19),
536 "USART0_RX" => Some(20),
537 "USART0_UDRE" => Some(21),
538 "USART0_TX" => Some(22),
539 "ANALOG_COMP" => Some(23),
540 "ADC" => Some(24),
541 "EE_READY" => Some(25),
542 "TWI" => Some(26),
543 "SPM_READY" => Some(27),
544 "USART1_RX" => Some(28),
545 "USART1_UDRE" => Some(29),
546 "USART1_TX" => Some(30),
547 _ => None,
548 },
549 "atmega328p" => match intr {
550 "RESET" => Some(0),
551 "INT0" => Some(1),
552 "INT1" => Some(2),
553 "PCINT0" => Some(3),
554 "PCINT1" => Some(4),
555 "PCINT2" => Some(5),
556 "WDT" => Some(6),
557 "TIMER2_COMPA" => Some(7),
558 "TIMER2_COMPB" => Some(8),
559 "TIMER2_OVF" => Some(9),
560 "TIMER1_CAPT" => Some(10),
561 "TIMER1_COMPA" => Some(11),
562 "TIMER1_COMPB" => Some(12),
563 "TIMER1_OVF" => Some(13),
564 "TIMER0_COMPA" => Some(14),
565 "TIMER0_COMPB" => Some(15),
566 "TIMER0_OVF" => Some(16),
567 "SPI_STC" => Some(17),
568 "USART_RX" => Some(18),
569 "USART_UDRE" => Some(19),
570 "USART_TX" => Some(20),
571 "ADC" => Some(21),
572 "EE_READY" => Some(22),
573 "ANALOG_COMP" => Some(23),
574 "TWI" => Some(24),
575 "SPM_READY" => Some(25),
576 _ => None,
577 },
578 "atmega328pb" => match intr {
579 "RESET" => Some(0),
580 "INT0" => Some(1),
581 "INT1" => Some(2),
582 "PCINT0" => Some(3),
583 "PCINT1" => Some(4),
584 "PCINT2" => Some(5),
585 "WDT" => Some(6),
586 "TIMER2_COMPA" => Some(7),
587 "TIMER2_COMPB" => Some(8),
588 "TIMER2_OVF" => Some(9),
589 "TIMER1_CAPT" => Some(10),
590 "TIMER1_COMPA" => Some(11),
591 "TIMER1_COMPB" => Some(12),
592 "TIMER1_OVF" => Some(13),
593 "TIMER0_COMPA" => Some(14),
594 "TIMER0_COMPB" => Some(15),
595 "TIMER0_OVF" => Some(16),
596 "SPI0_STC" => Some(17),
597 "USART0_RX" => Some(18),
598 "USART0_UDRE" => Some(19),
599 "USART0_TX" => Some(20),
600 "ADC" => Some(21),
601 "EE_READY" => Some(22),
602 "ANALOG_COMP" => Some(23),
603 "TWI0" => Some(24),
604 "SPM_READY" => Some(25),
605 "USART0_START" => Some(26),
606 "PCINT3" => Some(27),
607 "USART1_RX" => Some(28),
608 "USART1_UDRE" => Some(29),
609 "USART1_TX" => Some(30),
610 "USART1_START" => Some(31),
611 "TIMER3_CAPT" => Some(32),
612 "TIMER3_COMPA" => Some(33),
613 "TIMER3_COMPB" => Some(34),
614 "TIMER3_OVF" => Some(35),
615 "CFD" => Some(36),
616 "PTC_EOC" => Some(37),
617 "PTC_WCOMP" => Some(38),
618 "SPI1_STC" => Some(39),
619 "TWI1" => Some(40),
620 "TIMER4_CAPT" => Some(41),
621 "TIMER4_COMPA" => Some(42),
622 "TIMER4_COMPB" => Some(43),
623 "TIMER4_OVF" => Some(44),
624 _ => None,
625 },
626 "atmega32a" => match intr {
627 "RESET" => Some(0),
628 "INT0" => Some(1),
629 "INT1" => Some(2),
630 "INT2" => Some(3),
631 "TIMER2_COMP" => Some(4),
632 "TIMER2_OVF" => Some(5),
633 "TIMER1_CAPT" => Some(6),
634 "TIMER1_COMPA" => Some(7),
635 "TIMER1_COMPB" => Some(8),
636 "TIMER1_OVF" => Some(9),
637 "TIMER0_COMP" => Some(10),
638 "TIMER0_OVF" => Some(11),
639 "SPI_STC" => Some(12),
640 "USART_RXC" => Some(13),
641 "USART_UDRE" => Some(14),
642 "USART_TXC" => Some(15),
643 "ADC" => Some(16),
644 "EE_RDY" => Some(17),
645 "ANA_COMP" => Some(18),
646 "TWI" => Some(19),
647 "SPM_RDY" => Some(20),
648 _ => None,
649 },
650 "atmega32u2" => match intr {
651 "RESET" => Some(0),
652 "INT0" => Some(1),
653 "INT1" => Some(2),
654 "INT2" => Some(3),
655 "INT3" => Some(4),
656 "INT4" => Some(5),
657 "INT5" => Some(6),
658 "INT6" => Some(7),
659 "INT7" => Some(8),
660 "PCINT0" => Some(9),
661 "PCINT1" => Some(10),
662 "USB_GEN" => Some(11),
663 "USB_COM" => Some(12),
664 "WDT" => Some(13),
665 "TIMER1_CAPT" => Some(14),
666 "TIMER1_COMPA" => Some(15),
667 "TIMER1_COMPB" => Some(16),
668 "TIMER1_COMPC" => Some(17),
669 "TIMER1_OVF" => Some(18),
670 "TIMER0_COMPA" => Some(19),
671 "TIMER0_COMPB" => Some(20),
672 "TIMER0_OVF" => Some(21),
673 "SPI_STC" => Some(22),
674 "USART1_RX" => Some(23),
675 "USART1_UDRE" => Some(24),
676 "USART1_TX" => Some(25),
677 "ANALOG_COMP" => Some(26),
678 "EE_READY" => Some(27),
679 "SPM_READY" => Some(28),
680 _ => None,
681 },
682 "atmega32u4" => match intr {
683 "RESET" => Some(0),
684 "INT0" => Some(1),
685 "INT1" => Some(2),
686 "INT2" => Some(3),
687 "INT3" => Some(4),
688 "RESERVED1" => Some(5),
689 "RESERVED2" => Some(6),
690 "INT6" => Some(7),
691 "RESERVED3" => Some(8),
692 "PCINT0" => Some(9),
693 "USB_GEN" => Some(10),
694 "USB_COM" => Some(11),
695 "WDT" => Some(12),
696 "RESERVED4" => Some(13),
697 "RESERVED5" => Some(14),
698 "RESERVED6" => Some(15),
699 "TIMER1_CAPT" => Some(16),
700 "TIMER1_COMPA" => Some(17),
701 "TIMER1_COMPB" => Some(18),
702 "TIMER1_COMPC" => Some(19),
703 "TIMER1_OVF" => Some(20),
704 "TIMER0_COMPA" => Some(21),
705 "TIMER0_COMPB" => Some(22),
706 "TIMER0_OVF" => Some(23),
707 "SPI_STC" => Some(24),
708 "USART1_RX" => Some(25),
709 "USART1_UDRE" => Some(26),
710 "USART1_TX" => Some(27),
711 "ANALOG_COMP" => Some(28),
712 "ADC" => Some(29),
713 "EE_READY" => Some(30),
714 "TIMER3_CAPT" => Some(31),
715 "TIMER3_COMPA" => Some(32),
716 "TIMER3_COMPB" => Some(33),
717 "TIMER3_COMPC" => Some(34),
718 "TIMER3_OVF" => Some(35),
719 "TWI" => Some(36),
720 "SPM_READY" => Some(37),
721 "TIMER4_COMPA" => Some(38),
722 "TIMER4_COMPB" => Some(39),
723 "TIMER4_COMPD" => Some(40),
724 "TIMER4_OVF" => Some(41),
725 "TIMER4_FPF" => Some(42),
726 _ => None,
727 },
728 "atmega4808" => match intr {
729 "CRCSCAN_NMI" => Some(1),
730 "BOD_VLM" => Some(2),
731 "RTC_CNT" => Some(3),
732 "RTC_PIT" => Some(4),
733 "CCL_CCL" => Some(5),
734 "PORTA_PORT" => Some(6),
735 "TCA0_LUNF_OVF" => Some(7),
736 "TCA0_HUNF" => Some(8),
737 "TCA0_CMP0_LCMP0" => Some(9),
738 "TCA0_CMP1_LCMP1" => Some(10),
739 "TCA0_CMP2_LCMP2" => Some(11),
740 "TCB0_INT" => Some(12),
741 "TCB1_INT" => Some(13),
742 "TWI0_TWIS" => Some(14),
743 "TWI0_TWIM" => Some(15),
744 "SPI0_INT" => Some(16),
745 "USART0_RXC" => Some(17),
746 "USART0_DRE" => Some(18),
747 "USART0_TXC" => Some(19),
748 "PORTD_PORT" => Some(20),
749 "AC0_AC" => Some(21),
750 "ADC0_RESRDY" => Some(22),
751 "ADC0_WCOMP" => Some(23),
752 "PORTC_PORT" => Some(24),
753 "TCB2_INT" => Some(25),
754 "USART1_RXC" => Some(26),
755 "USART1_DRE" => Some(27),
756 "USART1_TXC" => Some(28),
757 "PORTF_PORT" => Some(29),
758 "NVMCTRL_EE" => Some(30),
759 "USART2_RXC" => Some(31),
760 "USART2_DRE" => Some(32),
761 "USART2_TXC" => Some(33),
762 "PORTB_PORT" => Some(34),
763 "PORTE_PORT" => Some(35),
764 _ => None,
765 },
766 "atmega4809" => match intr {
767 "CRCSCAN_NMI" => Some(1),
768 "BOD_VLM" => Some(2),
769 "RTC_CNT" => Some(3),
770 "RTC_PIT" => Some(4),
771 "CCL_CCL" => Some(5),
772 "PORTA_PORT" => Some(6),
773 "TCA0_LUNF_OVF" => Some(7),
774 "TCA0_HUNF" => Some(8),
775 "TCA0_CMP0_LCMP0" => Some(9),
776 "TCA0_CMP1_LCMP1" => Some(10),
777 "TCA0_CMP2_LCMP2" => Some(11),
778 "TCB0_INT" => Some(12),
779 "TCB1_INT" => Some(13),
780 "TWI0_TWIS" => Some(14),
781 "TWI0_TWIM" => Some(15),
782 "SPI0_INT" => Some(16),
783 "USART0_RXC" => Some(17),
784 "USART0_DRE" => Some(18),
785 "USART0_TXC" => Some(19),
786 "PORTD_PORT" => Some(20),
787 "AC0_AC" => Some(21),
788 "ADC0_RESRDY" => Some(22),
789 "ADC0_WCOMP" => Some(23),
790 "PORTC_PORT" => Some(24),
791 "TCB2_INT" => Some(25),
792 "USART1_RXC" => Some(26),
793 "USART1_DRE" => Some(27),
794 "USART1_TXC" => Some(28),
795 "PORTF_PORT" => Some(29),
796 "NVMCTRL_EE" => Some(30),
797 "USART2_RXC" => Some(31),
798 "USART2_DRE" => Some(32),
799 "USART2_TXC" => Some(33),
800 "PORTB_PORT" => Some(34),
801 "PORTE_PORT" => Some(35),
802 "TCB3_INT" => Some(36),
803 "USART3_RXC" => Some(37),
804 "USART3_DRE" => Some(38),
805 "USART3_TXC" => Some(39),
806 _ => None,
807 },
808 "atmega48p" => match intr {
809 "RESET" => Some(0),
810 "INT0" => Some(1),
811 "INT1" => Some(2),
812 "PCINT0" => Some(3),
813 "PCINT1" => Some(4),
814 "PCINT2" => Some(5),
815 "WDT" => Some(6),
816 "TIMER2_COMPA" => Some(7),
817 "TIMER2_COMPB" => Some(8),
818 "TIMER2_OVF" => Some(9),
819 "TIMER1_CAPT" => Some(10),
820 "TIMER1_COMPA" => Some(11),
821 "TIMER1_COMPB" => Some(12),
822 "TIMER1_OVF" => Some(13),
823 "TIMER0_COMPA" => Some(14),
824 "TIMER0_COMPB" => Some(15),
825 "TIMER0_OVF" => Some(16),
826 "SPI_STC" => Some(17),
827 "USART_RX" => Some(18),
828 "USART_UDRE" => Some(19),
829 "USART_TX" => Some(20),
830 "ADC" => Some(21),
831 "EE_READY" => Some(22),
832 "ANALOG_COMP" => Some(23),
833 "TWI" => Some(24),
834 "SPM_READY" => Some(25),
835 _ => None,
836 },
837 "atmega64" => match intr {
838 "RESET" => Some(0),
839 "INT0" => Some(1),
840 "INT1" => Some(2),
841 "INT2" => Some(3),
842 "INT3" => Some(4),
843 "INT4" => Some(5),
844 "INT5" => Some(6),
845 "INT6" => Some(7),
846 "INT7" => Some(8),
847 "TIMER2_COMP" => Some(9),
848 "TIMER2_OVF" => Some(10),
849 "TIMER1_CAPT" => Some(11),
850 "TIMER1_COMPA" => Some(12),
851 "TIMER1_COMPB" => Some(13),
852 "TIMER1_OVF" => Some(14),
853 "TIMER0_COMP" => Some(15),
854 "TIMER0_OVF" => Some(16),
855 "SPI_STC" => Some(17),
856 "USART0_RX" => Some(18),
857 "USART0_UDRE" => Some(19),
858 "USART0_TX" => Some(20),
859 "ADC" => Some(21),
860 "EE_READY" => Some(22),
861 "ANALOG_COMP" => Some(23),
862 "TIMER1_COMPC" => Some(24),
863 "TIMER3_CAPT" => Some(25),
864 "TIMER3_COMPA" => Some(26),
865 "TIMER3_COMPB" => Some(27),
866 "TIMER3_COMPC" => Some(28),
867 "TIMER3_OVF" => Some(29),
868 "USART1_RX" => Some(30),
869 "USART1_UDRE" => Some(31),
870 "USART1_TX" => Some(32),
871 "TWI" => Some(33),
872 "SPM_READY" => Some(34),
873 _ => None,
874 },
875 "atmega644" => match intr {
876 "RESET" => Some(0),
877 "INT0" => Some(1),
878 "INT1" => Some(2),
879 "INT2" => Some(3),
880 "PCINT0" => Some(4),
881 "PCINT1" => Some(5),
882 "PCINT2" => Some(6),
883 "PCINT3" => Some(7),
884 "WDT" => Some(8),
885 "TIMER2_COMPA" => Some(9),
886 "TIMER2_COMPB" => Some(10),
887 "TIMER2_OVF" => Some(11),
888 "TIMER1_CAPT" => Some(12),
889 "TIMER1_COMPA" => Some(13),
890 "TIMER1_COMPB" => Some(14),
891 "TIMER1_OVF" => Some(15),
892 "TIMER0_COMPA" => Some(16),
893 "TIMER0_COMPB" => Some(17),
894 "TIMER0_OVF" => Some(18),
895 "SPI_STC" => Some(19),
896 "USART0_RX" => Some(20),
897 "USART0_UDRE" => Some(21),
898 "USART0_TX" => Some(22),
899 "ANALOG_COMP" => Some(23),
900 "ADC" => Some(24),
901 "EE_READY" => Some(25),
902 "TWI" => Some(26),
903 "SPM_READY" => Some(27),
904 _ => None,
905 },
906 "atmega8" => match intr {
907 "RESET" => Some(0),
908 "INT0" => Some(1),
909 "INT1" => Some(2),
910 "TIMER2_COMP" => Some(3),
911 "TIMER2_OVF" => Some(4),
912 "TIMER1_CAPT" => Some(5),
913 "TIMER1_COMPA" => Some(6),
914 "TIMER1_COMPB" => Some(7),
915 "TIMER1_OVF" => Some(8),
916 "TIMER0_OVF" => Some(9),
917 "SPI_STC" => Some(10),
918 "USART_RXC" => Some(11),
919 "USART_UDRE" => Some(12),
920 "USART_TXC" => Some(13),
921 "ADC" => Some(14),
922 "EE_RDY" => Some(15),
923 "ANA_COMP" => Some(16),
924 "TWI" => Some(17),
925 "SPM_RDY" => Some(18),
926 _ => None,
927 },
928 "atmega88p" => match intr {
929 "RESET" => Some(0),
930 "INT0" => Some(1),
931 "INT1" => Some(2),
932 "PCINT0" => Some(3),
933 "PCINT1" => Some(4),
934 "PCINT2" => Some(5),
935 "WDT" => Some(6),
936 "TIMER2_COMPA" => Some(7),
937 "TIMER2_COMPB" => Some(8),
938 "TIMER2_OVF" => Some(9),
939 "TIMER1_CAPT" => Some(10),
940 "TIMER1_COMPA" => Some(11),
941 "TIMER1_COMPB" => Some(12),
942 "TIMER1_OVF" => Some(13),
943 "TIMER0_COMPA" => Some(14),
944 "TIMER0_COMPB" => Some(15),
945 "TIMER0_OVF" => Some(16),
946 "SPI_STC" => Some(17),
947 "USART_RX" => Some(18),
948 "USART_UDRE" => Some(19),
949 "USART_TX" => Some(20),
950 "ADC" => Some(21),
951 "EE_READY" => Some(22),
952 "ANALOG_COMP" => Some(23),
953 "TWI" => Some(24),
954 "SPM_READY" => Some(25),
955 _ => None,
956 },
957 "atmega8u2" => match intr {
958 "RESET" => Some(0),
959 "INT0" => Some(1),
960 "INT1" => Some(2),
961 "INT2" => Some(3),
962 "INT3" => Some(4),
963 "INT4" => Some(5),
964 "INT5" => Some(6),
965 "INT6" => Some(7),
966 "INT7" => Some(8),
967 "PCINT0" => Some(9),
968 "PCINT1" => Some(10),
969 "USB_GEN" => Some(11),
970 "USB_COM" => Some(12),
971 "WDT" => Some(13),
972 "TIMER1_CAPT" => Some(14),
973 "TIMER1_COMPA" => Some(15),
974 "TIMER1_COMPB" => Some(16),
975 "TIMER1_COMPC" => Some(17),
976 "TIMER1_OVF" => Some(18),
977 "TIMER0_COMPA" => Some(19),
978 "TIMER0_COMPB" => Some(20),
979 "TIMER0_OVF" => Some(21),
980 "SPI_STC" => Some(22),
981 "USART1_RX" => Some(23),
982 "USART1_UDRE" => Some(24),
983 "USART1_TX" => Some(25),
984 "ANALOG_COMP" => Some(26),
985 "EE_READY" => Some(27),
986 "SPM_READY" => Some(28),
987 _ => None,
988 },
989 "attiny13a" => match intr {
990 "RESET" => Some(0),
991 "INT0" => Some(1),
992 "PCINT0" => Some(2),
993 "TIM0_OVF" => Some(3),
994 "EE_RDY" => Some(4),
995 "ANA_COMP" => Some(5),
996 "TIM0_COMPA" => Some(6),
997 "TIM0_COMPB" => Some(7),
998 "WDT" => Some(8),
999 "ADC" => Some(9),
1000 _ => None,
1001 },
1002 "attiny1614" => match intr {
1003 "CRCSCAN_NMI" => Some(1),
1004 "BOD_VLM" => Some(2),
1005 "PORTA_PORT" => Some(3),
1006 "PORTB_PORT" => Some(4),
1007 "RTC_CNT" => Some(6),
1008 "RTC_PIT" => Some(7),
1009 "TCA0_LUNF_OVF" => Some(8),
1010 "TCA0_HUNF" => Some(9),
1011 "TCA0_CMP0_LCMP0" => Some(10),
1012 "TCA0_CMP1_LCMP1" => Some(11),
1013 "TCA0_CMP2_LCMP2" => Some(12),
1014 "TCB0_INT" => Some(13),
1015 "TCB1_INT" => Some(14),
1016 "TCD0_OVF" => Some(15),
1017 "TCD0_TRIG" => Some(16),
1018 "AC0_AC" => Some(17),
1019 "AC1_AC" => Some(18),
1020 "AC2_AC" => Some(19),
1021 "ADC0_RESRDY" => Some(20),
1022 "ADC0_WCOMP" => Some(21),
1023 "ADC1_RESRDY" => Some(22),
1024 "ADC1_WCOMP" => Some(23),
1025 "TWI0_TWIS" => Some(24),
1026 "TWI0_TWIM" => Some(25),
1027 "SPI0_INT" => Some(26),
1028 "USART0_RXC" => Some(27),
1029 "USART0_DRE" => Some(28),
1030 "USART0_TXC" => Some(29),
1031 "NVMCTRL_EE" => Some(30),
1032 _ => None,
1033 },
1034 "attiny167" => match intr {
1035 "RESET" => Some(0),
1036 "INT0" => Some(1),
1037 "INT1" => Some(2),
1038 "PCINT0" => Some(3),
1039 "PCINT1" => Some(4),
1040 "WDT" => Some(5),
1041 "TIMER1_CAPT" => Some(6),
1042 "TIMER1_COMPA" => Some(7),
1043 "TIMER1_COMPB" => Some(8),
1044 "TIMER1_OVF" => Some(9),
1045 "TIMER0_COMPA" => Some(10),
1046 "TIMER0_OVF" => Some(11),
1047 "LIN_TC" => Some(12),
1048 "LIN_ERR" => Some(13),
1049 "SPI_STC" => Some(14),
1050 "ADC" => Some(15),
1051 "EE_RDY" => Some(16),
1052 "ANA_COMP" => Some(17),
1053 "USI_START" => Some(18),
1054 "USI_OVF" => Some(19),
1055 _ => None,
1056 },
1057 "attiny202" => match intr {
1058 "CRCSCAN_NMI" => Some(1),
1059 "BOD_VLM" => Some(2),
1060 "PORTA_PORT" => Some(3),
1061 "RTC_CNT" => Some(6),
1062 "RTC_PIT" => Some(7),
1063 "TCA0_LUNF_OVF" => Some(8),
1064 "TCA0_HUNF" => Some(9),
1065 "TCA0_CMP0_LCMP0" => Some(10),
1066 "TCA0_CMP1_LCMP1" => Some(11),
1067 "TCA0_CMP2_LCMP2" => Some(12),
1068 "TCB0_INT" => Some(13),
1069 "AC0_AC" => Some(16),
1070 "ADC0_RESRDY" => Some(17),
1071 "ADC0_WCOMP" => Some(18),
1072 "TWI0_TWIS" => Some(19),
1073 "TWI0_TWIM" => Some(20),
1074 "SPI0_INT" => Some(21),
1075 "USART0_RXC" => Some(22),
1076 "USART0_DRE" => Some(23),
1077 "USART0_TXC" => Some(24),
1078 "NVMCTRL_EE" => Some(25),
1079 _ => None,
1080 },
1081 "attiny212" => match intr {
1082 "CRCSCAN_NMI" => Some(1),
1083 "BOD_VLM" => Some(2),
1084 "PORTA_PORT" => Some(3),
1085 "RTC_CNT" => Some(6),
1086 "RTC_PIT" => Some(7),
1087 "TCA0_LUNF_OVF" => Some(8),
1088 "TCA0_HUNF" => Some(9),
1089 "TCA0_LCMP0_CMP0" => Some(10),
1090 "TCA0_CMP1_LCMP1" => Some(11),
1091 "TCA0_CMP2_LCMP2" => Some(12),
1092 "TCB0_INT" => Some(13),
1093 "TCD0_OVF" => Some(14),
1094 "TCD0_TRIG" => Some(15),
1095 "AC0_AC" => Some(16),
1096 "ADC0_RESRDY" => Some(17),
1097 "ADC0_WCOMP" => Some(18),
1098 "TWI0_TWIS" => Some(19),
1099 "TWI0_TWIM" => Some(20),
1100 "SPI0_INT" => Some(21),
1101 "USART0_RXC" => Some(22),
1102 "USART0_DRE" => Some(23),
1103 "USART0_TXC" => Some(24),
1104 "NVMCTRL_EE" => Some(25),
1105 _ => None,
1106 },
1107 "attiny214" => match intr {
1108 "CRCSCAN_NMI" => Some(1),
1109 "BOD_VLM" => Some(2),
1110 "PORTA_PORT" => Some(3),
1111 "PORTB_PORT" => Some(4),
1112 "RTC_CNT" => Some(6),
1113 "RTC_PIT" => Some(7),
1114 "TCA0_LUNF_OVF" => Some(8),
1115 "TCA0_HUNF" => Some(9),
1116 "TCA0_LCMP0_CMP0" => Some(10),
1117 "TCA0_CMP1_LCMP1" => Some(11),
1118 "TCA0_CMP2_LCMP2" => Some(12),
1119 "TCB0_INT" => Some(13),
1120 "TCD0_OVF" => Some(14),
1121 "TCD0_TRIG" => Some(15),
1122 "AC0_AC" => Some(16),
1123 "ADC0_RESRDY" => Some(17),
1124 "ADC0_WCOMP" => Some(18),
1125 "TWI0_TWIS" => Some(19),
1126 "TWI0_TWIM" => Some(20),
1127 "SPI0_INT" => Some(21),
1128 "USART0_RXC" => Some(22),
1129 "USART0_DRE" => Some(23),
1130 "USART0_TXC" => Some(24),
1131 "NVMCTRL_EE" => Some(25),
1132 _ => None,
1133 },
1134 "attiny2313" => match intr {
1135 "RESET" => Some(0),
1136 "INT0" => Some(1),
1137 "INT1" => Some(2),
1138 "TIMER1_CAPT" => Some(3),
1139 "TIMER1_COMPA" => Some(4),
1140 "TIMER1_OVF" => Some(5),
1141 "TIMER0_OVF" => Some(6),
1142 "USART_RX" => Some(7),
1143 "USART_UDRE" => Some(8),
1144 "USART_TX" => Some(9),
1145 "ANA_COMP" => Some(10),
1146 "PCINT" => Some(11),
1147 "TIMER1_COMPB" => Some(12),
1148 "TIMER0_COMPA" => Some(13),
1149 "TIMER0_COMPB" => Some(14),
1150 "USI_START" => Some(15),
1151 "USI_OVERFLOW" => Some(16),
1152 "EEPROM_READY" => Some(17),
1153 "WDT_OVERFLOW" => Some(18),
1154 _ => None,
1155 },
1156 "attiny2313a" => match intr {
1157 "RESET" => Some(0),
1158 "INT0" => Some(1),
1159 "INT1" => Some(2),
1160 "TIMER1_CAPT" => Some(3),
1161 "TIMER1_COMPA" => Some(4),
1162 "TIMER1_OVF" => Some(5),
1163 "TIMER0_OVF" => Some(6),
1164 "USART_RX" => Some(7),
1165 "USART_UDRE" => Some(8),
1166 "USART_TX" => Some(9),
1167 "ANA_COMP" => Some(10),
1168 "PCINT_B" => Some(11),
1169 "TIMER1_COMPB" => Some(12),
1170 "TIMER0_COMPA" => Some(13),
1171 "TIMER0_COMPB" => Some(14),
1172 "USI_START" => Some(15),
1173 "USI_OVERFLOW" => Some(16),
1174 "EEPROM_READY" => Some(17),
1175 "WDT_OVERFLOW" => Some(18),
1176 "PCINT_A" => Some(19),
1177 "PCINT_D" => Some(20),
1178 _ => None,
1179 },
1180 "attiny26" => match intr {
1181 "RESET" => Some(0),
1182 "INT0" => Some(1),
1183 "IO_PINS" => Some(2),
1184 "TIMER1_CMPA" => Some(3),
1185 "TIMER1_CMPB" => Some(4),
1186 "TIMER1_OVF1" => Some(5),
1187 "TIMER0_OVF0" => Some(6),
1188 "USI_STRT" => Some(7),
1189 "USI_OVF" => Some(8),
1190 "EE_RDY" => Some(9),
1191 "ANA_COMP" => Some(10),
1192 "ADC" => Some(11),
1193 _ => None,
1194 },
1195 "attiny402" => match intr {
1196 "CRCSCAN_NMI" => Some(1),
1197 "BOD_VLM" => Some(2),
1198 "PORTA_PORT" => Some(3),
1199 "RTC_CNT" => Some(6),
1200 "RTC_PIT" => Some(7),
1201 "TCA0_LUNF_OVF" => Some(8),
1202 "TCA0_HUNF" => Some(9),
1203 "TCA0_CMP0_LCMP0" => Some(10),
1204 "TCA0_CMP1_LCMP1" => Some(11),
1205 "TCA0_CMP2_LCMP2" => Some(12),
1206 "TCB0_INT" => Some(13),
1207 "AC0_AC" => Some(16),
1208 "ADC0_RESRDY" => Some(17),
1209 "ADC0_WCOMP" => Some(18),
1210 "TWI0_TWIS" => Some(19),
1211 "TWI0_TWIM" => Some(20),
1212 "SPI0_INT" => Some(21),
1213 "USART0_RXC" => Some(22),
1214 "USART0_DRE" => Some(23),
1215 "USART0_TXC" => Some(24),
1216 "NVMCTRL_EE" => Some(25),
1217 _ => None,
1218 },
1219 "attiny404" => match intr {
1220 "CRCSCAN_NMI" => Some(1),
1221 "BOD_VLM" => Some(2),
1222 "PORTA_PORT" => Some(3),
1223 "PORTB_PORT" => Some(4),
1224 "RTC_CNT" => Some(6),
1225 "RTC_PIT" => Some(7),
1226 "TCA0_LUNF_OVF" => Some(8),
1227 "TCA0_HUNF" => Some(9),
1228 "TCA0_CMP0_LCMP0" => Some(10),
1229 "TCA0_CMP1_LCMP1" => Some(11),
1230 "TCA0_CMP2_LCMP2" => Some(12),
1231 "TCB0_INT" => Some(13),
1232 "AC0_AC" => Some(16),
1233 "ADC0_RESRDY" => Some(17),
1234 "ADC0_WCOMP" => Some(18),
1235 "TWI0_TWIS" => Some(19),
1236 "TWI0_TWIM" => Some(20),
1237 "SPI0_INT" => Some(21),
1238 "USART0_RXC" => Some(22),
1239 "USART0_DRE" => Some(23),
1240 "USART0_TXC" => Some(24),
1241 "NVMCTRL_EE" => Some(25),
1242 _ => None,
1243 },
1244 "attiny412" => match intr {
1245 "CRCSCAN_NMI" => Some(1),
1246 "BOD_VLM" => Some(2),
1247 "PORTA_PORT" => Some(3),
1248 "RTC_CNT" => Some(6),
1249 "RTC_PIT" => Some(7),
1250 "TCA0_LUNF_OVF" => Some(8),
1251 "TCA0_HUNF" => Some(9),
1252 "TCA0_LCMP0_CMP0" => Some(10),
1253 "TCA0_CMP1_LCMP1" => Some(11),
1254 "TCA0_CMP2_LCMP2" => Some(12),
1255 "TCB0_INT" => Some(13),
1256 "TCD0_OVF" => Some(14),
1257 "TCD0_TRIG" => Some(15),
1258 "AC0_AC" => Some(16),
1259 "ADC0_RESRDY" => Some(17),
1260 "ADC0_WCOMP" => Some(18),
1261 "TWI0_TWIS" => Some(19),
1262 "TWI0_TWIM" => Some(20),
1263 "SPI0_INT" => Some(21),
1264 "USART0_RXC" => Some(22),
1265 "USART0_DRE" => Some(23),
1266 "USART0_TXC" => Some(24),
1267 "NVMCTRL_EE" => Some(25),
1268 _ => None,
1269 },
1270 "attiny414" => match intr {
1271 "CRCSCAN_NMI" => Some(1),
1272 "BOD_VLM" => Some(2),
1273 "PORTA_PORT" => Some(3),
1274 "PORTB_PORT" => Some(4),
1275 "RTC_CNT" => Some(6),
1276 "RTC_PIT" => Some(7),
1277 "TCA0_LUNF_OVF" => Some(8),
1278 "TCA0_HUNF" => Some(9),
1279 "TCA0_LCMP0_CMP0" => Some(10),
1280 "TCA0_CMP1_LCMP1" => Some(11),
1281 "TCA0_CMP2_LCMP2" => Some(12),
1282 "TCB0_INT" => Some(13),
1283 "TCD0_OVF" => Some(14),
1284 "TCD0_TRIG" => Some(15),
1285 "AC0_AC" => Some(16),
1286 "ADC0_RESRDY" => Some(17),
1287 "ADC0_WCOMP" => Some(18),
1288 "TWI0_TWIS" => Some(19),
1289 "TWI0_TWIM" => Some(20),
1290 "SPI0_INT" => Some(21),
1291 "USART0_RXC" => Some(22),
1292 "USART0_DRE" => Some(23),
1293 "USART0_TXC" => Some(24),
1294 "NVMCTRL_EE" => Some(25),
1295 _ => None,
1296 },
1297 "attiny416" => match intr {
1298 "CRCSCAN_NMI" => Some(1),
1299 "BOD_VLM" => Some(2),
1300 "PORTA_PORT" => Some(3),
1301 "PORTB_PORT" => Some(4),
1302 "PORTC_PORT" => Some(5),
1303 "RTC_CNT" => Some(6),
1304 "RTC_PIT" => Some(7),
1305 "TCA0_LUNF_OVF" => Some(8),
1306 "TCA0_HUNF" => Some(9),
1307 "TCA0_LCMP0_CMP0" => Some(10),
1308 "TCA0_CMP1_LCMP1" => Some(11),
1309 "TCA0_CMP2_LCMP2" => Some(12),
1310 "TCB0_INT" => Some(13),
1311 "TCD0_OVF" => Some(14),
1312 "TCD0_TRIG" => Some(15),
1313 "AC0_AC" => Some(16),
1314 "ADC0_RESRDY" => Some(17),
1315 "ADC0_WCOMP" => Some(18),
1316 "TWI0_TWIS" => Some(19),
1317 "TWI0_TWIM" => Some(20),
1318 "SPI0_INT" => Some(21),
1319 "USART0_RXC" => Some(22),
1320 "USART0_DRE" => Some(23),
1321 "USART0_TXC" => Some(24),
1322 "NVMCTRL_EE" => Some(25),
1323 _ => None,
1324 },
1325 "attiny44a" => match intr {
1326 "RESET" => Some(0),
1327 "EXT_INT0" => Some(1),
1328 "PCINT0" => Some(2),
1329 "PCINT1" => Some(3),
1330 "WDT" => Some(4),
1331 "TIM1_CAPT" => Some(5),
1332 "TIM1_COMPA" => Some(6),
1333 "TIM1_COMPB" => Some(7),
1334 "TIM1_OVF" => Some(8),
1335 "TIM0_COMPA" => Some(9),
1336 "TIM0_COMPB" => Some(10),
1337 "TIM0_OVF" => Some(11),
1338 "ANA_COMP" => Some(12),
1339 "ADC" => Some(13),
1340 "EE_RDY" => Some(14),
1341 "USI_STR" => Some(15),
1342 "USI_OVF" => Some(16),
1343 _ => None,
1344 },
1345 "attiny816" => match intr {
1346 "CRCSCAN_NMI" => Some(1),
1347 "BOD_VLM" => Some(2),
1348 "PORTA_PORT" => Some(3),
1349 "PORTB_PORT" => Some(4),
1350 "PORTC_PORT" => Some(5),
1351 "RTC_CNT" => Some(6),
1352 "RTC_PIT" => Some(7),
1353 "TCA0_LUNF_OVF" => Some(8),
1354 "TCA0_HUNF" => Some(9),
1355 "TCA0_CMP0_LCMP0" => Some(10),
1356 "TCA0_CMP1_LCMP1" => Some(11),
1357 "TCA0_CMP2_LCMP2" => Some(12),
1358 "TCB0_INT" => Some(13),
1359 "TCD0_OVF" => Some(14),
1360 "TCD0_TRIG" => Some(15),
1361 "AC0_AC" => Some(16),
1362 "ADC0_RESRDY" => Some(17),
1363 "ADC0_WCOMP" => Some(18),
1364 "TWI0_TWIS" => Some(19),
1365 "TWI0_TWIM" => Some(20),
1366 "SPI0_INT" => Some(21),
1367 "USART0_RXC" => Some(22),
1368 "USART0_DRE" => Some(23),
1369 "USART0_TXC" => Some(24),
1370 "NVMCTRL_EE" => Some(25),
1371 _ => None,
1372 },
1373 "attiny828" => match intr {
1374 "RESET" => Some(0),
1375 "INT0" => Some(1),
1376 "INT1" => Some(2),
1377 "PCINT0" => Some(3),
1378 "PCINT1" => Some(4),
1379 "PCINT2" => Some(5),
1380 "PCINT3" => Some(6),
1381 "WDT" => Some(7),
1382 "TIMER1_CAPT" => Some(8),
1383 "TIMER1_COMPA" => Some(9),
1384 "TIMER1_COMPB" => Some(10),
1385 "TIMER1_OVF" => Some(11),
1386 "TIMER0_COMPA" => Some(12),
1387 "TIMER0_COMPB" => Some(13),
1388 "TIMER0_OVF" => Some(14),
1389 "SPI_STC" => Some(15),
1390 "USART_START" => Some(16),
1391 "USART_RX" => Some(17),
1392 "USART_UDRE" => Some(18),
1393 "USART_TX" => Some(19),
1394 "ADC" => Some(20),
1395 "EE_READY" => Some(21),
1396 "ANALOG_COMP" => Some(22),
1397 "TWI_SLAVE" => Some(23),
1398 "SPM_READY" => Some(24),
1399 "QTRIP" => Some(25),
1400 _ => None,
1401 },
1402 "attiny84" => match intr {
1403 "RESET" => Some(0),
1404 "EXT_INT0" => Some(1),
1405 "PCINT0" => Some(2),
1406 "PCINT1" => Some(3),
1407 "WDT" => Some(4),
1408 "TIM1_CAPT" => Some(5),
1409 "TIM1_COMPA" => Some(6),
1410 "TIM1_COMPB" => Some(7),
1411 "TIM1_OVF" => Some(8),
1412 "TIM0_COMPA" => Some(9),
1413 "TIM0_COMPB" => Some(10),
1414 "TIM0_OVF" => Some(11),
1415 "ANA_COMP" => Some(12),
1416 "ADC" => Some(13),
1417 "EE_RDY" => Some(14),
1418 "USI_STR" => Some(15),
1419 "USI_OVF" => Some(16),
1420 _ => None,
1421 },
1422 "attiny841" => match intr {
1423 "RESET" => Some(0),
1424 "INT0" => Some(1),
1425 "PCINT0" => Some(2),
1426 "PCINT1" => Some(3),
1427 "WDT" => Some(4),
1428 "TIMER1_CAPT" => Some(5),
1429 "TIMER1_COMPA" => Some(6),
1430 "TIMER1_COMPB" => Some(7),
1431 "TIMER1_OVF" => Some(8),
1432 "TIMER0_COMPA" => Some(9),
1433 "TIMER0_COMPB" => Some(10),
1434 "TIMER0_OVF" => Some(11),
1435 "ANA_COMP0" => Some(12),
1436 "ADC" => Some(13),
1437 "EE_RDY" => Some(14),
1438 "ANA_COMP1" => Some(15),
1439 "TIMER2_CAPT" => Some(16),
1440 "TIMER2_COMPA" => Some(17),
1441 "TIMER2_COMPB" => Some(18),
1442 "TIMER2_OVF" => Some(19),
1443 "SPI" => Some(20),
1444 "USART0_START" => Some(21),
1445 "USART0_RX" => Some(22),
1446 "USART0_UDRE" => Some(23),
1447 "USART0_TX" => Some(24),
1448 "USART1_START" => Some(25),
1449 "USART1_RX" => Some(26),
1450 "USART1_UDRE" => Some(27),
1451 "USART1_TX" => Some(28),
1452 "TWI_SLAVE" => Some(29),
1453 _ => None,
1454 },
1455 "attiny84a" => match intr {
1456 "RESET" => Some(0),
1457 "EXT_INT0" => Some(1),
1458 "PCINT0" => Some(2),
1459 "PCINT1" => Some(3),
1460 "WDT" => Some(4),
1461 "TIM1_CAPT" => Some(5),
1462 "TIM1_COMPA" => Some(6),
1463 "TIM1_COMPB" => Some(7),
1464 "TIM1_OVF" => Some(8),
1465 "TIM0_COMPA" => Some(9),
1466 "TIM0_COMPB" => Some(10),
1467 "TIM0_OVF" => Some(11),
1468 "ANA_COMP" => Some(12),
1469 "ADC" => Some(13),
1470 "EE_RDY" => Some(14),
1471 "USI_STR" => Some(15),
1472 "USI_OVF" => Some(16),
1473 _ => None,
1474 },
1475 "attiny85" => match intr {
1476 "RESET" => Some(0),
1477 "INT0" => Some(1),
1478 "PCINT0" => Some(2),
1479 "TIMER1_COMPA" => Some(3),
1480 "TIMER1_OVF" => Some(4),
1481 "TIMER0_OVF" => Some(5),
1482 "EE_RDY" => Some(6),
1483 "ANA_COMP" => Some(7),
1484 "ADC" => Some(8),
1485 "TIMER1_COMPB" => Some(9),
1486 "TIMER0_COMPA" => Some(10),
1487 "TIMER0_COMPB" => Some(11),
1488 "WDT" => Some(12),
1489 "USI_START" => Some(13),
1490 "USI_OVF" => Some(14),
1491 _ => None,
1492 },
1493 "attiny861" => match intr {
1494 "RESET" => Some(0),
1495 "INT0" => Some(1),
1496 "PCINT" => Some(2),
1497 "TIMER1_COMPA" => Some(3),
1498 "TIMER1_COMPB" => Some(4),
1499 "TIMER1_OVF" => Some(5),
1500 "TIMER0_OVF" => Some(6),
1501 "USI_START" => Some(7),
1502 "USI_OVF" => Some(8),
1503 "EE_RDY" => Some(9),
1504 "ANA_COMP" => Some(10),
1505 "ADC" => Some(11),
1506 "WDT" => Some(12),
1507 "INT1" => Some(13),
1508 "TIMER0_COMPA" => Some(14),
1509 "TIMER0_COMPB" => Some(15),
1510 "TIMER0_CAPT" => Some(16),
1511 "TIMER1_COMPD" => Some(17),
1512 "FAULT_PROTECTION" => Some(18),
1513 _ => None,
1514 },
1515 "attiny88" => match intr {
1516 "RESET" => Some(0),
1517 "INT0" => Some(1),
1518 "INT1" => Some(2),
1519 "PCINT0" => Some(3),
1520 "PCINT1" => Some(4),
1521 "PCINT2" => Some(5),
1522 "PCINT3" => Some(6),
1523 "WDT" => Some(7),
1524 "TIMER1_CAPT" => Some(8),
1525 "TIMER1_COMPA" => Some(9),
1526 "TIMER1_COMPB" => Some(10),
1527 "TIMER1_OVF" => Some(11),
1528 "TIMER0_COMPA" => Some(12),
1529 "TIMER0_COMPB" => Some(13),
1530 "TIMER0_OVF" => Some(14),
1531 "SPI_STC" => Some(15),
1532 "ADC" => Some(16),
1533 "EE_RDY" => Some(17),
1534 "ANALOG_COMP" => Some(18),
1535 "TWI" => Some(19),
1536 _ => None,
1537 },
1538 "avr64du28" => match intr {
1539 "CRCSCAN_NMI" => Some(1),
1540 "BOD_VLM" => Some(2),
1541 "CLKCTRL_CFD" => Some(3),
1542 "RTC_CNT" => Some(4),
1543 "RTC_PIT" => Some(5),
1544 "CCL_CCL" => Some(6),
1545 "USB0_BUSEVENT" => Some(7),
1546 "USB0_TRNCOMPL" => Some(8),
1547 "PORTA_PORT" => Some(9),
1548 "TCA0_LUNF_OVF" => Some(10),
1549 "TCA0_HUNF" => Some(11),
1550 "TCA0_CMP0_LCMP0" => Some(12),
1551 "TCA0_CMP1_LCMP1" => Some(13),
1552 "TCA0_CMP2_LCMP2" => Some(14),
1553 "TCB0_INT" => Some(15),
1554 "TWI0_TWIS" => Some(16),
1555 "TWI0_TWIM" => Some(17),
1556 "SPI0_INT" => Some(18),
1557 "USART0_RXC" => Some(19),
1558 "USART0_DRE" => Some(20),
1559 "USART0_TXC" => Some(21),
1560 "PORTD_PORT" => Some(22),
1561 "PORTC_PORT" => Some(23),
1562 "PORTF_PORT" => Some(24),
1563 "NVMCTRL_NVMREADY" => Some(25),
1564 "USART1_RXC" => Some(26),
1565 "USART1_DRE" => Some(27),
1566 "USART1_TXC" => Some(28),
1567 "TCB1_INT" => Some(29),
1568 "AC0_AC" => Some(30),
1569 "ADC0_ERROR" => Some(31),
1570 "ADC0_RESRDY" => Some(32),
1571 "ADC0_SAMPRDY" => Some(33),
1572 _ => None,
1573 },
1574 "avr64du32" => match intr {
1575 "CRCSCAN_NMI" => Some(1),
1576 "BOD_VLM" => Some(2),
1577 "CLKCTRL_CFD" => Some(3),
1578 "RTC_CNT" => Some(4),
1579 "RTC_PIT" => Some(5),
1580 "CCL_CCL" => Some(6),
1581 "USB0_BUSEVENT" => Some(7),
1582 "USB0_TRNCOMPL" => Some(8),
1583 "PORTA_PORT" => Some(9),
1584 "TCA0_LUNF_OVF" => Some(10),
1585 "TCA0_HUNF" => Some(11),
1586 "TCA0_CMP0_LCMP0" => Some(12),
1587 "TCA0_CMP1_LCMP1" => Some(13),
1588 "TCA0_CMP2_LCMP2" => Some(14),
1589 "TCB0_INT" => Some(15),
1590 "TWI0_TWIS" => Some(16),
1591 "TWI0_TWIM" => Some(17),
1592 "SPI0_INT" => Some(18),
1593 "USART0_RXC" => Some(19),
1594 "USART0_DRE" => Some(20),
1595 "USART0_TXC" => Some(21),
1596 "PORTD_PORT" => Some(22),
1597 "PORTC_PORT" => Some(23),
1598 "PORTF_PORT" => Some(24),
1599 "NVMCTRL_NVMREADY" => Some(25),
1600 "USART1_RXC" => Some(26),
1601 "USART1_DRE" => Some(27),
1602 "USART1_TXC" => Some(28),
1603 "TCB1_INT" => Some(29),
1604 "AC0_AC" => Some(30),
1605 "ADC0_ERROR" => Some(31),
1606 "ADC0_RESRDY" => Some(32),
1607 "ADC0_SAMPRDY" => Some(33),
1608 _ => None,
1609 },
1610 _ => None,
1611 }
1612}