Module attiny_hal::pac::adc::didr0

Digital Input Disable Register 0

Structs

• DIDR0_SPEC
  Digital Input Disable Register 0
• R
  Register DIDR0 reader
• W
  Register DIDR0 writer

Type Aliases

• ADC0D_R
  Field ADC0D reader - ADC0 Digital input Disable
• ADC0D_W
  Field ADC0D writer - ADC0 Digital input Disable
• ADC1D_R
  Field ADC1D reader - ADC1 Digital input Disable
• ADC1D_W
  Field ADC1D writer - ADC1 Digital input Disable
• ADC2D_R
  Field ADC2D reader - ADC2 Digital input Disable
• ADC2D_W
  Field ADC2D writer - ADC2 Digital input Disable
• ADC3D_R
  Field ADC3D reader - ADC3 Digital input Disable
• ADC3D_W
  Field ADC3D writer - ADC3 Digital input Disable