Enum attiny_hal::spi::SerialClockRate

pub enum SerialClockRate {
    OscfOver2 = 1,
    OscfOver4 = 2,
    OscfOver8 = 3,
    OscfOver16 = 4,
    OscfOver32 = 5,
    OscfOver64 = 6,
    OscfOver128 = 7,
}

Oscillator Clock Frequency division options.

The bus speed is calculated by dividing the IO clock by the prescaler:

F_sck = CLK_io / Prescaler

Please note that the overall transfer speed might be lower due to software overhead while sending / receiving.

Prescale	16 MHz Clock	8 MHz Clock
OscfOver2	8 MHz	4 MHz
OscfOver4	4 MHz	2 MHz
OscfOver8	2 MHz	1 MHz
OscfOver16	1 MHz	500 kHz
OscfOver32	500 kHz	250 kHz
OscfOver64	250 kHz	125 kHz
OscfOver128	125 kHz	62.5 kHz

Variants

OscfOver2 = 1

OscfOver4 = 2

OscfOver8 = 3

OscfOver16 = 4

OscfOver32 = 5

OscfOver64 = 6

OscfOver128 = 7

Implementations

impl SerialClockRate

pub fn into_divider(self) -> u8

Trait Implementations

impl Clone for SerialClockRate

fn clone(&self) -> SerialClockRate

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for SerialClockRate

fn fmt(&self, f: &mut Formatter<'_>) -> Result<(), Error>

Formats the value using the given formatter.

impl PartialEq for SerialClockRate

fn eq(&self, other: &SerialClockRate) -> bool

This method tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

This method tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for SerialClockRate

impl Eq for SerialClockRate

impl StructuralPartialEq for SerialClockRate