#[repr(u8)]pub enum USIWM_A {
DISABLED = 0,
THREE_WIRE = 1,
TWO_WIRE_SLAVE = 2,
TWO_WIRE_MASTER = 3,
}
Expand description
USI Wire Mode Bits
Value on reset: 0
Variants§
DISABLED = 0
0: All detectors disabled. Port pins operates as normal.
THREE_WIRE = 1
1: Three-wire mode. Uses DO, DI, and USCK pins.
TWO_WIRE_SLAVE = 2
2: Two-wire mode (Slave). Uses SDA (DI) and SCL (USCK) pins.
TWO_WIRE_MASTER = 3
3: Two-wire mode (Master). Uses SDA and SCL pins.
Trait Implementations§
source§impl PartialEq for USIWM_A
impl PartialEq for USIWM_A
impl Copy for USIWM_A
impl Eq for USIWM_A
impl StructuralPartialEq for USIWM_A
Auto Trait Implementations§
impl Freeze for USIWM_A
impl RefUnwindSafe for USIWM_A
impl Send for USIWM_A
impl Sync for USIWM_A
impl Unpin for USIWM_A
impl UnwindSafe for USIWM_A
Blanket Implementations§
source§impl<T> BorrowMut<T> for Twhere
T: ?Sized,
impl<T> BorrowMut<T> for Twhere
T: ?Sized,
source§fn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
Mutably borrows from an owned value. Read more