Struct attiny_hal::spi::Spi

pub struct Spi<H, SPI, SCLKPIN, MOSIPIN, MISOPIN, CSPIN> { /* private fields */ }

Behavior for a SPI interface.

Stores the SPI peripheral for register access. In addition, it takes ownership of the MOSI and MISO pins to ensure they are in the correct mode. Instantiate with the new method.

This can be used both with the embedded-hal 0.2 spi::FullDuplex trait, and with the embedded-hal 1.0 spi::SpiBus trait.

Implementations

impl<H, SPI, SCLKPIN, MOSIPIN, MISOPIN, CSPIN> Spi<H, SPI, SCLKPIN, MOSIPIN, MISOPIN, CSPIN>

where SPI: SpiOps<H, SCLKPIN, MOSIPIN, MISOPIN, CSPIN>, SCLKPIN: PinOps, MOSIPIN: PinOps, MISOPIN: PinOps, CSPIN: PinOps,

pub fn new( p: SPI, sclk: Pin<Output, SCLKPIN>, mosi: Pin<Output, MOSIPIN>, miso: Pin<Input<PullUp>, MISOPIN>, cs: Pin<Output, CSPIN>, settings: Settings ) -> (Spi<H, SPI, SCLKPIN, MOSIPIN, MISOPIN, CSPIN>, ChipSelectPin<CSPIN>)

Instantiate an SPI with the registers, SCLK/MOSI/MISO/CS pins, and settings, with the internal pull-up enabled on the MISO pin.

The pins are not actually used directly, but they are moved into the struct in order to enforce that they are in the correct mode, and cannot be used by anyone else while SPI is active. CS is placed into a ChipSelectPin instance and given back so that its output state can be changed as needed.

pub fn with_external_pullup( p: SPI, sclk: Pin<Output, SCLKPIN>, mosi: Pin<Output, MOSIPIN>, miso: Pin<Input<Floating>, MISOPIN>, cs: Pin<Output, CSPIN>, settings: Settings ) -> (Spi<H, SPI, SCLKPIN, MOSIPIN, MISOPIN, CSPIN>, ChipSelectPin<CSPIN>)

Instantiate an SPI with the registers, SCLK/MOSI/MISO/CS pins, and settings, with an external pull-up on the MISO pin.

The pins are not actually used directly, but they are moved into the struct in order to enforce that they are in the correct mode, and cannot be used by anyone else while SPI is active.

pub fn reconfigure( &mut self, settings: Settings ) -> Result<(), Error<Infallible>>

Reconfigure the SPI peripheral after initializing

pub fn release( self, cs: ChipSelectPin<CSPIN> ) -> (SPI, Pin<Output, SCLKPIN>, Pin<Output, MOSIPIN>, Pin<Input, MISOPIN>, Pin<Output, CSPIN>)

Disable the SPI device and release ownership of the peripheral and pins. Instance can no-longer be used after this is invoked.

Trait Implementations

impl<H, SPI, SCLKPIN, MOSIPIN, MISOPIN, CSPIN> ErrorType for Spi<H, SPI, SCLKPIN, MOSIPIN, MISOPIN, CSPIN>

where SPI: SpiOps<H, SCLKPIN, MOSIPIN, MISOPIN, CSPIN>, SCLKPIN: PinOps, MOSIPIN: PinOps, MISOPIN: PinOps, CSPIN: PinOps,

type Error = Infallible

Error type.

impl<H, SPI, SCLKPIN, MOSIPIN, MISOPIN, CSPIN> SpiBus for Spi<H, SPI, SCLKPIN, MOSIPIN, MISOPIN, CSPIN>

where SPI: SpiOps<H, SCLKPIN, MOSIPIN, MISOPIN, CSPIN>, SCLKPIN: PinOps, MOSIPIN: PinOps, MISOPIN: PinOps, CSPIN: PinOps,

fn flush( &mut self ) -> Result<(), <Spi<H, SPI, SCLKPIN, MOSIPIN, MISOPIN, CSPIN> as ErrorType>::Error>

Wait until all operations have completed and the bus is idle.

fn read( &mut self, read: &mut [u8] ) -> Result<(), <Spi<H, SPI, SCLKPIN, MOSIPIN, MISOPIN, CSPIN> as ErrorType>::Error>

Read words from the slave.

fn write( &mut self, write: &[u8] ) -> Result<(), <Spi<H, SPI, SCLKPIN, MOSIPIN, MISOPIN, CSPIN> as ErrorType>::Error>

Write words to the slave, ignoring all the incoming words.

fn transfer( &mut self, read: &mut [u8], write: &[u8] ) -> Result<(), <Spi<H, SPI, SCLKPIN, MOSIPIN, MISOPIN, CSPIN> as ErrorType>::Error>

Write and read simultaneously. write is written to the slave on MOSI and words received on MISO are stored in read.

fn transfer_in_place( &mut self, buffer: &mut [u8] ) -> Result<(), <Spi<H, SPI, SCLKPIN, MOSIPIN, MISOPIN, CSPIN> as ErrorType>::Error>

Write and read simultaneously. The contents of words are written to the slave, and the received words are stored into the same words buffer, overwriting it.

impl<H, SPI, SCLKPIN, MOSIPIN, MISOPIN, CSPIN> FullDuplex<u8> for Spi<H, SPI, SCLKPIN, MOSIPIN, MISOPIN, CSPIN>

where SPI: SpiOps<H, SCLKPIN, MOSIPIN, MISOPIN, CSPIN>, SCLKPIN: PinOps, MOSIPIN: PinOps, MISOPIN: PinOps, CSPIN: PinOps,

FullDuplex trait implementation, allowing this struct to be provided to drivers that require it for operation. Only 8-bit word size is supported for now.

fn send( &mut self, byte: u8 ) -> Result<(), Error<<Spi<H, SPI, SCLKPIN, MOSIPIN, MISOPIN, CSPIN> as FullDuplex<u8>>::Error>>

Sets up the device for transmission and sends the data

fn read( &mut self ) -> Result<u8, Error<<Spi<H, SPI, SCLKPIN, MOSIPIN, MISOPIN, CSPIN> as FullDuplex<u8>>::Error>>

Reads and returns the response in the data register

type Error = Infallible

An enumeration of SPI errors

impl<H, SPI, SCLKPIN, MOSIPIN, MISOPIN, CSPIN> Default<u8> for Spi<H, SPI, SCLKPIN, MOSIPIN, MISOPIN, CSPIN>

where SPI: SpiOps<H, SCLKPIN, MOSIPIN, MISOPIN, CSPIN>, SCLKPIN: PinOps, MOSIPIN: PinOps, MISOPIN: PinOps, CSPIN: PinOps,

Default Transfer trait implementation. Only 8-bit word size is supported for now.

impl<H, SPI, SCLKPIN, MOSIPIN, MISOPIN, CSPIN> Default<u8> for Spi<H, SPI, SCLKPIN, MOSIPIN, MISOPIN, CSPIN>

where SPI: SpiOps<H, SCLKPIN, MOSIPIN, MISOPIN, CSPIN>, SCLKPIN: PinOps, MOSIPIN: PinOps, MISOPIN: PinOps, CSPIN: PinOps,

Default Write trait implementation. Only 8-bit word size is supported for now.