Type Alias MUX_W

pub type MUX_W<'a, REG> = FieldWriter<'a, REG, 4, MUX_A>;

Field MUX writer - Analog Channel and Gain Selection Bits

Aliased Type

struct MUX_W<'a, REG> { /* private fields */ }

Implementations

impl<'a, REG> MUX_W<'a, REG>

where REG: Writable + RegisterSpec, REG::Ux: From<u8>,

pub fn adc0(self) -> &'a mut W<REG>

Single-ended Input ADC0

pub fn adc1(self) -> &'a mut W<REG>

Single-ended Input ADC1

pub fn adc2(self) -> &'a mut W<REG>

Single-ended Input ADC2

pub fn adc3(self) -> &'a mut W<REG>

Single-ended Input ADC3

pub fn adc2_adc2_1x(self) -> &'a mut W<REG>

Differential Inputs Positive ADC2 Negative ADC2 1x Gain

pub fn adc2_adc2_20x(self) -> &'a mut W<REG>

Differential Inputs Positive ADC2 Negative ADC2 20x Gain

pub fn adc2_adc3_1x(self) -> &'a mut W<REG>

Differential Inputs Positive ADC2 Negative ADC3 1x Gain

pub fn adc2_adc3_20x(self) -> &'a mut W<REG>

Differential Inputs Positive ADC2 Negative ADC3 20x Gain

pub fn adc0_adc0_1x(self) -> &'a mut W<REG>

Differential Inputs Positive ADC0 Negative ADC0 1x Gain

pub fn adc0_adc0_20x(self) -> &'a mut W<REG>

Differential Inputs Positive ADC0 Negative ADC0 20x Gain

pub fn adc0_adc1_1x(self) -> &'a mut W<REG>

Differential Inputs Positive ADC0 Negative ADC1 1x Gain

pub fn adc0_adc1_20x(self) -> &'a mut W<REG>

Differential Inputs Positive ADC0 Negative ADC1 20x Gain

pub fn adc_vbg(self) -> &'a mut W<REG>

Internal Reference (VBG)

pub fn adc_gnd(self) -> &'a mut W<REG>

0V (GND)

pub fn tempsens(self) -> &'a mut W<REG>

Temperature sensor