atmega_hal/
port.rs

Help
1//! Port
2//!
3//! # Example
4//!
5//! Complete example source code can be found in the repository:
6//! [`atmega2560-blink.rs`](https://github.com/Rahix/avr-hal/blob/main/examples/atmega2560/src/bin/atmega2560-blink.rs)
7//!
8//! ```
9//! let dp = atmega_hal::Peripherals::take().unwrap();
10//! let pins = atmega_hal::pins!(dp);
11//!
12//! let mut led = pins.pb7.into_output();
13//!
14//! loop {
15//!     led.toggle();
16//!     delay_ms(1000);
17//! }
18//! ```
19
20pub use avr_hal_generic::port::{mode, PinMode, PinOps};
21
22#[cfg(any(
23    feature = "atmega48p",
24    feature = "atmega88p",
25    feature = "atmega168",
26    feature = "atmega328p"
27))]
28avr_hal_generic::impl_port_traditional! {
29    enum Ports {
30        B: crate::pac::PORTB = [0, 1, 2, 3, 4, 5, 6, 7],
31        C: crate::pac::PORTC = [0, 1, 2, 3, 4, 5, 6],
32        D: crate::pac::PORTD = [0, 1, 2, 3, 4, 5, 6, 7],
33    }
34}
35
36#[cfg(any(feature = "atmega16", feature = "atmega32a"))]
37avr_hal_generic::impl_port_traditional_old! {
38    enum Ports {
39        A: crate::pac::PORTA = [0, 1, 2, 3, 4, 5, 6 ,7],
40        B: crate::pac::PORTB = [0, 1, 2, 3, 4, 5, 6 ,7],
41        C: crate::pac::PORTC = [0, 1, 2, 3, 4, 5, 6 ,7],
42        D: crate::pac::PORTD = [0, 1, 2, 3, 4, 5, 6 ,7],
43    }
44}
45
46#[cfg(feature = "atmega328pb")]
47avr_hal_generic::impl_port_traditional! {
48    enum Ports {
49        B: crate::pac::PORTB = [0, 1, 2, 3, 4, 5, 6, 7],
50        C: crate::pac::PORTC = [0, 1, 2, 3, 4, 5, 6],
51        D: crate::pac::PORTD = [0, 1, 2, 3, 4, 5, 6, 7],
52        E: crate::pac::PORTE = [0, 1, 2, 3],
53    }
54}
55
56#[cfg(feature = "atmega32u4")]
57avr_hal_generic::impl_port_traditional! {
58    enum Ports {
59        B: crate::pac::PORTB = [0, 1, 2, 3, 4, 5, 6, 7],
60        C: crate::pac::PORTC = [6, 7],
61        D: crate::pac::PORTD = [0, 1, 2, 3, 4, 5, 6, 7],
62        E: crate::pac::PORTE = [2, 6],
63        F: crate::pac::PORTF = [0, 1, 4, 5, 6, 7],
64    }
65}
66
67#[cfg(any(feature = "atmega128a"))]
68avr_hal_generic::impl_port_traditional_old! {
69    enum Ports {
70        A: crate::pac::PORTA = [0, 1, 2, 3, 4, 5, 6, 7],
71        B: crate::pac::PORTB = [0, 1, 2, 3, 4, 5, 6, 7],
72        C: crate::pac::PORTC = [0, 1, 2, 3, 4, 5, 6, 7],
73        D: crate::pac::PORTD = [0, 1, 2, 3, 4, 5, 6, 7],
74        E: crate::pac::PORTE = [0, 1, 2, 3, 4, 5, 6, 7],
75        F: crate::pac::PORTF = [0, 1, 2, 3, 4, 5, 6, 7],
76        G: crate::pac::PORTG = [0, 1, 2, 3, 4],
77    }
78}
79
80#[cfg(any(feature = "atmega1280", feature = "atmega2560"))]
81avr_hal_generic::impl_port_traditional! {
82    enum Ports {
83        A: crate::pac::PORTA = [0, 1, 2, 3, 4, 5, 6, 7],
84        B: crate::pac::PORTB = [0, 1, 2, 3, 4, 5, 6, 7],
85        C: crate::pac::PORTC = [0, 1, 2, 3, 4, 5, 6, 7],
86        D: crate::pac::PORTD = [0, 1, 2, 3, 4, 5, 6, 7],
87        E: crate::pac::PORTE = [0, 1, 2, 3, 4, 5, 6, 7],
88        F: crate::pac::PORTF = [0, 1, 2, 3, 4, 5, 6, 7],
89        G: crate::pac::PORTG = [0, 1, 2, 3, 4, 5],
90        H: crate::pac::PORTH = [0, 1, 2, 3, 4, 5, 6, 7],
91        J: crate::pac::PORTJ = [0, 1, 2, 3, 4, 5, 6, 7],
92        K: crate::pac::PORTK = [0, 1, 2, 3, 4, 5, 6, 7],
93        L: crate::pac::PORTL = [0, 1, 2, 3, 4, 5, 6, 7],
94    }
95}
96
97#[cfg(any(feature = "atmega1284p", feature = "atmega164pa"))]
98avr_hal_generic::impl_port_traditional! {
99    enum Ports {
100        A: crate::pac::PORTA = [0, 1, 2, 3, 4, 5, 6, 7],
101        B: crate::pac::PORTB = [0, 1, 2, 3, 4, 5, 6, 7],
102        C: crate::pac::PORTC = [0, 1, 2, 3, 4, 5, 6, 7],
103        D: crate::pac::PORTD = [0, 1, 2, 3, 4, 5, 6, 7],
104    }
105}
106
107#[cfg(any(feature = "atmega8"))]
108avr_hal_generic::impl_port_traditional_old! {
109    enum Ports {
110        B: crate::pac::PORTB = [0, 1, 2, 3, 4, 5, 6, 7],
111        C: crate::pac::PORTC = [0, 1, 2, 3, 4, 5, 6],
112        D: crate::pac::PORTD = [0, 1, 2, 3, 4, 5, 6, 7],
113    }
114}
atmega_hal/port.rs

atmega_hal/
port.rs
